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REJ09B0413-0200
The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
32
H8SX/1658R Group, H8SX/1658M Group
Hardware Manual
Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series H8SX/1658R H8SX/1654R H8SX/1653R H8SX/1658M H8SX/1654M H8SX/1653M R5F61658R R5F61654R R5F61653R R5F61658M R5F61654M R5F61653M
All information contained in this material, including products and product specifications at the time of publication of this material, is subject to change by Renesas Technology Corp. without notice. Please review the latest information published by Renesas Technology Corp. through various means, including the Renesas Technology Corp. website (http://www.renesas.com).
Rev.2.00 Revision Date: Sep. 25, 2008
Rev. 2.00 Sep. 25, 2008 Page ii of xxx
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 2.00 Sep. 25, 2008 Page iii of xxx
General Precautions in the Handling of MPU/MCU Products
The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1. Handling of Unused Pins Handle unused pins in accord with the directions given under Handling of Unused Pins in the manual. The input pins of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur due to the false recognition of the pin state as an input signal become possible. Unused pins should be handled as described under Handling of Unused Pins in the manual. 2. Processing at Power-on The state of the product is undefined at the moment when power is supplied. The states of internal circuits in the LSI are indeterminate and the states of register settings and pins are undefined at the moment when power is supplied. In a finished product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the moment when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset by an on-chip power-on reset function are not guaranteed from the moment when power is supplied until the power reaches the level at which resetting has been specified. 3. Prohibition of Access to Reserved Addresses Access to reserved addresses is prohibited. The reserved addresses are provided for the possible future expansion of functions. Do not access these addresses; the correct operation of LSI is not guaranteed if they are accessed. 4. Clock Signals After applying a reset, only release the reset line after the operating clock signal has become stable. When switching the clock signal during program execution, wait until the target clock signal has stabilized. When the clock signal is generated with an external resonator (or from an external oscillator) during a reset, ensure that the reset line is only released after full stabilization of the clock signal. Moreover, when switching to a clock signal produced with an external resonator (or by an external oscillator) while program execution is in progress, wait until the target clock signal is stable. 5. Differences between Products Before changing from one product to another, i.e. to one with a different type number, confirm that the change will not lead to problems. The characteristics of MPU/MCU in the same group but having different type numbers may differ because of the differences in internal memory capacity and layout pattern. When changing to products of different type numbers, implement a system-evaluation test for each of the products.
Rev. 2.00 Sep. 25, 2008 Page iv of xxx
How to Use This Manual
1. Objective and Target Users This manual was written to explain the hardware functions and electrical characteristics of this LSI to the target users, i.e. those who will be using this LSI in the design of application systems. Target users are expected to understand the fundamentals of electrical circuits, logic circuits, and microcomputers. This manual is organized in the following items: an overview of the product, descriptions of the CPU, system control functions, and peripheral functions, electrical characteristics of the device, and usage notes.
When designing an application system that includes this LSI, take all points to note into account. Points to note are given in their contexts and at the final part of each section, and in the section giving usage notes.
The list of revisions is a summary of major points of revision or addition for earlier versions. It does not cover all revised items. For details on the revised points, see the actual locations in the manual.
The following documents have been prepared for the H8SX/1658R Group and the H8SX/1658M Group. Before using any of the documents, please visit our web site to verify that you have the most up-to-date available version of the document.
Document Type Data Sheet Hardware Manual Contents Document Title Document No. This manual
Overview of hardware and electrical characteristics Hardware specifications (pin assignments, memory maps, peripheral specifications, electrical characteristics, and timing charts) and descriptions of operation Detailed descriptions of the CPU and instruction set Examples of applications and sample programs Preliminary report on the specifications of a product, document, etc. H8SX/1658R, H8SX/1658M Group Hardware Manual
Software Manual Application Note Renesas Technical Update
H8SX Family Software Manual
REJ09B0102
The latest versions are available from our web site.
Rev. 2.00 Sep. 25, 2008 Page v of xxx
2. Description of Numbers and Symbols Aspects of the notations for register names, bit names, numbers, and symbolic names in this manual are explained below.
(1) Overall notation In descriptions involving the names of bits and bit fields within this manual, the modules and registers to which the bits belong may be clarified by giving the names in the forms "module name"."register name"."bit name" or "register name"."bit name". (2) Register notation The style "register name"_"instance number" is used in cases where there is more than one instance of the same function or similar functions. [Example] CMCSR_0: Indicates the CMCSR register for the compare-match timer of channel 0. (3) Number notation Binary numbers are given as B'nnnn (B' may be omitted if the number is obviously binary), hexadecimal numbers are given as H'nnnn or 0xnnnn, and decimal numbers are given as nnnn. [Examples] Binary: B'11 or 11 Hexadecimal: H'EFA0 or 0xEFA0 Decimal: 1234 (4) Notation for active-low An overbar on the name indicates that a signal or pin is active-low. [Example] WDTOVF
(4) (2)
14.2.2 Compare Match Control/Status Register_0, _1 (CMCSR_0, CMCSR_1)
CMCSR indicates compare match generation, enables or disables interrupts, and selects the counter input clock. Generation of a WDTOVF signal or interrupt initializes the TCNT value to 0.
14.3 Operation
14.3.1 Interval Count Operation
When an internal clock is selected with the CKS1 and CKS0 bits in CMCSR and the STR bit in CMSTR is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and the compare match constant register (CMCOR) match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the CKS1 and CKS0 bits are set to B'01 at this time, a f/4 clock is selected.
Rev. 0.50, 10/04, page 416 of 914
(3)
Note: The bit names and sentences in the above figure are examples and have nothing to do with the contents of this manual.
Rev. 2.00 Sep. 25, 2008 Page vi of xxx
3. Description of Registers Each register description includes a bit chart, illustrating the arrangement of bits, and a table of bits, describing the meanings of the bit settings. The standard format and notation for bit charts and tables are described below.
[Bit Chart]
Bit: 15 Initial value: R/W: 0 R/W 14 0 R/W 13 12 11 10 0 R 9 1 R 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 Q 0 R/W 3 2 1 0 IFE 0 R/W
ASID2 ASID1 ASID0 0 R/W 0 R/W 0 R/W
ACMP2 ACMP1 ACMP0 0 R/W 0 R/W 0 R/W
[Table of Bits]
(1) Bit 15 14 13 to 11 10 9
(2) Bit Name - - ASID2 to ASID0 - - -
(3)
(4) Description
(5) Reserved These bits are always read as 0. Address Identifier These bits enable or disable the pin function. Reserved This bit is always read as 0. Reserved This bit is always read as 1.
Initial Value R/W 0 0 All 0 0 1 0 R R R/W R R
Note: The bit names and sentences in the above figure are examples, and have nothing to do with the contents of this manual.
(1) Bit Indicates the bit number or numbers. In the case of a 32-bit register, the bits are arranged in order from 31 to 0. In the case of a 16-bit register, the bits are arranged in order from 15 to 0. (2) Bit name Indicates the name of the bit or bit field. When the number of bits has to be clearly indicated in the field, appropriate notation is included (e.g., ASID[3:0]). A reserved bit is indicated by "-". Certain kinds of bits, such as those of timer counters, are not assigned bit names. In such cases, the entry under Bit Name is blank. (3) Initial value Indicates the value of each bit immediately after a power-on reset, i.e., the initial value. 0: The initial value is 0 1: The initial value is 1 -: The initial value is undefined (4) R/W For each bit and bit field, this entry indicates whether the bit or field is readable or writable, or both writing to and reading from the bit or field are impossible. The notation is as follows: R/W: The bit or field is readable and writable. R/(W): The bit or field is readable and writable. However, writing is only performed to flag clearing. R: The bit or field is readable. "R" is indicated for all reserved bits. When writing to the register, write the value under Initial Value in the bit chart to reserved bits or fields. W: The bit or field is writable. (5) Description Describes the function of the bit or field and specifies the values for writing.
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4. Description of Abbreviations The abbreviations used in this manual are listed below.
*
Abbreviations specific to this product
Description Bus controller Clock pulse generator Data transfer controller Interrupt controller Programmable pulse generator Serial communications interface 8-bit timer 16-bit timer pulse unit Watchdog timer
Abbreviation BSC CPG DTC INTC PPG SCI TMR TPU WDT
* Abbreviations other than those listed above
Abbreviation ACIA bps CRC DMA DMAC GSM Hi-Z IEBus I/O IrDA LSB MSB NC PLL PWM SFR SIM UART VCO Description Asynchronous communications interface adapter Bits per second Cyclic redundancy check Direct memory access Direct memory access controller Global System for Mobile Communications High impedance Inter Equipment Bus (IEBus is a trademark of NEC Electronics Corporation.) Input/output Infrared Data Association Least significant bit Most significant bit No connection Phase-locked loop Pulse width modulation Special function register Subscriber Identity Module Universal asynchronous receiver/transmitter Voltage-controlled oscillator
All trademarks and registered trademarks are the property of their respective owners.
Rev. 2.00 Sep. 25, 2008 Page viii of xxx
Contents
Section 1 Overview................................................................................................1
1.1 Features................................................................................................................................. 1 1.1.1 Applications .......................................................................................................... 1 1.1.2 Overview of Functions.......................................................................................... 2 List of Products..................................................................................................................... 9 Block Diagram.................................................................................................................... 11 Pin Assignments ................................................................................................................. 12 1.4.1 Pin Assignments ................................................................................................. 12 1.4.2 Correspondence between Pin Configuration and Operating Modes ................... 13 1.4.3 Pin Functions ...................................................................................................... 19
1.2 1.3 1.4
Section 2 CPU......................................................................................................25
2.1 2.2 Features............................................................................................................................... 25 CPU Operating Modes........................................................................................................ 27 2.2.1 Normal Mode...................................................................................................... 27 2.2.2 Middle Mode....................................................................................................... 29 2.2.3 Advanced Mode.................................................................................................. 30 2.2.4 Maximum Mode ................................................................................................. 31 Instruction Fetch ................................................................................................................. 33 Address Space..................................................................................................................... 33 Registers ............................................................................................................................. 34 2.5.1 General Registers................................................................................................ 35 2.5.2 Program Counter (PC) ........................................................................................ 36 2.5.3 Condition-Code Register (CCR)......................................................................... 37 2.5.4 Extended Control Register (EXR) ...................................................................... 38 2.5.5 Vector Base Register (VBR)............................................................................... 39 2.5.6 Short Address Base Register (SBR).................................................................... 39 2.5.7 Multiply-Accumulate Register (MAC) ............................................................... 39 2.5.8 Initial Values of CPU Registers .......................................................................... 39 Data Formats....................................................................................................................... 40 2.6.1 General Register Data Formats ........................................................................... 40 2.6.2 Memory Data Formats ........................................................................................ 42 Instruction Set ..................................................................................................................... 43 2.7.1 Instructions and Addressing Modes.................................................................... 45 2.7.2 Table of Instructions Classified by Function ...................................................... 49 2.7.3 Basic Instruction Formats ................................................................................... 59
2.3 2.4 2.5
2.6
2.7
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2.8
2.9
Addressing Modes and Effective Address Calculation....................................................... 60 2.8.1 Register Direct--Rn ........................................................................................... 60 2.8.2 Register Indirect--@ERn................................................................................... 61 2.8.3 Register Indirect with Displacement --@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn)...................................................................................................... 61 2.8.4 Index Register Indirect with Displacement--@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L) ................................................................................................... 61 2.8.5 Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement--@ERn+, @-ERn, @+ERn, or @ERn-................................. 62 2.8.6 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32................................... 63 2.8.7 Immediate--#xx ................................................................................................. 64 2.8.8 Program-Counter Relative--@(d:8, PC) or @(d:16, PC) .................................. 64 2.8.9 Program-Counter Relative with Index Register--@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC)....................................................................... 64 2.8.10 Memory Indirect--@@aa:8 ............................................................................... 65 2.8.11 Extended Memory Indirect--@@vec:7 ............................................................. 66 2.8.12 Effective Address Calculation ............................................................................ 66 2.8.13 MOVA Instruction.............................................................................................. 68 Processing States ................................................................................................................ 69
Section 3 MCU Operating Modes ....................................................................... 71
3.1 3.2 Operating Mode Selection .................................................................................................. 71 Register Descriptions.......................................................................................................... 73 3.2.1 Mode Control Register (MDCR) ........................................................................ 73 3.2.2 System Control Register (SYSCR)..................................................................... 75 Operating Mode Descriptions ............................................................................................. 77 3.3.1 Mode 1................................................................................................................ 77 3.3.2 Mode 2................................................................................................................ 77 3.3.3 Mode 3................................................................................................................ 77 3.3.4 Mode 4................................................................................................................ 77 3.3.5 Mode 5................................................................................................................ 78 3.3.6 Mode 6................................................................................................................ 78 3.3.7 Mode 7................................................................................................................ 78 3.3.8 Pin Functions ...................................................................................................... 79 Address Map....................................................................................................................... 79 3.4.1 Address Map....................................................................................................... 79
3.3
3.4
Section 4 Reset .................................................................................................... 87
4.1 Types of Reset .................................................................................................................... 87
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4.2 4.3
4.4 4.5 4.6 4.7 4.8 4.9
Input/Output Pin ................................................................................................................. 89 Register Descriptions.......................................................................................................... 90 4.3.1 Reset Status Register (RSTSR)........................................................................... 90 4.3.2 Reset Control/Status Register (RSTCSR)........................................................... 92 Pin Reset ............................................................................................................................. 93 Power-on Reset (POR) (H8SX/1658M Group) .................................................................. 93 Power Supply Monitoring Reset (H8SX/1658M Group).................................................... 94 Deep Software Standby Reset............................................................................................. 95 Watchdog Timer Reset ....................................................................................................... 95 Determination of Reset Generation Source......................................................................... 95
Section 5 Voltage Detection Circuit (LVD) ........................................................97
5.1 5.2 Features............................................................................................................................... 97 Register Descriptions.......................................................................................................... 98 5.2.1 Voltage Detection Control Register (LVDCR)................................................... 98 5.2.2 Reset Status Register (RSTSR)........................................................................... 99 Voltage Detection Circuit ................................................................................................. 101 5.3.1 Voltage Monitoring Reset................................................................................. 101 5.3.2 Voltage Monitoring Interrupt............................................................................ 102 5.3.3 Release from Deep Software Standby Mode by the Voltage-Detection Circuit ............................................................................................................... 104 5.3.4 Voltage Monitor................................................................................................ 104
5.3
Section 6 Exception Handling ...........................................................................105
6.1 6.2 6.3 Exception Handling Types and Priority............................................................................ 105 Exception Sources and Exception Handling Vector Table ............................................... 106 Reset ................................................................................................................................. 108 6.3.1 Reset Exception Handling................................................................................. 108 6.3.2 Interrupts after Reset......................................................................................... 109 6.3.3 On-Chip Peripheral Functions after Reset Release ........................................... 109 Traces................................................................................................................................ 111 Address Error.................................................................................................................... 112 6.5.1 Address Error Source........................................................................................ 112 6.5.2 Address Error Exception Handling ................................................................... 114 Interrupts........................................................................................................................... 116 6.6.1 Interrupt Sources............................................................................................... 116 6.6.2 Interrupt Exception Handling ........................................................................... 116 Instruction Exception Handling ........................................................................................ 117 6.7.1 Trap Instruction................................................................................................. 117 6.7.2 Sleep Instruction Exception Handling .............................................................. 118
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6.4 6.5
6.6
6.7
6.8 6.9
6.7.3 Exception Handling by Illegal Instruction ........................................................ 119 Stack Status after Exception Handling ............................................................................. 120 Usage Note ....................................................................................................................... 121
Section 7 Interrupt Controller............................................................................ 123
7.1 7.2 7.3 Features............................................................................................................................. 123 Input/Output Pins.............................................................................................................. 125 Register Descriptions........................................................................................................ 125 7.3.1 Interrupt Control Register (INTCR) ................................................................. 126 7.3.2 CPU Priority Control Register (CPUPCR) ....................................................... 127 7.3.3 Interrupt Priority Registers A to C, E to O, Q, and R (IPRA to IPRC, IPRE to IPRO, IPRQ, and IPRR)...................................................................... 129 7.3.4 IRQ Enable Register (IER) ............................................................................... 131 7.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL).................................. 133 7.3.6 IRQ Status Register (ISR)................................................................................. 138 7.3.7 Software Standby Release IRQ Enable Register (SSIER) ................................ 140 Interrupt Sources............................................................................................................... 141 7.4.1 External Interrupts ............................................................................................ 141 7.4.2 Internal Interrupts ............................................................................................. 142 Interrupt Exception Handling Vector Table...................................................................... 143 Interrupt Control Modes and Interrupt Operation............................................................. 149 7.6.1 Interrupt Control Mode 0.................................................................................. 149 7.6.2 Interrupt Control Mode 2.................................................................................. 151 7.6.3 Interrupt Exception Handling Sequence ........................................................... 153 7.6.4 Interrupt Response Times ................................................................................. 154 7.6.5 DTC and DMAC Activation by Interrupt ......................................................... 155 CPU Priority Control Function Over DTC, DMAC, and EXDMAC ............................... 158 Usage Notes ...................................................................................................................... 161 7.8.1 Conflict between Interrupt Generation and Disabling ...................................... 161 7.8.2 Instructions that Disable Interrupts................................................................... 162 7.8.3 Times when Interrupts are Disabled ................................................................. 162 7.8.4 Interrupts during Execution of EEPMOV Instruction ...................................... 162 7.8.5 Interrupts during Execution of MOVMD and MOVSD Instructions................ 162 7.8.6 Interrupts of Peripheral Modules ...................................................................... 163
7.4
7.5 7.6
7.7 7.8
Section 8 User Break Controller (UBC)............................................................ 165
8.1 8.2 8.3 Features............................................................................................................................. 165 Block Diagram.................................................................................................................. 166 Register Descriptions........................................................................................................ 167 8.3.1 Break Address Register n (BARA, BARB, BARC, BARD) ............................ 168
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8.4
8.5
8.3.2 Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD) .... 169 8.3.3 Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD) ................... 170 Operation .......................................................................................................................... 172 8.4.1 Setting of Break Control Conditions................................................................. 172 8.4.2 PC Break........................................................................................................... 172 8.4.3 Condition Match Flag ....................................................................................... 173 Usage Notes ...................................................................................................................... 174
Section 9 Bus Controller (BSC).........................................................................177
9.1 9.2 Features............................................................................................................................. 177 Register Descriptions........................................................................................................ 180 9.2.1 Bus Width Control Register (ABWCR)............................................................ 181 9.2.2 Access State Control Register (ASTCR) .......................................................... 182 9.2.3 Wait Control Registers A and B (WTCRA, WTCRB) ..................................... 183 9.2.4 Read Strobe Timing Control Register (RDNCR) ............................................. 188 9.2.5 CS Assertion Period Control Registers (CSACR) ............................................ 189 9.2.6 Idle Control Register (IDLCR) ......................................................................... 192 9.2.7 Bus Control Register 1 (BCR1) ........................................................................ 194 9.2.8 Bus Control Register 2 (BCR2) ........................................................................ 196 9.2.9 Endian Control Register (ENDIANCR)............................................................ 197 9.2.10 SRAM Mode Control Register (SRAMCR) ..................................................... 198 9.2.11 Burst ROM Interface Control Register (BROMCR)......................................... 199 9.2.12 Address/Data Multiplexed I/O Control Register (MPXCR) ............................. 201 Bus Configuration............................................................................................................. 202 Multi-Clock Function and Number of Access Cycles ...................................................... 203 External Bus...................................................................................................................... 207 9.5.1 Input/Output Pins.............................................................................................. 207 9.5.2 Area Division.................................................................................................... 210 9.5.3 Chip Select Signals ........................................................................................... 211 9.5.4 External Bus Interface....................................................................................... 212 9.5.5 Area and External Bus Interface ....................................................................... 216 9.5.6 Endian and Data Alignment.............................................................................. 221 Basic Bus Interface ........................................................................................................... 224 9.6.1 Data Bus............................................................................................................ 224 9.6.2 I/O Pins Used for Basic Bus Interface .............................................................. 224 9.6.3 Basic Timing..................................................................................................... 225 9.6.4 Wait Control ..................................................................................................... 231 9.6.5 Read Strobe (RD) Timing................................................................................. 233 9.6.6 Extension of Chip Select (CS) Assertion Period............................................... 234 9.6.7 DACK and EDACK Signal Output Timings .................................................... 236
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9.3 9.4 9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12 9.13
Byte Control SRAM Interface .......................................................................................... 237 9.7.1 Byte Control SRAM Space Setting................................................................... 237 9.7.2 Data Bus ........................................................................................................... 237 9.7.3 I/O Pins Used for Byte Control SRAM Interface ............................................. 238 9.7.4 Basic Timing..................................................................................................... 239 9.7.5 Wait Control ..................................................................................................... 241 9.7.6 Read Strobe (RD) ............................................................................................. 243 9.7.7 Extension of Chip Select (CS) Assertion Period............................................... 243 9.7.8 DACK and EDACK Signal Output Timings .................................................... 243 Burst ROM Interface ........................................................................................................ 245 9.8.1 Burst ROM Space Setting................................................................................. 245 9.8.2 Data Bus ........................................................................................................... 245 9.8.3 I/O Pins Used for Burst ROM Interface............................................................ 246 9.8.4 Basic Timing..................................................................................................... 247 9.8.5 Wait Control ..................................................................................................... 249 9.8.6 Read Strobe (RD) Timing................................................................................. 249 9.8.7 Extension of Chip Select (CS) Assertion Period............................................... 249 Address/Data Multiplexed I/O Interface........................................................................... 250 9.9.1 Address/Data Multiplexed I/O Space Setting ................................................... 250 9.9.2 Address/Data Multiplex.................................................................................... 250 9.9.3 Data Bus ........................................................................................................... 250 9.9.4 I/O Pins Used for Address/Data Multiplexed I/O Interface.............................. 251 9.9.5 Basic Timing..................................................................................................... 252 9.9.6 Address Cycle Control...................................................................................... 254 9.9.7 Wait Control ..................................................................................................... 255 9.9.8 Read Strobe (RD) Timing................................................................................. 255 9.9.9 Extension of Chip Select (CS) Assertion Period............................................... 257 9.9.10 DACK and EDACK Signal Output Timings .................................................... 259 Idle Cycle.......................................................................................................................... 260 9.10.1 Operation .......................................................................................................... 260 9.10.2 Pin States in Idle Cycle..................................................................................... 269 Bus Release....................................................................................................................... 270 9.11.1 Operation .......................................................................................................... 270 9.11.2 Pin States in External Bus Released State ........................................................ 271 9.11.3 Transition Timing ............................................................................................. 272 Internal Bus....................................................................................................................... 273 9.12.1 Access to Internal Address Space ..................................................................... 273 Write Data Buffer Function .............................................................................................. 274 9.13.1 Write Data Buffer Function for External Data Bus .......................................... 274 9.13.2 Write Data Buffer Function for Peripheral Modules ........................................ 275
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9.14
9.15 9.16
Bus Arbitration ................................................................................................................. 276 9.14.1 Operation .......................................................................................................... 276 9.14.2 Bus Transfer Timing ......................................................................................... 277 Bus Controller Operation in Reset .................................................................................... 280 Usage Notes ...................................................................................................................... 280
Section 10 DMA Controller (DMAC) ...............................................................283
10.1 10.2 10.3 Features............................................................................................................................. 283 Input/Output Pins.............................................................................................................. 286 Register Descriptions........................................................................................................ 287 10.3.1 DMA Source Address Register (DSAR)........................................................... 288 10.3.2 DMA Destination Address Register (DDAR)................................................... 289 10.3.3 DMA Offset Register (DOFR).......................................................................... 290 10.3.4 DMA Transfer Count Register (DTCR) ........................................................... 291 10.3.5 DMA Block Size Register (DBSR) .................................................................. 292 10.3.6 DMA Mode Control Register (DMDR)............................................................ 293 10.3.7 DMA Address Control Register (DACR) ......................................................... 302 10.3.8 DMA Module Request Select Register (DMRSR) ........................................... 308 Transfer Modes ................................................................................................................. 309 Operations......................................................................................................................... 310 10.5.1 Address Modes ................................................................................................. 310 10.5.2 Transfer Modes ................................................................................................. 314 10.5.3 Activation Sources............................................................................................ 319 10.5.4 Bus Access Modes ............................................................................................ 321 10.5.5 Extended Repeat Area Function ....................................................................... 323 10.5.6 Address Update Function using Offset ............................................................. 326 10.5.7 Register during DMA Transfer ......................................................................... 330 10.5.8 Priority of Channels .......................................................................................... 335 10.5.9 DMA Basic Bus Cycle...................................................................................... 337 10.5.10 Bus Cycles in Dual Address Mode ................................................................... 338 10.5.11 Bus Cycles in Single Address Mode................................................................. 347 DMA Transfer End ........................................................................................................... 352 Relationship among DMAC and Other Bus Masters ........................................................ 355 10.7.1 CPU Priority Control Function Over DMAC ................................................... 355 10.7.2 Bus Arbitration among DMAC and Other Bus Masters ................................... 356 Interrupt Sources............................................................................................................... 357 Usage Notes ...................................................................................................................... 360
10.4 10.5
10.6 10.7
10.8 10.9
Section 11 EXDMA Controller (EXDMAC) ....................................................361
11.1 Features............................................................................................................................. 361
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11.2 11.3
Input/Output Pins.............................................................................................................. 364 Registers Descriptions ...................................................................................................... 365 11.3.1 EXDMA Source Address Register (EDSAR)................................................... 367 11.3.2 EXDMA Destination Address Register (EDDAR)........................................... 368 11.3.3 EXDMA Offset Register (EDOFR).................................................................. 369 11.3.4 EXDMA Transfer Count Register (EDTCR).................................................... 370 11.3.5 EXDMA Block Size Register (EDBSR)........................................................... 371 11.3.6 EXDMA Mode Control Register (EDMDR) .................................................... 372 11.3.7 EXDMA Address Control Register (EDACR) ................................................. 381 11.3.8 Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7).................................... 387 11.4 Transfer Modes................................................................................................................. 388 11.4.1 Ordinary Modes ................................................................................................ 388 11.4.2 Cluster Transfer Modes .................................................................................... 389 11.5 Mode Operation ................................................................................................................ 390 11.5.1 Address Modes ................................................................................................. 390 11.5.2 Transfer Modes................................................................................................. 394 11.5.3 Activation Sources............................................................................................ 399 11.5.4 Bus Mode.......................................................................................................... 400 11.5.5 Extended Repeat Area Function ....................................................................... 401 11.5.6 Address Update Function Using Offset ............................................................ 404 11.5.7 Registers during EXDMA Transfer Operation ................................................. 408 11.5.8 Channel Priority Order...................................................................................... 413 11.5.9 Basic Bus Cycles .............................................................................................. 414 11.5.10 Bus Cycles in Dual Address Mode ................................................................... 415 11.5.11 Bus Cycles in Single Address Mode................................................................. 424 11.5.12 Operation Timing in Each Mode ...................................................................... 429 11.6 Operation in Cluster Transfer Mode ................................................................................. 440 11.6.1 Address Mode................................................................................................... 440 11.6.2 Setting of Address Update Mode...................................................................... 445 11.6.3 Caution for Combining with Extended Repeat Area Function ......................... 446 11.6.4 Bus Cycles in Cluster Transfer Dual Address Mode ........................................ 446 11.6.5 Operation Timing in Cluster Transfer Mode .................................................... 449 11.7 Ending EXDMA Transfer................................................................................................. 457 11.8 Relationship among EXDMAC and Other Bus Masters................................................... 460 11.8.1 CPU Priority Control Function Over EXDMAC .............................................. 460 11.8.2 Bus Arbitration with Another Bus Master ........................................................ 461 11.9 Interrupt Sources............................................................................................................... 462 11.10 Usage Notes ...................................................................................................................... 465
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Section 12 Data Transfer Controller (DTC) ......................................................467
12.1 12.2 Features............................................................................................................................. 467 Register Descriptions........................................................................................................ 469 12.2.1 DTC Mode Register A (MRA) ......................................................................... 470 12.2.2 DTC Mode Register B (MRB).......................................................................... 471 12.2.3 DTC Source Address Register (SAR)............................................................... 472 12.2.4 DTC Destination Address Register (DAR)....................................................... 473 12.2.5 DTC Transfer Count Register A (CRA) ........................................................... 473 12.2.6 DTC Transfer Count Register B (CRB)............................................................ 474 12.2.7 DTC enable registers A to F (DTCERA to DTCERF)...................................... 474 12.2.8 DTC Control Register (DTCCR) ...................................................................... 475 12.2.9 DTC Vector Base Register (DTCVBR)............................................................ 477 Activation Sources............................................................................................................ 477 Location of Transfer Information and DTC Vector Table ................................................ 477 Operation .......................................................................................................................... 482 12.5.1 Bus Cycle Division ........................................................................................... 484 12.5.2 Transfer Information Read Skip Function ........................................................ 486 12.5.3 Transfer Information Writeback Skip Function ................................................ 487 12.5.4 Normal Transfer Mode ..................................................................................... 487 12.5.5 Repeat Transfer Mode....................................................................................... 488 12.5.6 Block Transfer Mode ........................................................................................ 490 12.5.7 Chain Transfer .................................................................................................. 491 12.5.8 Operation Timing.............................................................................................. 492 12.5.9 Number of DTC Execution Cycles ................................................................... 494 12.5.10 DTC Bus Release Timing ................................................................................. 495 12.5.11 DTC Priority Level Control to the CPU ........................................................... 495 DTC Activation by Interrupt............................................................................................. 496 Examples of Use of the DTC ............................................................................................ 497 12.7.1 Normal Transfer Mode ..................................................................................... 497 12.7.2 Chain Transfer .................................................................................................. 497 12.7.3 Chain Transfer when Counter = 0..................................................................... 498 Interrupt Sources............................................................................................................... 500 Usage Notes ...................................................................................................................... 500 12.9.1 Module Stop State Setting ................................................................................ 500 12.9.2 On-Chip RAM .................................................................................................. 500 12.9.3 DMAC Transfer End Interrupt.......................................................................... 500 12.9.4 DTCE Bit Setting.............................................................................................. 500 12.9.5 Chain Transfer .................................................................................................. 501
12.3 12.4 12.5
12.6 12.7
12.8 12.9
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12.9.6 12.9.7 12.9.8 12.9.9
Transfer Information Start Address, Source Address, and Destination Address ............................................................................................................. 501 Transfer Information Modification ................................................................... 501 Endian Format .................................................................................................. 501 Points for Caution when Overwriting DTCER ................................................. 502
Section 13 I/O Ports........................................................................................... 503
13.1 Register Descriptions........................................................................................................ 510 13.1.1 Data Direction Register (PnDDR) (n = 1, 2, 6, A, B, D to F, H to K, and M)......................................................... 511 13.1.2 Data Register (PnDR) (n = 1, 2, 6, A, B, D to F, H to K, and M)..................... 512 13.1.3 Port Register (PORTn) (n = 1, 2, 5, 6, A, B, D to F, H to K, and M) ............... 512 13.1.4 Input Buffer Control Register (PnICR) (n = 1, 2, 5, 6, A, B, D to F, H to K, and M)............................................................................................................... 513 13.1.5 Pull-Up MOS Control Register (PnPCR) (n = D to F, and H to K).................. 514 13.1.6 Open-Drain Control Register (PnODR) (n = 2 and F)...................................... 515 Output Buffer Control....................................................................................................... 516 13.2.1 Port 1................................................................................................................. 516 13.2.2 Port 2................................................................................................................. 520 13.2.3 Port 5................................................................................................................. 524 13.2.4 Port 6................................................................................................................. 525 13.2.5 Port A................................................................................................................ 528 13.2.6 Port B................................................................................................................ 532 13.2.7 Port D................................................................................................................ 534 13.2.8 Port E ................................................................................................................ 535 13.2.9 Port F ................................................................................................................ 536 13.2.10 Port H................................................................................................................ 538 13.2.11 Port I ................................................................................................................. 539 13.2.12 Port J ................................................................................................................. 540 13.2.13 Port K................................................................................................................ 544 13.2.14 Port M ............................................................................................................... 548 Port Function Controller ................................................................................................... 557 13.3.1 Port Function Control Register 0 (PFCR0)....................................................... 558 13.3.2 Port Function Control Register 1 (PFCR1)....................................................... 559 13.3.3 Port Function Control Register 2 (PFCR2)....................................................... 560 13.3.4 Port Function Control Register 4 (PFCR4)....................................................... 562 13.3.5 Port Function Control Register 6 (PFCR6)....................................................... 563 13.3.6 Port Function Control Register 7 (PFCR7)....................................................... 564 13.3.7 Port Function Control Register 8 (PFCR8)....................................................... 565 13.3.8 Port Function Control Register 9 (PFCR9)....................................................... 566
13.2
13.3
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13.4
13.3.9 Port Function Control Register A (PFCRA) ..................................................... 567 13.3.10 Port Function Control Register B (PFCRB)...................................................... 569 13.3.11 Port Function Control Register C (PFCRC)...................................................... 571 13.3.12 Port Function Control Register D (PFCRD) ..................................................... 572 Usage Notes ...................................................................................................................... 573 13.4.1 Notes on Input Buffer Control Register (ICR) Setting ..................................... 573 13.4.2 Notes on Port Function Control Register (PFCR) Settings............................... 573
Section 14 16-Bit Timer Pulse Unit (TPU) .......................................................575
Features............................................................................................................................. 575 Input/Output Pins.............................................................................................................. 582 Register Descriptions........................................................................................................ 584 14.3.1 Timer Control Register (TCR).......................................................................... 589 14.3.2 Timer Mode Register (TMDR) ......................................................................... 594 14.3.3 Timer I/O Control Register (TIOR) .................................................................. 596 14.3.4 Timer Interrupt Enable Register (TIER) ........................................................... 630 14.3.5 Timer Status Register (TSR)............................................................................. 631 14.3.6 Timer Counter (TCNT)..................................................................................... 635 14.3.7 Timer General Register (TGR) ......................................................................... 635 14.3.8 Timer Start Register (TSTR) ............................................................................ 636 14.3.9 Timer Synchronous Register (TSYR)............................................................... 637 14.4 Operation .......................................................................................................................... 638 14.4.1 Basic Operation................................................................................................. 638 14.4.2 Synchronous Operation..................................................................................... 644 14.4.3 Buffer Operation ............................................................................................... 646 14.4.4 Cascaded Operation .......................................................................................... 650 14.4.5 PWM Modes ..................................................................................................... 652 14.4.6 Phase Counting Mode ....................................................................................... 658 14.5 Interrupt Sources............................................................................................................... 665 14.6 DTC Activation................................................................................................................. 667 14.7 DMAC Activation............................................................................................................. 667 14.8 A/D Converter Activation................................................................................................. 667 14.9 Operation Timing.............................................................................................................. 668 14.9.1 Input/Output Timing ......................................................................................... 668 14.9.2 Interrupt Signal Timing..................................................................................... 672 14.10 Usage Notes ...................................................................................................................... 676 14.10.1 Module Stop Function Setting .......................................................................... 676 14.10.2 Input Clock Restrictions ................................................................................... 676 14.10.3 Caution on Cycle Setting .................................................................................. 677 14.10.4 Conflict between TCNT Write and Clear Operations....................................... 677
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14.1 14.2 14.3
14.10.5 14.10.6 14.10.7 14.10.8 14.10.9 14.10.10 14.10.11 14.10.12 14.10.13 14.10.14
Conflict between TCNT Write and Increment Operations ............................... 678 Conflict between TGR Write and Compare Match........................................... 678 Conflict between Buffer Register Write and Compare Match .......................... 679 Conflict between TGR Read and Input Capture ............................................... 679 Conflict between TGR Write and Input Capture .............................................. 680 Conflict between Buffer Register Write and Input Capture.............................. 681 Conflict between Overflow/Underflow and Counter Clearing ......................... 682 Conflict between TCNT Write and Overflow/Underflow ................................ 682 Multiplexing of I/O Pins ................................................................................... 683 Interrupts in the Module Stop State .................................................................. 683
Section 15 Programmable Pulse Generator (PPG)............................................ 685
15.1 15.2 15.3 Features............................................................................................................................. 685 Input/Output Pins.............................................................................................................. 688 Register Descriptions........................................................................................................ 689 15.3.1 Next Data Enable Registers H, L (NDERH, NDERL) ..................................... 690 15.3.2 Output Data Registers H, L (PODRH, PODRL)............................................... 692 15.3.3 Next Data Registers H, L (NDRH, NDRL) ...................................................... 695 15.3.4 PPG Output Control Register (PCR) ................................................................ 699 15.3.5 PPG Output Mode Register (PMR) .................................................................. 701 Operation .......................................................................................................................... 705 15.4.1 Output Timing .................................................................................................. 705 15.4.2 Sample Setup Procedure for Normal Pulse Output........................................... 706 15.4.3 Example of Normal Pulse Output (Example of 5-Phase Pulse Output)............ 708 15.4.4 Non-Overlapping Pulse Output......................................................................... 709 15.4.5 Sample Setup Procedure for Non-Overlapping Pulse Output........................... 711 15.4.6 Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output)............................................................. 713 15.4.7 Inverted Pulse Output ....................................................................................... 715 15.4.8 Pulse Output Triggered by Input Capture ......................................................... 716 Usage Notes ...................................................................................................................... 717 15.5.1 Module Stop State Setting ................................................................................ 717 15.5.2 Operation of Pulse Output Pins......................................................................... 717 15.5.3 TPU Setting when PPG1 is in Use.................................................................... 717
15.4
15.5
Section 16 8-Bit Timers (TMR) ........................................................................ 719
16.1 16.2 16.3 Features............................................................................................................................. 719 Input/Output Pins.............................................................................................................. 724 Register Descriptions........................................................................................................ 725 16.3.1 Timer Counter (TCNT)..................................................................................... 727
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16.4
16.5
16.6
16.7
16.8
16.3.2 Time Constant Register A (TCORA)................................................................ 727 16.3.3 Time Constant Register B (TCORB) ................................................................ 728 16.3.4 Timer Control Register (TCR).......................................................................... 728 16.3.5 Timer Counter Control Register (TCCR) ......................................................... 730 16.3.6 Timer Control/Status Register (TCSR)............................................................. 735 Operation .......................................................................................................................... 739 16.4.1 Pulse Output...................................................................................................... 739 16.4.2 Reset Input ........................................................................................................ 740 Operation Timing.............................................................................................................. 741 16.5.1 TCNT Count Timing ........................................................................................ 741 16.5.2 Timing of CMFA and CMFB Setting at Compare Match................................. 742 16.5.3 Timing of Timer Output at Compare Match ..................................................... 742 16.5.4 Timing of Counter Clear by Compare Match ................................................... 743 16.5.5 Timing of TCNT External Reset*..................................................................... 743 16.5.6 Timing of Overflow Flag (OVF) Setting .......................................................... 744 Operation with Cascaded Connection............................................................................... 744 16.6.1 16-Bit Counter Mode ........................................................................................ 744 16.6.2 Compare Match Count Mode............................................................................ 745 Interrupt Sources............................................................................................................... 745 16.7.1 Interrupt Sources and DTC Activation ............................................................. 745 16.7.2 A/D Converter Activation................................................................................. 746 Usage Notes ...................................................................................................................... 747 16.8.1 Notes on Setting Cycle...................................................................................... 747 16.8.2 Conflict between TCNT Write and Counter Clear............................................ 747 16.8.3 Conflict between TCNT Write and Increment.................................................. 748 16.8.4 Conflict between TCOR Write and Compare Match ........................................ 748 16.8.5 Conflict between Compare Matches A and B................................................... 749 16.8.6 Switching of Internal Clocks and TCNT Operation.......................................... 749 16.8.7 Mode Setting with Cascaded Connection ......................................................... 751 16.8.8 Module Stop State Setting ................................................................................ 751 16.8.9 Interrupts in Module Stop State ........................................................................ 751
Section 17 Watchdog Timer (WDT)..................................................................753
17.1 17.2 17.3 Features............................................................................................................................. 753 Input/Output Pin ............................................................................................................... 754 Register Descriptions........................................................................................................ 755 17.3.1 Timer Counter (TCNT)..................................................................................... 755 17.3.2 Timer Control/Status Register (TCSR)............................................................. 755 17.3.3 Reset Control/Status Register (RSTCSR)......................................................... 757 Operation .......................................................................................................................... 758
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17.4
17.5 17.6
17.4.1 Watchdog Timer Mode..................................................................................... 758 17.4.2 Interval Timer Mode......................................................................................... 760 Interrupt Source ................................................................................................................ 760 Usage Notes ...................................................................................................................... 761 17.6.1 Notes on Register Access ................................................................................. 761 17.6.2 Conflict between Timer Counter (TCNT) Write and Increment....................... 762 17.6.3 Changing Values of Bits CKS2 to CKS0.......................................................... 762 17.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode............. 762 17.6.5 Internal Reset in Watchdog Timer Mode.......................................................... 763 17.6.6 System Reset by WDTOVF Signal................................................................... 763 17.6.7 Transition to Watchdog Timer Mode or Software Standby Mode.................... 763
Section 18 Serial Communication Interface (SCI, IrDA, CRC) ...................... 765
18.1 18.2 18.3 Features............................................................................................................................. 765 Input/Output Pins.............................................................................................................. 770 Register Descriptions........................................................................................................ 771 18.3.1 Receive Shift Register (RSR) ........................................................................... 773 18.3.2 Receive Data Register (RDR)........................................................................... 773 18.3.3 Transmit Data Register (TDR).......................................................................... 774 18.3.4 Transmit Shift Register (TSR) .......................................................................... 774 18.3.5 Serial Mode Register (SMR) ............................................................................ 774 18.3.6 Serial Control Register (SCR) .......................................................................... 778 18.3.7 Serial Status Register (SSR) ............................................................................. 783 18.3.8 Smart Card Mode Register (SCMR)................................................................. 792 18.3.9 Bit Rate Register (BRR) ................................................................................... 793 18.3.10 Serial Extended Mode Register (SEMR_2) ...................................................... 800 18.3.11 Serial Extended Mode Register 5 and 6 (SEMR_5 and SEMR_6)................... 802 18.3.12 IrDA Control Register (IrCR)........................................................................... 809 Operation in Asynchronous Mode .................................................................................... 810 18.4.1 Data Transfer Format........................................................................................ 811 18.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode................................................................................................................. 812 18.4.3 Clock................................................................................................................. 813 18.4.4 SCI Initialization (Asynchronous Mode).......................................................... 814 18.4.5 Serial Data Transmission (Asynchronous Mode) ............................................. 815 18.4.6 Serial Data Reception (Asynchronous Mode) .................................................. 817 Multiprocessor Communication Function ........................................................................ 821 18.5.1 Multiprocessor Serial Data Transmission ......................................................... 823 18.5.2 Multiprocessor Serial Data Reception .............................................................. 824 Operation in Clocked Synchronous Mode (SCI_0, 1, 2, and 4 only)................................ 827
18.4
18.5
18.6
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Clock................................................................................................................. 827 SCI Initialization (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)...... 828 Serial Data Transmission (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)............................................................................................................... 829 18.6.4 Serial Data Reception (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)................................................................................... 831 18.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only) .................................. 832 18.7 Operation in Smart Card Interface Mode.......................................................................... 834 18.7.1 Sample Connection ........................................................................................... 834 18.7.2 Data Format (Except in Block Transfer Mode) ................................................ 835 18.7.3 Block Transfer Mode ........................................................................................ 836 18.7.4 Receive Data Sampling Timing and Reception Margin.................................... 837 18.7.5 Initialization ...................................................................................................... 838 18.7.6 Data Transmission (Except in Block Transfer Mode) ...................................... 839 18.7.7 Serial Data Reception (Except in Block Transfer Mode).................................. 842 18.7.8 Clock Output Control (Only SCI_0, 1, 2, and 4) .............................................. 843 18.8 IrDA Operation ................................................................................................................. 845 18.9 Interrupt Sources............................................................................................................... 848 18.9.1 Interrupts in Normal Serial Communication Interface Mode ........................... 848 18.9.2 Interrupts in Smart Card Interface Mode .......................................................... 849 18.10 Usage Notes ...................................................................................................................... 851 18.10.1 Module Stop Function Setting .......................................................................... 851 18.10.2 Break Detection and Processing ....................................................................... 851 18.10.3 Mark State and Break Detection ....................................................................... 851 18.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)....................................................................................................... 851 18.10.5 Relation between Writing to TDR and TDRE Flag .......................................... 852 18.10.6 Restrictions on Using DTC or DMAC.............................................................. 852 18.10.7 SCI Operations during Power-Down State ....................................................... 853 18.11 CRC Operation Circuit ..................................................................................................... 856 18.11.1 Features............................................................................................................. 856 18.11.2 Register Descriptions ........................................................................................ 857 18.11.3 CRC Operation Circuit Operation..................................................................... 859 18.11.4 Note on CRC Operation Circuit........................................................................ 862
18.6.1 18.6.2 18.6.3
Section 19 USB Function Module (USB)..........................................................863
19.1 19.2 19.3 Features............................................................................................................................. 863 Input/Output Pins.............................................................................................................. 864 Register Descriptions........................................................................................................ 865
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19.4 19.5
19.6 19.7
19.3.1 Interrupt Flag Register 0 (IFR0) ....................................................................... 866 19.3.2 Interrupt Flag Register 1 (IFR1) ....................................................................... 868 19.3.3 Interrupt Flag Register 2 (IFR2) ....................................................................... 869 19.3.4 Interrupt Select Register 0 (ISR0)..................................................................... 871 19.3.5 Interrupt Select Register 1 (ISR1)..................................................................... 872 19.3.6 Interrupt Select Register 2 (ISR2)..................................................................... 873 19.3.7 Interrupt Enable Register 0 (IER0) ................................................................... 874 19.3.8 Interrupt Enable Register 1 (IER1) ................................................................... 875 19.3.9 Interrupt Enable Register 2 (IER2) ................................................................... 875 19.3.10 EP0i Data Register (EPDR0i)........................................................................... 876 19.3.11 EP0o Data Register (EPDR0o) ......................................................................... 877 19.3.12 EP0s Data Register (EPDR0s) .......................................................................... 877 19.3.13 EP1 Data Register (EPDR1) ............................................................................. 878 19.3.14 EP2 Data Register (EPDR2) ............................................................................. 878 19.3.15 EP3 Data Register (EPDR3) ............................................................................. 879 19.3.16 EP0o Receive Data Size Register (EPSZ0o) .................................................... 879 19.3.17 EP1 Receive Data Size Register (EPSZ1) ........................................................ 880 19.3.18 Trigger Register (TRG) .................................................................................... 880 19.3.19 Data Status Register (DASTS).......................................................................... 882 19.3.20 FIFO Clear Register (FCLR) ............................................................................ 883 19.3.21 DMA Transfer Setting Register (DMA) ........................................................... 884 19.3.22 Endpoint Stall Register (EPSTL)...................................................................... 887 19.3.23 Configuration Value Register (CVR) ............................................................... 888 19.3.24 Control Register (CTLR) .................................................................................. 888 19.3.25 Endpoint Information Register (EPIR) ............................................................. 890 19.3.26 Transceiver Test Register 0 (TRNTREG0) ...................................................... 894 19.3.27 Transceiver Test Register 1 (TRNTREG1) ...................................................... 896 Interrupt Sources............................................................................................................... 898 Operation .......................................................................................................................... 900 19.5.1 Cable Connection.............................................................................................. 900 19.5.2 Cable Disconnection ......................................................................................... 901 19.5.3 Suspend and Resume Operations...................................................................... 901 19.5.4 Control Transfer................................................................................................ 910 19.5.5 EP1 Bulk-Out Transfer (Dual FIFOs)............................................................... 916 19.5.6 EP2 Bulk-In Transfer (Dual FIFOs) ................................................................. 917 19.5.7 EP3 Interrupt-In Transfer.................................................................................. 919 Processing of USB Standard Commands and Class/Vendor Commands ......................... 920 19.6.1 Processing of Commands Transmitted by Control Transfer............................. 920 Stall Operations ................................................................................................................ 921 19.7.1 Overview .......................................................................................................... 921
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19.7.2 Forcible Stall by Application ............................................................................ 921 19.7.3 Automatic Stall by USB Function Module ....................................................... 923 19.8 DMA Transfer................................................................................................................... 924 19.8.1 Overview........................................................................................................... 924 19.8.2 DMA Transfer for Endpoint 1 .......................................................................... 924 19.8.3 DMA Transfer for Endpoint 2 .......................................................................... 925 19.9 Example of USB External Circuitry ................................................................................. 926 19.10 Usage Notes ...................................................................................................................... 928 19.10.1 Receiving Setup Data........................................................................................ 928 19.10.2 Clearing the FIFO ............................................................................................. 928 19.10.3 Overreading and Overwriting the Data Registers ............................................. 928 19.10.4 Assigning Interrupt Sources to EP0 .................................................................. 929 19.10.5 Clearing the FIFO When DMA Transfer is Enabled ........................................ 929 19.10.6 Notes on TR Interrupt ....................................................................................... 929 19.10.7 Restrictions on Peripheral Module Clock (P) Operating Frequency............... 930 19.10.8 Notes on Deep Software Standby Mode when USB is Used ............................ 930
Section 20 I2C Bus Interface 2 (IIC2) ................................................................931
20.1 20.2 20.3 Features............................................................................................................................. 931 Input/Output Pins.............................................................................................................. 933 Register Descriptions........................................................................................................ 934 20.3.1 I2C Bus Control Register A (ICCRA) ............................................................... 935 20.3.2 I2C Bus Control Register B (ICCRB)................................................................ 937 20.3.3 I2C Bus Mode Register (ICMR)........................................................................ 939 20.3.4 I2C Bus Interrupt Enable Register (ICIER) ....................................................... 940 20.3.5 I2C Bus Status Register (ICSR)......................................................................... 943 20.3.6 Slave Address Register (SAR).......................................................................... 946 20.3.7 I2C Bus Transmit Data Register (ICDRT)......................................................... 947 20.3.8 I2C Bus Receive Data Register (ICDRR).......................................................... 947 20.3.9 I2C Bus Shift Register (ICDRS)........................................................................ 947 Operation .......................................................................................................................... 948 20.4.1 I2C Bus Format.................................................................................................. 948 20.4.2 Master Transmit Operation ............................................................................... 949 20.4.3 Master Receive Operation................................................................................. 951 20.4.4 Slave Transmit Operation ................................................................................. 953 20.4.5 Slave Receive Operation................................................................................... 956 20.4.6 Noise Canceler.................................................................................................. 957 20.4.7 Example of Use................................................................................................. 958 Interrupt Request............................................................................................................... 962 Bit Synchronous Circuit.................................................................................................... 962
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20.4
20.5 20.6
20.7
Usage Notes ...................................................................................................................... 963
Section 21 A/D Converter ................................................................................. 965
21.1 21.2 21.3 Features............................................................................................................................. 965 Input/Output Pins.............................................................................................................. 968 Register Descriptions........................................................................................................ 969 21.3.1 A/D Data Registers A to H (ADDRA to ADDRH) .......................................... 970 21.3.2 A/D Control/Status Register for Unit 0 (ADCSR_0)........................................ 971 21.3.3 A/D Control/Status Register for Unit 1 (ADCSR_1)........................................ 973 21.3.4 A/D Control Register for Unit 0 (ADCR_0)..................................................... 975 21.3.5 A/D Control Register for Unit 1 (ADCR_1)..................................................... 977 Operation .......................................................................................................................... 979 21.4.1 Single Mode...................................................................................................... 979 21.4.2 Scan Mode ........................................................................................................ 980 21.4.3 Input Sampling and A/D Conversion Time ...................................................... 983 21.4.4 External Trigger Input Timing.......................................................................... 985 Interrupt Source ................................................................................................................ 987 A/D Conversion Accuracy Definitions ............................................................................. 988 Usage Notes ...................................................................................................................... 990 21.7.1 Module Stop Function Setting .......................................................................... 990 21.7.2 A/D Input Hold Function in Software Standby Mode ...................................... 990 21.7.3 Notes on A/D Activation by an External Trigger ............................................. 990 21.7.4 Permissible Signal Source Impedance .............................................................. 991 21.7.5 Influences on Absolute Accuracy ..................................................................... 992 21.7.6 Setting Range of Analog Power Supply and Other Pins................................... 992 21.7.7 Notes on Board Design ..................................................................................... 993 21.7.8 Notes on Noise Countermeasures ..................................................................... 993
21.4
21.5 21.6 21.7
Section 22 D/A Converter ................................................................................. 995
22.1 22.2 22.3 Features............................................................................................................................. 995 Input/Output Pins.............................................................................................................. 996 Register Descriptions........................................................................................................ 996 22.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)......................................... 996 22.3.2 D/A Control Register 01 (DACR01) ................................................................ 997 Operation .......................................................................................................................... 999 Usage Notes .................................................................................................................... 1000 22.5.1 Module Stop State Setting .............................................................................. 1000 22.5.2 D/A Output Hold Function in Software Standby Mode.................................. 1000 22.5.3 Notes on Deep Software Standby Mode ......................................................... 1000
22.4 22.5
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Section 23 RAM ..............................................................................................1001 Section 24 Flash Memory ................................................................................1003
24.1 24.2 24.3 24.4 Features........................................................................................................................... 1003 Mode Transition Diagram............................................................................................... 1006 Memory MAT Configuration ......................................................................................... 1008 Block Structure ............................................................................................................... 1009 24.4.1 Block Diagram of H8SX/1653........................................................................ 1009 24.4.2 Block Diagram of H8SX/1654........................................................................ 1010 24.4.3 Block Diagram of H8SX/1658........................................................................ 1011 Programming/Erasing Interface ...................................................................................... 1012 Input/Output Pins............................................................................................................ 1014 Register Descriptions...................................................................................................... 1015 24.7.1 Programming/Erasing Interface Registers ...................................................... 1016 24.7.2 Programming/Erasing Interface Parameters ................................................... 1023 24.7.3 RAM Emulation Register (RAMER).............................................................. 1035 On-Board Programming Mode ....................................................................................... 1036 24.8.1 SCI Boot Mode ............................................................................................... 1036 24.8.2 USB Boot Mode.............................................................................................. 1040 24.8.3 User Programming Mode................................................................................ 1044 24.8.4 User Boot Mode.............................................................................................. 1054 24.8.5 On-Chip Program and Storable Area for Program Data ................................. 1058 Protection........................................................................................................................ 1064 24.9.1 Hardware Protection ....................................................................................... 1064 24.9.2 Software Protection......................................................................................... 1065 24.9.3 Error Protection............................................................................................... 1065 Flash Memory Emulation Using RAM........................................................................... 1067 Switching between User MAT and User Boot MAT...................................................... 1070 Programmer Mode .......................................................................................................... 1071 Standard Serial Communications Interface Specifications for Boot Mode..................... 1071 Usage Notes .................................................................................................................... 1100
24.5 24.6 24.7
24.8
24.9
24.10 24.11 24.12 24.13 24.14
Section 25 Boundary Scan ...............................................................................1103
25.1 25.2 25.3 25.4 Features........................................................................................................................... 1103 Block Diagram of Boundary Scan Function ................................................................... 1104 Input/Output Pins............................................................................................................ 1104 Register Descriptions...................................................................................................... 1105 25.4.1 Instruction Register (JTIR) ............................................................................. 1106 25.4.2 Bypass Register (JTBPR) ............................................................................... 1107 25.4.3 Boundary Scan Register (JTBSR)................................................................... 1107
Rev. 2.00 Sep. 25, 2008 Page xxvii of xxx
25.5
25.6
25.4.4 IDCODE Register (JTID) ............................................................................... 1112 Operations....................................................................................................................... 1113 25.5.1 TAP Controller ............................................................................................... 1113 25.5.2 Commands ...................................................................................................... 1114 Usage Notes .................................................................................................................... 1116
Section 26 Clock Pulse Generator................................................................... 1117
26.1 26.2 Register Description ....................................................................................................... 1119 26.1.1 System Clock Control Register (SCKCR) ...................................................... 1119 Oscillator ........................................................................................................................ 1122 26.2.1 Connecting Crystal Resonator ........................................................................ 1122 26.2.2 External Clock Input....................................................................................... 1123 PLL Circuit ..................................................................................................................... 1124 Frequency Divider .......................................................................................................... 1124 Usage Notes .................................................................................................................... 1125 26.5.1 Notes on Clock Pulse Generator ..................................................................... 1125 26.5.2 Notes on Resonator......................................................................................... 1126 26.5.3 Notes on Board Design ................................................................................... 1126
26.3 26.4 26.5
Section 27 Power-Down Modes...................................................................... 1129
27.1 27.2 Features........................................................................................................................... 1129 Register Descriptions...................................................................................................... 1133 27.2.1 Standby Control Register (SBYCR) ............................................................... 1133 27.2.2 Module Stop Control Registers A and B (MSTPCRA and MSTPCRB) ........ 1136 27.2.3 Module Stop Control Register C (MSTPCRC)............................................... 1139 27.2.4 Deep Standby Control Register (DPSBYCR)................................................. 1140 27.2.5 Deep Standby Wait Control Register (DPSWCR).......................................... 1143 27.2.6 Deep Standby Interrupt Enable Register (DPSIER) ....................................... 1145 27.2.7 Deep Standby Interrupt Flag Register (DPSIFR)............................................ 1147 27.2.8 Deep Standby Interrupt Edge Register (DPSIEGR) ....................................... 1149 27.2.9 Reset Status Register (RSTSR)....................................................................... 1150 27.2.10 Deep Standby Backup Register (DPSBKRn) ................................................. 1151 Multi-Clock Function ..................................................................................................... 1152 Module Stop State........................................................................................................... 1152 Sleep Mode ..................................................................................................................... 1153 27.5.1 Entry to Sleep Mode ....................................................................................... 1153 27.5.2 Exit from Sleep Mode..................................................................................... 1153 All-Module-Clock-Stop Mode........................................................................................ 1154 Software Standby Mode.................................................................................................. 1155 27.7.1 Entry to Software Standby Mode.................................................................... 1155
27.3 27.4 27.5
27.6 27.7
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27.7.2 Exit from Software Standby Mode ................................................................. 1155 27.7.3 Setting Oscillation Settling Time after Exit from Software Standby Mode.... 1156 27.7.4 Software Standby Mode Application Example............................................... 1158 27.8 Deep Software Standby Mode ........................................................................................ 1159 27.8.1 Entry to Deep Software Standby Mode .......................................................... 1159 27.8.2 Exit from Deep Software Standby Mode ........................................................ 1160 27.8.3 Pin State on Exit from Deep Software Standby Mode.................................... 1161 27.8.4 B Operation after Exit from Deep Software Standby Mode ......................... 1162 27.8.5 Setting Oscillation Settling Time after Exit from Deep Software Standby Mode ................................................................................................. 1163 27.8.6 Deep Software Standby Mode Application Example ..................................... 1165 27.8.7 Flowchart of Deep Software Standby Mode Operation .................................. 1169 27.9 Hardware Standby Mode ................................................................................................ 1171 27.9.1 Transition to Hardware Standby Mode ........................................................... 1171 27.9.2 Clearing Hardware Standby Mode.................................................................. 1171 27.9.3 Hardware Standby Mode Timing.................................................................... 1171 27.9.4 Timing Sequence at Power-On ....................................................................... 1172 27.10 Sleep Instruction Exception Handling ............................................................................ 1173 27.11 Clock Output Control................................................................................................ 1176 27.12 Usage Notes .................................................................................................................... 1177 27.12.1 I/O Port Status................................................................................................. 1177 27.12.2 Current Consumption during Oscillation Settling Standby Period ................. 1177 27.12.3 Module Stop State of EXDMAC, DMAC, or DTC ........................................ 1177 27.12.4 On-Chip Peripheral Module Interrupts ........................................................... 1177 27.12.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC ..................................... 1177 27.12.6 Control of Input Buffers by DIRQnE (n = 3 to 0)........................................... 1178 27.12.7 Conflict between a transition to deep software standby mode and interrupts ......................................................................................................... 1178 27.12.8 B Output State............................................................................................... 1178
Section 28 List of Registers .............................................................................1179
28.1 28.2 28.3 Register Addresses (Address Order)............................................................................... 1180 Register Bits.................................................................................................................... 1199 Register States in Each Operating Mode ........................................................................ 1230
Section 29 Electrical Characteristics ...............................................................1249
29.1 29.2 29.3 29.4 Absolute Maximum Ratings ........................................................................................... 1249 DC Characteristics H8SX/1658R Group ...................................................................... 1250 DC Characteristics H8SX/1658M Group...................................................................... 1254 AC Characteristics .......................................................................................................... 1257
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29.5 29.6 29.7 29.8 29.9
29.4.1 Clock Timing .................................................................................................. 1258 29.4.2 Control Signal Timing .................................................................................... 1261 29.4.3 Bus Timing ..................................................................................................... 1262 29.4.4 DMAC/EXDMAC Timing ............................................................................. 1277 29.4.5 Timing of On-Chip Peripheral Modules ......................................................... 1282 USB Characteristics........................................................................................................ 1289 A/D Conversion Characteristics ..................................................................................... 1291 D/A Conversion Characteristics ..................................................................................... 1291 Flash Memory Characteristics ........................................................................................ 1292 Power-On Reset Circuit and Voltage-Detection Circuit Characteristics (H8SX/1658M Group).................................................................................................... 1293
Appendix ........................................................................................................... 1295
A. B. C. D. Port States in Each Pin State........................................................................................... 1295 Product Lineup................................................................................................................ 1300 Package Dimensions....................................................................................................... 1301 Treatment of Unused Pins............................................................................................... 1302
Main Revisions and Additions in this Edition................................................... 1305 Index ................................................................................................................. 1333
Rev. 2.00 Sep. 25, 2008 Page xxx of xxx
Section 1 Overview
Section 1 Overview
1.1 Features
The core of each product in the H8SX/1658R Group and the H8SX/1658M Group of CISC (complex instruction set computer) microcontrollers is an H8SX CPU, which has an internal 32bit architecture. The H8SX CPU provides upward-compatibility with the CPUs of other Renesas Technology-original microcontrollers; H8/300, H8/300H, and H8S. As peripheral functions, each LSI of the Group includes a DMA controller and EXDMA controller which enables high-speed data transfer, and a bus-state controller, which enables direct connection to different kinds of memory. The LSI of the Group also includes serial communication interfaces, A/D and D/A converters, and a multi-function timer that makes motor control easy. Together, the modules realize low-cost configurations for end systems. The power consumption of these modules is kept down dynamically by an on-chip power-management function. The on-chip ROM is a flash memory (F-ZTATTM*) with a capacity of 1024 Kbytes (H8SX/1658R and H8SX/1658M), 512 Kbytes (H8SX/1654R and H8SX/1654M) or 384 Kbytes (H8SX/1653R and H8SX/1653M). Note: * F-ZTATTM is a trademark of Renesas Technology Corp. 1.1.1 Applications
Examples of the applications of this LSI include PC peripheral equipment, optical storage devices, office automation equipment, and industrial equipment.
Rev. 2.00 Sep. 25, 2008 Page 1 of 1340 REJ09B0413-0200
Section 1 Overview
1.1.2
Overview of Functions
Table 1.1 lists the functions of H8SX/1658R Group and H8SX/1658M Group products in outline. Table 1.2 shows the comparison of support functions in each group. Table 1.1 Overview of Functions
Module/ Function ROM RAM CPU CPU Description * * * ROM capacity: 1024 Kbytes, 512 Kbytes, or 384 Kbytes RAM capacity: 56 Kbytes or 40 Kbytes 32-bit high-speed H8SX CPU (CISC type) Upwardly compatible for H8/300, H8/300H, and H8S CPUs at object level * * * General-register architecture (sixteen 16-bit general registers) 11 addressing modes 4-Gbyte address space Program: 4 Gbytes available Data: 4 Gbytes available * 87 basic instructions, classifiable as bit arithmetic and logic instructions, multiply and divide instructions, bit manipulation instructions, multiply-and-accumulate instructions, and others Minimum instruction execution time: 20.0 ns (for an ADD instruction while system clock I = 50 MHz and VCC = 3.0 to 3.6 V) On-chip multiplier (16 x 16 32 bits) Supports multiply-and-accumulate instructions (16 x 16 + 42 42 bits) Advanced mode Normal, middle, or maximum mode is not supported.
Classification Memory
*
* * Operating mode *
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Section 1 Overview
Classification CPU
Module/ Function MCU operating mode
Description Mode 1: User boot mode (selected by driving the MD2 and MD1 pins low and driving the MD0 pin high) Mode 2: Boot mode (selected by driving the MD2 and MD0 pins low and driving the MD1 pin high) Mode 3: Boundary scan enabled single-chip mode (selected by driving the MD2 pin low and driving the MD1 and MD0 pins high) Mode 4: On-chip ROM disabled external extended mode, 16-bit bus (selected by driving the MD1 and MD0 pins low and driving the MD2 pin high) Mode 5: On-chip ROM disabled external extended mode, 8-bit bus (selected by driving the MD1 pin low and driving the MD2 and MD0 pins high) Mode 6: On-chip ROM enabled external extended mode (selected by driving the MD0 pin low and driving the MD2 and MD1 pins high) Mode 7: Single-chip mode (can be externally extended) (selected by driving the MD2, MD1, and MD0 pins high) * Low power consumption state (transition driven by the SLEEP instruction) At power-on or low power supply voltage, an internal reset signal is generated At low power supply voltage, an internal reset signal and an interrupt are generated 13 external interrupt pins (NMI, and IRQ11 to IRQ0) Internal interrupt sources H8SX/1658 Group: 120 pins H8SX/1658M Group: 121 pins * * * 2 interrupt control modes (specified by the interrupt control register) 8 priority orders specifiable (by setting the interrupt priority register) Independent vector addresses
Power on reset (POR)* Voltage detection circuit (LVD)* Interrupt (source) Interrupt controller (INTC)
* * * *
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Section 1 Overview
Classification Interrupt (source) DMA
Module/ Function Break interrupt (UBC)
Description * * Break point can be set for four channels Address break can be set for CPU instruction fetch cycles 4-channel DMA transfer available 2 activation methods (auto-request, external request) 4 transfer modes (normal transfer, repeat transfer, block transfer, cluster transfer) Dual or single address mode selectable Extended repeat-area function 4-channel DMA transfer available 3 activation methods (auto-request, on-chip module interrupt, external request) 3 transfer modes (normal transfer, repeat transfer, block transfer) Dual or single address mode selectable Extended repeat-area function Allows DMA transfer over 78 channels (number of DTC activation sources) Activated by interrupt sources (chain transfer enabled) 3 transfer modes (normal transfer, repeat transfer, block transfer mode) Short-address mode or full-address mode selectable 16-Mbyte external address space The external address space can be divided into 8 areas, each of which is independently controllable Chip-select signals (CS0 to CS7) can be output Access in 2 or 3 states can be selected for each area Program wait cycles can be inserted The period of CS assertion can be extended Idle cycles can be inserted * Bus arbitration function (arbitrates bus mastership among the internal CPU, DMAC, EXDMAC, and DTC, and external bus masters)
EXDMA * controller * (EXDMAC) * * * DMA controller (DMAC) * * * * * Data transfer controller (DTC) * * * *
External bus extension
Bus controller (BSC)
* *
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Section 1 Overview
Classification External bus extension
Module/ Function Bus controller (BSC)
Description Bus formats * * * External memory interfaces (for the connection of ROM, burst ROM, SRAM, and byte control SRAM) Address/data bus format: Support for both separate and multiplexed buses (8-bit access or 16-bit access) Endian conversion function for connecting devices in littleendian format 1 clock generation circuit available Separate clock signals are provided for each of functional modules (detailed below) and each is independently specifiable (multi-clock function) System-intended data transfer modules, i.e. the CPU, runs in synchronization with the system clock (I): 8 to 50 MHz Internal peripheral functions run in synchronization with the peripheral module clock (P): 8 to 35 MHz Modules in the external space are supplied with the external bus clock (B): 8 to 50 MHz * * Includes a PLL frequency multiplication circuit and frequency divider, so the operating frequency is selectable 5 low-power-consumption modes: Sleep mode, all-moduleclock-stop mode, software standby mode, deep software standby mode, and hardware standby mode
Clock
Clock pulse * generator * (CPG)
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Section 1 Overview
Classification A/D converter
Module/ Function A/D converter (ADC)
Description * * 10-bit resolution x 2 units Selectable input channel and unit configuration 4 channels x 2 units (units 0 and 1) 8 channels x one unit (unit 0) Sample and hold function included Conversion time: 2.7 s per channel (with peripheral module clock (P) at 25-MHz operation) 2 operating modes: single mode and scan mode 3 ways to start A/D conversion: Unit 0: Software, timer (TPU (unit 0) /TMR (units 0 and 1)) trigger, and external trigger Unit 1: Software, TMR (units 2 and 3) trigger, and external trigger Activation of DTC and DMAC by ADI interrupt: Unit 0: DTC and DMAC can be activated by an ADI interrupt. Unit 1: DMAC can be activated by an ADI1 interrupt.
* * * *
*
D/A converter
D/A converter (DAC) 8-bit timer (TMR)
* * * *
8-bit resolution x 2 output channels Output voltage: 0 V to Vref, maximum conversion time: 10 s (with 20-pF load)
Timer
8 bits x 8 channels (can be used as 16 bits x four channels) Select from among 7 clock sources (6 internal clocks and 1 external clock) * Allows the output of pulse trains with a desired duty cycle or PWM signals 16-bit timer * 16 bits x 12 channels (unit 0, unit 1*) pulse unit * Select from among 8 counter-input clocks for each channel (TPU) * Up to 24 pulse inputs and outputs * Counter clear operation, simultaneous writing to multiple timer counters (TCNT), simultaneous clearing by compare match and input capture possible, simultaneous input/output for registers possible by counter synchronous operation, and up to 15-phase PWM output possible by combination with synchronous operation * Buffered operation, cascaded operation (32 bits x two channels), and phase counting mode (two-phase encoder input) settable for each channel * Input capture function supported * Output compare function (by the output of compare match waveform) supported Note: * Pin function of unit 1 cannot be used in the external bus extended mode.
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Section 1 Overview
Classification Timer
Module/ Function
Description
12 24-bit* * pulse output 4 output groups, non-overlapping mode, and inverted output can be set Selectable output trigger signals; the PPG can operate in conjunction with the data transfer controller (DTC) and the DMA controller (DMAC) Notes: 1. Pulse output pins PO31 to PO16 cannot be activated by input capture. 2. Pulse of unit 1 cannot be output in the external bus extended mode.
* Programmable pulse * generator (PPG) *
Watchdog timer Watchdog timer (WDT) Serial interface Serial communications interface (SCI)
* * * * * * * *
8 bits x one channel (selectable from eight counter input clocks) Switchable between watchdog timer mode and interval timer mode 6 channels (select asynchronous or clock synchronous serial communications mode) Full-duplex communications capability Select the desired bit rate and LSB-first or MSB-first transfer Average transfer rate clock input from TMR (SCI_5, SCI_6) IrDA transmission and reception conformant with the IrDA Specifications version 1.0 On-chip cyclic redundancy check (CRC) calculator for improved reliability in data transfer The SCI module supports a smart card (SIM) interface. 2 channels Bus can be directly driven (the SCL and SDA pins are NMOS open drains). On-chip UDC (USB Device Controller) supporting USB 2.0 and transceiver Transfer speed: full-speed (12 Mbps) Bulk transfer by DMA Self-power mode and bus power mode selectable 9 CMOS input-only pins 75 CMOS input/output pins 8 large-current drive pins (port 3) 40 pull-up resistors 16 open drains LQFP-120 package
Smart card/SIM I C bus interface I C bus interface 2 (IIC2) Universal serial Universal bus interface serial bus interface (USB)
2 2
* * * * * * *
I/O ports
Package
* * * * * *
Rev. 2.00 Sep. 25, 2008 Page 7 of 1340 REJ09B0413-0200
Section 1 Overview
Classification
Module/ Function
Description * * * * Operating frequency: 8 to 50 MHz Power supply voltage: VCC = PLLVCC = DrVCC = 3.0 to 3.6 V, AVCC = 3.0 to 3.6 V Flash programming/erasure voltage: 3.0 to 3.6 V Supply current: 50 mA (typ.) (VCC = PLLVCC = DrVCC = 3.0 V, AVCC = 3.0 V, I = P = B = 35 MHz )
Operating frequency/ Power supply voltage
Operating peripheral temperature (C) Note *
* *
-20 to +75C (regular specifications) -40 to +85C (wide-range specifications)
Supported only by the H8SX/1658M Group.
Table 1.2
Function DMAC DTC PPG UBC SCI IIC2 TMR WDT 10-bit ADC 8-bit DAC EXDMAC POR/LVD Package
Comparison of Support Functions in the H8SX/1658R and H8SX/1658M Group
H8SX/1658R Group O O O O O O O O O O O LQFP-120 O H8SX/1658M Group O O O O O O O O O O O O O
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Section 1 Overview
1.2
List of Products
Table 1.3 is the list of products, and figure 1.1 shows how to read the product name code. Table 1.3
Group H8SX/1658R
List of Products
Part No. R5F61658RN50FPV R5F61654RN50FPV R5F61653RN50FPV R5F61658RD50FPV R5F61654RD50FPV R5F61653RD50FPV ROM Capacity 1024 Kbytes 512 Kbytes 384 Kbytes 1024 Kbytes 512 Kbytes 384 Kbytes 1024 Kbytes 512 Kbytes 384 Kbytes 1024 Kbytes 512 Kbytes 384 Kbytes RAM Capacity 56 Kbytes 40 Kbytes 40 Kbytes 56 Kbytes 40 Kbytes 40 Kbytes 56 Kbytes 40 Kbytes 40 Kbytes 56 Kbytes 40 Kbytes 40 Kbytes Package LQFP-120 LQFP-120 LQFP-120 LQFP-120 LQFP-120 LQFP-120 LQFP-120 LQFP-120 LQFP-120 LQFP-120 LQFP-120 LQFP-120 Wide range specifications Regular specifications Wide range specifications Remarks Regular specifications
H8SX/1658M
R5F61658MN50FPV R5F61654MN50FPV R5F61653MN50FPV R5F61658MD50FPV R5F61654MD50FPV R5F61653MD50FPV
Part No.
R
5
F 61658RN50 FP
V Indicates the Pb-free version. Indicates the package. FP: LQFP Indicates the product-specific number. N : Regular specifications D : Wide range specifications Indicates the type of ROM device. F: On-chip flash memory Product classification Microcontroller Indicates a Renesas semiconductor product.
Figure 1.1 How to Read the Product Name Code
Rev. 2.00 Sep. 25, 2008 Page 9 of 1340 REJ09B0413-0200
Section 1 Overview
* Small Package
Package LQFP-120 Note: * Pb-free version Package Code PLQP0120LA-A (FP-120BV)* Body Size 14.0 x 14.0 mm Pin Pitch 0.40 mm
Rev. 2.00 Sep. 25, 2008 Page 10 of 1340 REJ09B0413-0200
Section 1 Overview
1.3
Block Diagram
WDT TMR x 2 channels (unit 0) TMR x 2 channels (unit 1) TMR x 2 channels (unit 2) TMR x 2 channels (unit 3)
Internal peripheral bus
Port 1
Port 2
Interrupt controller RAM
Port 5
ROM
Internal system bus
BSC
TPU x 6 channels (unit 0) TPU x 6 channels (unit 1) PPG x 8 channels (unit 0) PPG x 16 channels (unit 1) SCI x 6 channels
Port 6
Port A
H8SX CPU
Port B
Port D/ port J*1
DTC
DMAC x 4 channels
USB IIC2 x 2 channels
Port E/ port K*1
EXDMAC x 4 channels
Internal system bus
Clock pulse generator
10-bit AD x 4 channels (unit 0) 10-bit AD x 4 channels (unit 1) 8-bit DA x 2 channels
Port F
Port H
Port I
POR/LVD*2
External bus
Port M
[Legend] CPU: DTC: BSC: DMAC: EXDMAC: WDT:
Central processing unit Data transfer controller Bus controller DMA controller EXDMA controller Watchdog timer
TMR: TPU: PPG: SCI: USB: IIC2: POR/LVD*2:
8-bit timer 16-bit timer pulse unit Programmable pulse generator Serial communications interface Universal serial bus interface IIC bus interface 2 Power-on reset / Low voltage detection circuit
Notes: 1. In single-chip mode, the port D and port E functions can be used in the initial state. Pin functions are selectable by setting the PCJKE bit in PFCRD. Ports D and E are enabled when PCJKE = 0 (initial value) and ports J and K are enabled when PCJKE = 1. In external extended mode, only ports D and E can be used. 2. Supported only by the H8SX/1658M Group.
Figure 1.2 Block Diagram
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Section 1 Overview
1.4
1.4.1
Pin Assignments
Pin Assignments
P61/TMCI2/RxD4/TEND2/IRQ9-B/ETEND0-B P60/TMRI2/TxD4/DREQ2/IRQ8-B/EDREQ0-B STBY P17/TCLKD-B/SCL0/ADTRG1/IRQ7-A/EDRAK1 P16/TCLKC-B/SDA0/DACK1/IRQ6-A/EDACK1-A Vcc EXTAL XTAL Vss WDTOVF/TDO P15/TCLKB-B/RxD5/IrRXD/SCL1/TEND1/IRQ5-A/ETEND1-A P14/TCLKA-B/TxD5/IrTXD/SDA1/DREQ1/IRQ4-A/EDREQ1-A VCL RES Vss P13/ADTRG0/IRQ3-A/EDRAK0 P12/SCK2/DACK0/IRQ2-A/EDACK0-A P11/RxD2/TEND0/IRQ1-A/ETEND0-A P10/TxD2/DREQ0/IRQ0-A/EDREQ0-A PI7/D15 PI6/D14 PI5/D13 PI4/D12 Vss PI3/D11 PI2/D10 PI1/D9 PI0/D8 Vcc PH7/D7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
P62/TMO2/SCK4/DACK2/IRQ10-B/TRST/EDACK0-B PLLVcc P63/TMRI3/DREQ3/IRQ11-B/TMS/EDREQ1-B PLLVss P64/TMCI3/TEND3/TDI/ETEND1-B P65/TMO3/DACK3/TCK/EDACK1-B MD0 P50/AN0/IRQ0-B P51/AN1/IRQ1-B P52/AN2/IRQ2-B AVcc P53/AN3/IRQ3-B AVss P54/AN4/IRQ4-B Vref P55/AN5/IRQ5-B P56/AN6/DA0/IRQ6-B P57/AN7/DA1/IRQ7-B MD1 PA0/BREQO/BS-A PA1/BACK/RD/WR PA2/BREQ/WAIT PA3/LLWR/LLB PA4/LHWR/LUB PA5/RD PA6/AS/AH/BS-B Vss PA7/B Vcc PB0/CS0/CS4/CS5-B
91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
LQFP-120 (Top View)
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
PH6/D6 PH5/D5 PH4/D4 Vss PH3/D3 PH2/D2 PH1/D1 PH0/D0 NMI P27/PO7/TIOCA5/TIOCB5 P26/PO6/TIOCA5/TMO1/TxD1 P25/PO5/TIOCA4/TMCI1/RxD1 P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1 P23/PO3/TIOCC3/TIOCD3/IRQ11-A P22/PO2/TIOCC3/TMO0/TxD0/IRQ10-A P21/PO1/TIOCA3/TMCI0/RxD0/IRQ9-A Vcc P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/IRQ8-A Vss MD_CLK VBUS DrVss USDUSD+ DrVcc PM4 PM3 EMLE*2 PJ0/PO16/TIOCA6 PD0/A0 PD1/A1 PJ1/PO17/TIOCA6/TIOCB6
*1
Note: 1. In single-chip mode prots D and E can be used (initial state). Pin functions are selectable by setting the PCJKE bit in PFCRD.
Pin functions are selectable by setting the PCJKE bit in PFCRD. Ports D and E are enabled when PCJKE = 0 (initial value) and ports J and K are enabled when PCJKE = 1. In external extended mode, only ports D and E can be used. 2. This pin is an on-chip emulator enable pin. Drive this pin low for the connection in normal operating mode. The on-chip emulator function is enabled by driving this pin high. When the on-chip emulator is in use, the P62, P63, P64, P65, and WDTOVF pins are dedicated pins for the on-chip emulator. For details on a connection example with the E10A, see E10A Emulator User's Manual.
Rev. 2.00 Sep. 25, 2008 Page 12 of 1340 REJ09B0413-0200
PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B PB2/CS2-A/CS6-A PB3/CS3/CS7-A MD2 PM0/TxD6 PM1/RxD6 PM2 PF4/A20 PF3/A19 Vss PF2/A18 PF1/A17 PF0/A16 PK7/PO31/TIOCA11/TIOCB11 PE7/A15 PK6/PO30/TIOCA11 PE6/A14 PK5/PO29/TIOCA10/TIOCB10 PE5/A13 Vss PK4/PO28/TIOCA10 PE4/A12 Vcc PK3/PO27/TIOCC9/TIOCD9 PE3/A11 PK2/PO26/TIOCC9 PE2/A10 PK1/PO25/TIOCA9/TIOCB9 PE1/A9 PK0/PO24/TIOCA9 PE0/A8 PJ7/PO23/TIOCA8/TIOCB8/TCLKH PD7/A7 PJ6/PO22/TIOCA8 PD6/A6 Vss PD5/A5 PJ5/PO21/TIOCA7/TIOCB7/TCLKG PD4/A4 PJ4/PO20/TIOCA7 PD3/A3 PJ3/PO19/TIOCC6/TIOCD6/TCLKF PD2/A2 PJ2/PO18/TIOCC6/TCLKE
*1
Figure 1.3 Pin Assignments
Section 1 Overview
1.4.2 Table 1.3
Correspondence between Pin Configuration and Operating Modes Pin Configuration in Each Operating Mode (H8SX/1658R Group and H8SX/1658M Group)
Pin Name
Pin No. Modes 1, 2, and 6 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PB1/CS1/CS2-B/ CS5-A/CS6-B/CS7-B PB2/CS2-A/CS6-A PB3/CS3/CS7-A MD2 PM0/TxD6 PM1/RxD6 PM2 PF4/A20 PF3/A19 Vss PF2/A18 PF1/A17 PF0/A16 PE7/A15
Modes 3 and 7 PB1/CS1/CS2-B/ CS5-A/CS6-B/CS7-B PB2/CS2-A/CS6-A PB3/CS3/CS7-A MD2 PM0/TxD6 PM1/RxD6 PM2 PF4/A20 PF3/A19 Vss PF2/A18 PF1/A17 PF0/A16 * PE7/A15 PK7/PO31/TIOCA11/TIOCB11* PE6/A14 PK6/PO30/TIOCA11* PE5/A13 PK5/PO29/TIOCA10/TIOCB10*
1 1 1
Modes 4 and 5 PB1/CS1/CS2-B/ CS5-A/CS6-B/CS7-B PB2/CS2-A/CS6-A PB3/CS3/CS7-A MD2 PM0/TxD6 PM1/RxD6 PM2 PF4/A20 PF3/A19 Vss PF2/A18 PF1/A17 PF0/A16 A15
*
15 PE6/A14 *
A14
*
16 PE5/A13 *
A13
*
17 18 Vss PE4/A12 Vss *
Vss PE4/A12 PK4/PO28/TIOCA10*
1
A12
*
19 20 Vcc PE3/A11 Vcc *
Vcc PE3/A11 PK3/PO27/TIOCC9/TIOCD9* PE2/A10 PK2/PO26/TIOCC9*
1 1
A11
*
21 PE2/A10 *
A10
*
Rev. 2.00 Sep. 25, 2008 Page 13 of 1340 REJ09B0413-0200
Section 1 Overview
Pin Name Pin No. Modes 1, 2, and 6 22 PE1/A9 Modes 3 and 7 * PE1/A9 PK1/PO25/TIOCA9/TIOCB9* PE0/A8 PK0/PO24/TIOCA9* PD7/A7 PJ7/PO23/TIOCA8/TIOCB8/ TCLKH* 25 PD6/A6 * PD6/A6 PJ6/PO22/TIOCA8*
1 1 1 1
Modes 4 and 5 A9
*
23 PE0/A8 *
A8
*
24 PD7/A7 *
A7
*
A6
*
26 27 Vss PD5/A5 Vss *
Vss PD5/A5 PJ5/PO21/TIOCA7/TIOCB7/ TCLKG*
1
A5
*
28 PD4/A4 *
PD4/A4 PJ4/PO20/TIOCA7* PD3/A3 PJ3/PO19/TIOCC6/TIOCD6/ TCLKF*
1 1
A4
*
29 PD3/A3 *
A3
*
30 PD2/A2 *
PD2/A2 PJ2/PO18/TIOCC6/TCLKE* PD1/A1 PJ1/PO17/TIOCA6/TIOCB6* PD0/A0 PJ0/PO16/TIOCA6*
1 1 1
A2
*
31 PD1/A1 *
A1
*
32 PD0/A0 *
A0
*
33 34 35 36 37 38 39 40 EMLE PM3 PM4 DrVcc USD+ USD- DrVss VBUS
EMLE PM3 PM4 DrVcc USD+ USD- DrVss VBUS
EMLE PM3 PM4 DrVcc USD+ USD- DrVss VBUS
Rev. 2.00 Sep. 25, 2008 Page 14 of 1340 REJ09B0413-0200
Section 1 Overview
Pin Name Pin No. Modes 1, 2, and 6 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 MD_CLK Vss Modes 3 and 7 MD_CLK Vss Modes 4 and 5 MD_CLK Vss P20/PO0/TIOCA3/TIOCB3/ TMRI0/SCK0/IRQ8-A Vcc P21/PO1/TIOCA3/TMCI0/ RxD0/IRQ9-A P22/PO2/TIOCC3/TMO0/TxD0/ IRQ10-A P23/PO3/TIOCC3/TIOCD3/ IRQ11-A P24/PO4/TIOCA4/TIOCB4/ TMRI1/SCK1 P25/PO5/TIOCA4/TMCI1/ RxD1 P26/PO6/TIOCA5/TMO1/ TxD1 P27/PO7/TIOCA5/ TIOCB5 NMI D0 D1 D2 D3 Vss D4 D5 D6 D7 Vcc PI0/D8 PI1/D9 PI2/D10 PI3/D11
P20/PO0/TIOCA3/TIOCB3/ P20/PO0/TIOCA3/TIOCB3/ TMRI0/SCK0/IRQ8-A TMRI0/SCK0/IRQ8-A Vcc Vcc
P21/PO1/TIOCA3/TMCI0/R P21/PO1/TIOCA3/TMCI0/RxD0/ xD0/IRQ9-A IRQ9-A P22/PO2/TIOCC3/TMO0/ TxD0/IRQ10-A P22/PO2/TIOCC3/TMO0/TxD0/ IRQ10-A
P23/PO3/TIOCC3/TIOCD3/I P23/PO3/TIOCC3/TIOCD3/ RQ11-A IRQ11-A P24/PO4/TIOCA4/TIOCB4/ P24/PO4/TIOCA4/TIOCB4/ TMRI1/SCK1 TMRI1/SCK1 P25/PO5/TIOCA4/TMCI1/R P25/PO5/TIOCA4/TMCI1/ xD1 RxD1 P26/PO6/TIOCA5/TMO1/Tx P26/PO6/TIOCA5/TMO1/ D1 TxD1 P27/PO7/TIOCA5/ TIOCB5 P27/PO7/TIOCA5/ TIOCB5 NMI PH0/D0 PH1/D1 PH2/D2 PH3/D3 Vss PH4/D4 PH5/D5 PH6/D6 PH7/D7 Vcc PI0/D8 PI1/D9 PI2/D10 PI3/D11 NMI PH0/D0 PH1/D1 PH2/D2 PH3/D3 Vss PH4/D4 PH5/D5 PH6/D6 PH7/D7 Vcc PI0/D8 PI1/D9 PI2/D10 PI3/D11
Rev. 2.00 Sep. 25, 2008 Page 15 of 1340 REJ09B0413-0200
Section 1 Overview
Pin Name Pin No. Modes 1, 2, and 6 67 68 69 70 71 72 73 74 75 76 77 78 79 Vss PI4/D12 PI5/D13 PI6/D14 PI7/D15 P10/TxD2/DREQ0/IRQ0A/EDREQ0-A P11/RxD2/TEND0/IRQ1A/ETEND0-A P12/SCK2/DACK0/IRQ2A/EDACK0-A P13/ADTRG0/IRQ3A/EDRAK0 Vss RES VCL Modes 3 and 7 Vss PI4/D12 PI5/D13 PI6/D14 PI7/D15 P10/TxD2/DREQ0/IRQ0-A/ EDREQ0-A P11/RxD2/TEND0/IRQ1-A/ ETEND0-A P12/SCK2/DACK0/IRQ2-A/ EDACK0-A P13/ADTRG0/IRQ3-A/EDRAK0 Vss RES VCL Modes 4 and 5 Vss PI4/D12 PI5/D13 PI6/D14 PI7/D15 P10/TxD2/DREQ0/IRQ0-A/ EDREQ0-A P11/RxD2/TEND0/IRQ1-A/ ETEND0-A P12/SCK2/DACK0/IRQ2-A/ EDACK0-A P13/ADTRG0/IRQ3A/EDRAK0 Vss RES VCL P14/TCLKA-B/TxD5/IrTXD/ SDA1/DREQ1/IRQ4-A/ EDREQ1-A P15/TCLKB-B/RxD5/IrRXD/ SCL1/TEND1/IRQ5-A/ ETEND1-A WDTOVF Vss XTAL EXTAL Vcc P16/TCLKC-B/SDA0/ DACK1/IRQ6-A/EDACK1-A P17/TCLKD-B/SCL0/ ADTRG1/IRQ7-A/EDRAK1 STBY P60/TMRI2/TxD4/DREQ2/ IRQ8-B/EDREQ0-B
P14/TCLKA-B/TxD5/IrTXD/ P14/TCLKA-B/TxD5/IrTXD/ SDA1/DREQ1/IRQ4-A/ SDA1/DREQ1/IRQ4-A/ EDREQ1-A EDREQ1-A P15/TCLKB-B/RxD5/IrRXD/ P15/TCLKB-B/RxD5/IrRXD/ SCL1/TEND1/IRQ5-A/ SCL1/TEND1/IRQ5-A/ ETEND1-A ETEND1-A WDTOVF Vss XTAL EXTAL Vcc WDTOVF/TDO* Vss XTAL EXTAL Vcc
2
80
81 82 83 84 85 86 87 88 89
P16/TCLKC-B/SDA0/ P16/TCLKC-B/SDA0/ DACK1/IRQ6-A/EDACK1-A DACK1/IRQ6-A/EDACK1-A P17/TCLKD-B/SCL0/ ADTRG1/IRQ7-A/EDRAK1 STBY P60/TMRI2/TxD4/DREQ2/ IRQ8-B/EDREQ0-B P17/TCLKD-B/SCL0/ ADTRG1/IRQ7-A/EDRAK1 STBY P60/TMRI2/TxD4/DREQ2/ IRQ8-B/EDREQ0-B
Rev. 2.00 Sep. 25, 2008 Page 16 of 1340 REJ09B0413-0200
Section 1 Overview
Pin Name Pin No. Modes 1, 2, and 6 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 Modes 3 and 7 Modes 4 and 5 P61/TMCI2/RxD4/ TEND2/IRQ9-B/ETEND0-B P62/TMO2/SCK4/DACK2/ IRQ10-B/EDACK0-B PLLVcc P63/TMRI3/DREQ3/IRQ11-B/ EDREQ1-B PLLVss
2
P61/TMCI2/RxD4/ P61/TMCI2/RxD4/ TEND2/IRQ9-B/ETEND0-B TEND2/IRQ9-B/ETEND0-B P62/TMO2/SCK4/DACK2/ IRQ10-B/EDACK0-B PLLVcc P63/TMRI3/DREQ3/ IRQ11-B/EDREQ1-B PLLVss P64/TMCI3/TEND3/ ETEND1-B P65/TMO3/DACK3/ EDACK1-B MD0 P50/AN0/IRQ0-B P51/AN1/IRQ1-B P52/AN2/IRQ2-B Avcc P53/AN3/IRQ3-B Avss P54/AN4/IRQ4-B Vref P55/AN5/IRQ5-B P56/AN6/DA0/IRQ6-B P57/AN7/DA1/IRQ7-B MD1 PA0/BREQO/BS-A PA1/BACK/(RD/WR) PA2/BREQ/WAIT PA3/LLWR/LLB PA4/LHWR/LUB PA5/RD PA6/AS/AH/BS-B P62/TMO2/SCK4/DACK2/ 2 IRQ10-B/TRST /EDACK0-B PLLVcc P63/TMRI3/DREQ3/IRQ11-B/ 2 TMS* /EDREQ1-B PLLVss P64/TMCI3/TEND3/TDI* / ETEND1-B P65/TMO3/DACK3/TCK* / EDACK1-B MD0 P50/AN0/IRQ0-B P51/AN1/IRQ1-B P52/AN2/IRQ2-B Avcc P53/AN3/IRQ3-B Avss P54/AN4/IRQ4-B Vref P55/AN5/IRQ5-B P56/AN6/DA0/IRQ6-B P57/AN7/DA1/IRQ7-B MD1 PA0/BREQO/BS-A PA1/BACK/(RD/WR) PA2/BREQ/WAIT PA3/LLWR/LLB PA4/LHWR/LUB PA5/RD PA6/AS/AH/BS-B
2
P64/TMCI3/TEND3/ETEND1-B P65/TMO3/DACK3/EDACK1-B MD0 P50/AN0/IRQ0-B P51/AN1/IRQ1-B P52/AN2/IRQ2-B Avcc P53/AN3/IRQ3-B Avss P54/AN4/IRQ4-B Vref P55/AN5/IRQ5-B P56/AN6/DA0/IRQ6-B P57/AN7/DA1/IRQ7-B MD1 PA0/BREQO/BS-A PA1/BACK/(RD/WR) PA2/BREQ/WAIT LLWR/LLB PA4/LHWR/LUB RD PA6/AS/AH/BS-B
Rev. 2.00 Sep. 25, 2008 Page 17 of 1340 REJ09B0413-0200
Section 1 Overview
Pin Name Pin No. Modes 1, 2, and 6 117 118 119 120 Vss PA7/B Vcc PB0/CS0/CS4-A/CS5-B Modes 3 and 7 Vss PA7/B Vcc PB0/CS0/CS4-A/CS5-B Modes 4 and 5 Vss PA7/B Vcc PB0/CS0/CS4-A/CS5-B
Notes: 1. These pins can be used when the PCJKE bit in PFCRD is set to 1 in single-chip mode. 2. Pins TDO, TRST, TMS, TDI, and TCK are enabled in mode 3.
Rev. 2.00 Sep. 25, 2008 Page 18 of 1340 REJ09B0413-0200
Section 1 Overview
1.4.3 Table 1.4
Pin Functions Pin Functions
Pin Name VCC VCL VSS PLLVCC PLLVSS DrVCC DrVSS I/O Input Input Input Input Input Input Input Input Input Output Description Power supply pins. Connect them to the system power supply. Connect this pin to VSS via a 0.1-F capacitor (The capacitor should be placed close to the pin). Ground pins. Connect them to the system power supply (0 V). Power supply pin for the PLL circuit. Connect it to the system power supply. Ground pin for the PLL circuit. Power supply pin for the transceiver with on-chip USB. Connect it to the system power supply. Ground pin for the transceiver with on-chip USB. Pins for a crystal resonator. An external clock signal can be input through the EXTAL pin. For an example of this connection, see section 26, Clock Pulse Generator. Outputs the system clock for external devices. Pins for setting the operating mode. The signal levels on these pins must not be changed during operation. Pins for switching the multiplication ratio of the clock pulse generator. The signal levels on these pins must not be changed during operation. Reset signal input pin. This LSI enters the reset state when this signal goes low. This LSI enters hardware standby mode when this signal goes low. Input pin for the on-chip emulator enable signal. If the on-chip emulator is used, the signal level should be fixed high. If the on-chip emulator is not used, the signal level should be fixed low. On-chip emulator pins or boundary scan pins. When the EMLE pin is driven high, these pins are dedicated for the on-chip emulator. When the EMLE pin is driven low and to mode 3, these pins are dedicated for the boundary scan.
Classification Power supply
Clock
XTAL EXTAL B
Operating mode MD2 to MD0 Input control MD_CLK Input
System control
RES STBY EMLE
Input Input Input
On-chip emulator
TRST TMS TDI TCK TDO
Input Input Input Input Output Output
Address bus
A20 to A0
Output pins for the address bits.
Rev. 2.00 Sep. 25, 2008 Page 19 of 1340 REJ09B0413-0200
Section 1 Overview
Classification Data bus
Pin Name D15 to D0
I/O Input/ output Input Output
Description Input and output for the bidirectional data bus. These pins also output addresses when accessing an address-data multiplexed I/O interface space. External bus-master modules assert this signal to request the bus. Internal bus-master modules assert this signal to request access to the external space via the bus in the external bus released state. Bus acknowledge signal, which indicates that the bus has been released. Indicates the start of a bus cycle. Strobe signal which indicates that the output address on the address bus is valid in access to the basic bus interface or byte control SRAM interface space. This signal is used to hold the address when accessing the address-data multiplexed I/O interface space. Strobe signal which indicates that reading from the basic bus interface space is in progress. Indicates the direction (input or output) of the data bus. Strobe signal which indicates that the higher-order byte (D15 to D8) is valid in access to the basic bus interface space. Strobe signal which indicates that the lower-order byte (D7 to D0) is valid in access to the basic bus interface space. Strobe signal which indicates that the higher-order byte (D15 to D8) is valid in access to the byte control SRAM interface space. Strobe signal which indicates that the lower-order byte (D7 to D0) is valid in access to the byte control SRAM interface space. Select signals for areas 0 to 7.
Bus control
BREQ BREQO
BACK BS-A/BS-B AS
Output Output Output
AH RD RD/WR LHWR
Output Output Output Output
LLWR LUB
Output Output
LLB
Output
CS0 CS1 CS2-A/CS2-B CS3 CS4 CS5-A/CS5-B CS6-A/CS6-B CS7-A/CS7-B WAIT
Output
Input
Requests wait cycles in access to the external space.
Rev. 2.00 Sep. 25, 2008 Page 20 of 1340 REJ09B0413-0200
Section 1 Overview
Classification Interrupt
Pin Name NMI IRQ11-A/IRQ11-B IRQ10-A/IRQ10-B IRQ9-A/IRQ9-B IRQ8-A/IRQ8-B IRQ7-A/IRQ7-B IRQ6-A/IRQ6-B IRQ5-A/IRQ5-B IRQ4-A/IRQ4-B IRQ3-A/IRQ3-B IRQ2-A/IRQ2-B IRQ1-A/IRQ1-B IRQ0-A/IRQ0-B
I/O Input Input
Description Non-maskable interrupt request signal. When this pin is not in use, this signal must be fixed high. Maskable interrupt request signal.
DMA controller (DMAC)
DREQ0-A/DREQ0-B Input DREQ1-A/DREQ1-B DREQ2 DREQ3 DACK0-A/DACK0-B Output DACK1-A/DACK1-B DACK2 DACK3 TEND0-A/TEND0-B Output TEND1-A/TEND1-B TEND2 TEND3
Requests DMAC activation.
DMAC single address-transfer acknowledge signal.
Indicates end of data transfer by the DMAC.
EXDMA controller (EXDMAC)
EDREQ0A/EDREQ0-B EDREQ1A/EDREQ1-B EDACK0A/EDACK0-B EDACK1A/EDACK1-B ETEND0A/ETEND0-B ETEND1A/ETEND1-B EDRAK0 EDRAK1
Input
Requests EXDMAC activation.
Output
EXDMAC single address-transfer acknowledge signal.
Output
Indicates end of data transfer by the EXDMAC.
Output
Notification to external device of EXDMAC request acceptance and start of execution
Rev. 2.00 Sep. 25, 2008 Page 21 of 1340 REJ09B0413-0200
Section 1 Overview
Classification
Pin Name
I/O
Description Input pins for the external clock signals.
TCLKA-A/TCLKA-B Input 16-bit timer pulse unit (TPU) TCLKB-A/TCLKB-B TCLKC-A/TCLKC-B TCLKD-A/TCLKD-B TIOCA3 TIOCB3 TIOCC3 TIOCD3 16-bit timer TIOCA4 pulse unit (TPU) TIOCB4 TIOCA5 TIOCB5 TCLKE TCLKF TCLKG TCLKH TIOCA6 TIOCB6 TIOCC6 TIOCD6 TIOCA7 TIOCB7 TIOCA8 TIOCB8 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TIOCA10 TIOCB10 TIOCA11 TIOCB11 Programmable pulse generator (PPG) PO31 to PO16, PO7 to PO0 Input/ output
Signals for TGRA_3 to TGRD_3. These pins are used as input capture inputs, output compare outputs, or PWM outputs. Signals for TGRA_4 and TGRB_4. These pins are used as input capture inputs, output compare outputs, or PWM outputs. Signals for TGRA_5 and TGRB_5. These pins are used as input capture inputs, output compare outputs, or PWM outputs. Input pins for external clock signals.
Input/ output Input/ output Input
Input/ output
Signals for TGRA_6 to TGRD_6. These pins are used as input capture inputs, output compare outputs, or PWM outputs. Signals for TGRA_7 and TGRB_7. These pins are used as input capture inputs, output compare outputs, or PWM outputs. Signals for TGRA_8 and TGRB_8. These pins are used as input capture inputs, output compare outputs, or PWM outputs. Signals for TGRA_9 to TGRD_9. These pins are used as input capture inputs, output compare outputs, or PWM outputs. Signals for TGRA_10 and TGRB_10. These pins are used as input capture inputs, output compare outputs, or PWM outputs. Signals for TGRA_11 and TGRB_11. These pins are used as input capture inputs, output compare outputs, or PWM outputs. Output pins for the pulse signals.
Input/ output Input/ output Input/ output
Input/ output Input/ output Output
Rev. 2.00 Sep. 25, 2008 Page 22 of 1340 REJ09B0413-0200
Section 1 Overview
Classification 8-bit timer (TMR)
Pin Name TMO0 to TMO7 TMCI0 to TMCI3 TMRI0 to TMRI3
I/O Output Input Input Output Output
Description Output pins for the compare match signals. Input pins for the external clock signals that drive for the counters. Input pins for the counter-reset signals. Output pin for the counter-overflow signal in watchdog-timer mode. Output pins for data transmission.
Watchdog timer WDTOVF (WDT) Serial TxD0 communications TxD1 interface (SCI) TxD2 TxD4 TxD5 TxD6 RxD0 RxD1 RxD2 RxD4 RxD5 RxD6 SCK0 SCK1 SCK2 SCK4 SCI with IrDA (SCI)
2
Input
Input pins for data reception.
Input/ output
Input/output pins for clock signals.
IrTxD IrRxD
Output Input Input/ output Input/ output Input/ output Input Input Input Output
Output pin that outputs encoded data for IrDA. Input pin that inputs encoded data for IrDA. Input/output pin for IIC clock. Bus can be directly driven by the NMOS open drain output. Input/output pin for IIC data. Bus can be directly driven by the NMOS open drain output. Input/output pin for USB data.
I C bus interface SCL0, SCL1 2 (IIC2) SDA0, SDA1 Universal serial bus interface (USB) A/D converter USD+ USD- VBUS AN7 to AN0 ADTRG0, ADTRG1 D/A converter DA1, DA0
Input/output pin to connect/disconnect USB cable. Input pins for the analog signals to be processed by the A/D converter. Input pins for the external trigger signal that starts A/D conversion. Output pins for the analog signals from the D/A converter.
Rev. 2.00 Sep. 25, 2008 Page 23 of 1340 REJ09B0413-0200
Section 1 Overview
Classification A/D converter, D/A converter
Pin Name AVCC
I/O Input
Description Analog power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not in use, connect this pin to the system power supply. Ground pin for the A/D and D/A converters. Connect this pin to the system power supply (0 V). Reference power supply pin for the A/D and D/A converters. When the A/D and D/A converters are not in use, connect this pin to the system power supply. 8-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. 6-bit input/output pins. Input-only pin 7-bit input/output pins. 4-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. 5-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins. 5-bit input/output pins. 8-bit input/output pins. 8-bit input/output pins.
AVSS Vref
Input Input
I/O ports
P17 to P10 P27 to P20 P57 to P50 P65 to P60 PA7 PA6 to PA0 PB3 to PB0 PD7 to PD0 PE7 to PE0 PF4 to PF0 PH7 to PH0 PI7 to PI0 PM4 to PM0 PJ7 to PJ0* PK7 to PK0*
Input/ output Input/ output Input Input/ output Input Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output Input/ output
Note:
*
These pins can be used when the PCJKE bit in PFCRD is set to 1 in single-chip mode.
Rev. 2.00 Sep. 25, 2008 Page 24 of 1340 REJ09B0413-0200
Section 2 CPU
Section 2 CPU
The H8SX CPU is a high-speed CPU with an internal 32-bit architecture that is upward compatible with the H8/300, H8/300H, and H8S CPUs. The H8SX CPU has sixteen 16-bit general registers, can handle a 4-Gbyte linear address space, and is ideal for a realtime control system.
2.1
Features
* Upward-compatible with H8/300, H8/300H, and H8S CPUs Can execute object programs of these CPUs * Sixteen 16-bit general registers Also usable as sixteen 8-bit registers or eight 32-bit registers * 87 basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Bit field transfer instructions Powerful bit-manipulation instructions Bit condition branch instructions Multiply-and-accumulate instruction * Eleven addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:2,ERn), @(d:16,ERn), or @(d:32,ERn)] Index register indirect with displacement [@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)] Register indirect with pre-/post-increment or pre-/post-decrement [@+ERn, @-ERn, @ERn+, or @ERn-] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:3, #xx:4, #xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Program-counter relative with index register [@(RnL.B,PC), @(Rn.W,PC), or @(ERn.L,PC)] Memory indirect [@@aa:8] Extended memory indirect [@@vec:7]
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Section 2 CPU
* Two base registers Vector base register Short address base register * 4-Gbyte address space Program: 4 Gbytes Data: 4 Gbytes * High-speed operation All frequently-used instructions executed in one or two states 8/16/32-bit register-register add/subtract: 1 state 8 x 8-bit register-register multiply: 1 state (when the multiplier is available.) 16 / 8-bit register-register divide: 10 states (when the divider is available.) 16 x 16-bit register-register multiply: 1 state (when the multiplier is available.) 32 / 16-bit register-register divide: 18 states (when the divider is available.) 32 x 32-bit register-register multiply: 5 states (when the multiplier is available.) 32 / 32-bit register-register divide: 18 states (when the divider is available.) * Four CPU operating modes Normal mode Middle mode Advanced mode Maximum mode * Power-down modes Transition is made by execution of SLEEP instruction Choice of CPU operating clocks Notes: 1. Advanced mode is only supported as the CPU operating mode of the H8SX/1658R Group and H8SX/1658M Group. Normal, middle, and maximum modes are not supported. 2. The multiplier and divider are supported by the H8SX/1658R Group and H8SX/1658M Group.
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Section 2 CPU
2.2
CPU Operating Modes
The H8SX CPU has four operating modes: normal, middle, advanced and maximum modes. These modes can be selected by the mode pins of this LSI.
Maximum 64 kbytes for program Normal mode and data areas combined Maximum 16-Mbyte program Middle mode CPU operating modes Advanced mode area and 64-kbyte data area, maximum 16 Mbytes for program and data areas combined Maximum 16-Mbyte program area and 4-Gbyte data area, maximum 4 Gbytes for program and data areas combined Maximum mode Maximum 4 Gbytes for program and data areas combined
Figure 2.1 CPU Operating Modes 2.2.1 Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU. * Address Space The maximum address space of 64 kbytes can be accessed. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register it can contain any value, even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/post-decrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.) * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid.
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Section 2 CPU
* Exception Vector Table and Memory Indirect Branch Addresses In normal mode, the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The structure of the exception vector table is shown in figure 2.2.
H'0000 H'0001 H'0002 H'0003
Reset exception vector Reset exception vector Exception vector table
Figure 2.2 Exception Vector Table (Normal Mode) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.3. The PC contents are saved or restored in 16-bit units.
SP
PC (16 bits)
SP
(SP*2 )
EXR*1 Reserved*1, *3 CCR CCR*3 PC (16 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored on return.
Figure 2.3 Stack Structure (Normal Mode)
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Section 2 CPU
2.2.2
Middle Mode
The program area in middle mode is extended to 16 Mbytes as compared with that in normal mode. * Address Space The maximum address space of 16 Mbytes can be accessed as a total of the program and data areas. For individual areas, up to 16 Mbytes of the program area or up to 64 kbytes of the data area can be allocated. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When the extended register En is used as a 16-bit register (in other than the JMP and JSR instructions), it can contain any value even when the corresponding general register Rn is used as an address register. (If the general register Rn is referenced in the register indirect addressing mode with pre-/post-increment or pre-/postdecrement and a carry or borrow occurs, however, the value in the corresponding extended register En will be affected.) * Instruction Set All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid and the upper eight bits are sign-extended. * Exception Vector Table and Memory Indirect Branch Addresses In middle mode, the top area starting at H'000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4. The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In middle mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00. * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units.
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Section 2 CPU
2.2.3
Advanced Mode
The data area is extended to 4 Gbytes as compared with that in middle mode. * Address Space The maximum address space of 4 Gbytes can be linearly accessed. For individual areas, up to 16 Mbytes of the program area and up to 4 Gbytes of the data area can be allocated. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In advanced mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The upper eight bits are ignored and the lower 24 bits are stored. The structure of the exception vector table is shown in figure 2.4.
H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005
H'00000006
Reserved Reset exception vector Reserved
Exception vector table
H'00000007
Figure 2.4 Exception Vector Table (Middle and Advanced Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In advanced mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. The upper eight bits are reserved and assumed to be H'00.
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Section 2 CPU
* Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.5. The PC contents are saved or restored in 24-bit units.
SP
SP
Reserved
PC (24 bits)
(SP *2
)
EXR*1 Reserved*1, *3 CCR PC (24 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored on return.
Figure 2.5 Stack Structure (Middle and Advanced Modes) 2.2.4 Maximum Mode
The program area is extended to 4 Gbytes as compared with that in advanced mode. * Address Space The maximum address space of 4 Gbytes can be linearly accessed. * Extended Registers (En) The extended registers (E0 to E7) can be used as 16-bit registers or as the upper 16-bit segments of 32-bit registers or address registers. * Instruction Set All instructions and addressing modes can be used. * Exception Vector Table and Memory Indirect Branch Addresses In maximum mode, the top area starting at H'00000000 is allocated to the exception vector table. One branch address is stored per 32 bits. The structure of the exception vector table is shown in figure 2.6.
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Section 2 CPU
H'00000000 H'00000001 H'00000002 H'00000003 H'00000004 H'00000005
H'00000006
Reset exception vector
Exception vector table
H'00000007
Figure 2.6 Exception Vector Table (Maximum Modes) The memory indirect (@@aa:8) and extended memory indirect (@@vec:7) addressing modes are used in the JMP and JSR instructions. An 8-bit absolute address included in the instruction code specifies a memory location. Execution branches to the contents of the memory location. In maximum mode, an operand is a 32-bit (longword) operand, providing a 32-bit branch address. * Stack Structure The stack structure of PC at a subroutine branch and that of PC and CCR at an exception handling are shown in figure 2.7. The PC contents are saved or restored in 32-bit units. The EXR contents are saved or restored regardless of whether or not EXR is in use.
SP
SP
PC (32 bits)
EXR CCR PC (32 bits)
(a) Subroutine Branch
(b) Exception Handling
Figure 2.7 Stack Structure (Maximum Mode)
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Section 2 CPU
2.3
Instruction Fetch
The H8SX CPU has two modes for instruction fetch: 16-bit and 32-bit modes. It is recommended that the mode be set according to the bus width of the memory in which a program is stored. The instruction-fetch mode setting does not affect operation other than instruction fetch such as data accesses. Whether an instruction is fetched in 16- or 32-bit mode is selected by the FETCHMD bit in SYSCR. For details, see section 3.2.2, System Control Register (SYSCR).
2.4
Address Space
Figure 2.8 shows a memory map of the H8SX CPU. The address space differs depending on the CPU operating mode.
Normal mode H'0000 H'000000 H'007FFF Program area Data area (64 kbytes) Middle mode H'00000000 Advanced mode H'00000000 Maximum mode
H'FFFF
Program area (16 Mbytes) Program area (16 Mbytes)
Data area (64 kbytes)
H'FF8000 H'FFFFFF H'00FFFFFF
Program area Data area (4 Gbytes)
Data area (4 Gbytes)
H'FFFFFFFF
H'FFFFFFFF
Figure 2.8 Memory Map
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Section 2 CPU
2.5
Registers
The H8SX CPU has the internal registers shown in figure 2.9. There are two types of registers: general registers and control registers. The control registers are the 32-bit program counter (PC), 8-bit extended control register (EXR), 8-bit condition-code register (CCR), 32-bit vector base register (VBR), 32-bit short address base register (SBR), and 64-bit multiply-accumulate register (MAC).
General Registers and Extended Registers 15
ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP)
07 E0 E1 E2 E3 E4 E5 E6 E7 R0H R1H R2H R3H R4H R5H R6H R7H
07 R0L R1L R2L R3L R4L R5L R6L R7L
0
Control Registers 31
PC
0
76543210
CCR I UI H U N Z V C 76543210
EXR
31
VBR 31 SBR
T -- -- -- -- I2 I1 I0
0 (Reserved)
8 (Reserved) 0
12
63
MAC 31
41
32
MACH
Sign extension
MACL
[Legend] SP: PC: CCR: I: UI: H:
0
Stack pointer Program counter Condition-code register Interrupt mask bit User bit or interrupt mask bit Half-carry flag
U: N: Z: V: C: EXR:
User bit Negative flag Zero flag Overflow flag Carry flag Extended control register
T: I2 to I0: VBR: SBR: MAC:
Trace bit Interrupt mask bits Vector base register Short address base register Multiply-accumulate register
Figure 2.9 CPU Registers
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Section 2 CPU
2.5.1
General Registers
The H8SX CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.10 illustrates the usage of the general registers. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). When the general registers are used as 16-bit registers, the ER registers are divided into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. When the general registers are used as 8-bit registers, the R registers are divided into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. The general registers ER (ER0 to ER7), R (R0 to R7), and RL (R0L to R7L) are also used as index registers. The size in the operand field determines which register is selected. The usage of each register can be selected independently.
* 16-bit registers
* Address registers * 32-bit registers * 32-bit index registers General registers ER (ER0 to ER7)
General registers E (E0 to E7)
* 8-bit registers * 16-bit registers * 16-bit index registers
General registers RH (R0H to R7H)
* 8-bit registers * 8-bit index registers
General registers R (R0 to R7)
General registers RL (R0L to R7L)
Figure 2.10 Usage of General Registers
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Section 2 CPU
General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine branches. Figure 2.11 shows the stack.
Free area
SP (ER7)
Stack area
Figure 2.11 Stack 2.5.2 Program Counter (PC)
PC is a 32-bit counter that indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 16 bits (one word) or a multiple of 16 bits, so the least significant bit is ignored. (When the instruction code is fetched, the least significant bit is regarded as 0.
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2.5.3
Condition-Code Register (CCR)
CCR is an 8-bit register that contains internal CPU status information, including an interrupt mask (I) and user (UI, U) bits and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branch conditions for conditional branch (Bcc) instructions.
Bit 7 Bit Name I Initial Value 1 R/W R/W Description Interrupt Mask Bit Masks interrupts when set to 1. This bit is set to 1 at the start of an exception handling. 6 UI Undefined R/W User Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 5 H Undefined R/W Half-Carry Flag When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. 4 U Undefined R/W User Bit Can be written to and read from by software using the LDC, STC, ANDC, ORC, and XORC instructions. 3 N Undefined R/W Negative Flag Stores the value of the most significant bit (regarded as sign bit) of data.
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Bit 2
Bit Name Z
Initial Value
R/W
Description Zero Flag Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data.
Undefined R/W
1
V
Undefined R/W
Overflow Flag Set to 1 when an arithmetic overflow occurs, and cleared to 0 otherwise.
0
C
Undefined R/W
Carry Flag Set to 1 when a carry occurs, and cleared to 0 otherwise. A carry has the following types: * * * Carry from the result of addition Borrow from the result of subtraction Carry from the result of shift or rotation
The carry flag is also used as a bit accumulator by bit manipulation instructions.
2.5.4
Extended Control Register (EXR)
EXR is an 8-bit register that contains the trace bit (T) and three interrupt mask bits (I2 to I0). Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. For details, see section 6, Exception Handling.
Bit 7 Bit Name T Initial Value 0 R/W R/W Description Trace Bit When this bit is set to 1, a trace exception is generated each time an instruction is executed. When this bit is cleared to 0, instructions are executed in sequence. 6 to 3 2 1 0 -- I2 I1 I0 All 1 1 1 1 R/W R/W R/W R/W Reserved These bits are always read as 1. Interrupt Mask Bits These bits designate the interrupt mask level (0 to 7).
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Section 2 CPU
2.5.5
Vector Base Register (VBR)
VBR is a 32-bit register in which the upper 20 bits are valid. The lower 12 bits of this register are read as 0s. This register is a base address of the vector area for exception handlings other than a reset and a CPU address error (extended memory indirect is also out of the target). The initial value is H'00000000. The VBR contents are changed with the LDC and STC instructions. 2.5.6 Short Address Base Register (SBR)
SBR is a 32-bit register in which the upper 24 bits are valid. The lower eight bits are read as 0s. In 8-bit absolute address addressing mode (@aa:8), this register is used as the upper address. The initial value is H'FFFFFF00. The SBR contents are changed with the LDC and STC instructions. 2.5.7 Multiply-Accumulate Register (MAC)
MAC is a 64-bit register that stores the results of multiply-and-accumulate operations. It consists of two 32-bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are sign extended. The MAC contents are changed with the MAC, CLRMAC, LDMAC, and STMAC instructions. 2.5.8 Initial Values of CPU Registers
Reset exception handling loads the start address from the vector table into the PC, clears the T bit in EXR to 0, and sets the I bits in CCR and EXR to 1. The general registers, MAC, and the other bits in CCR are not initialized. In particular, the initial value of the stack pointer (ER7) is undefined. The SP should therefore be initialized using an MOV.L instruction executed immediately after a reset.
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Section 2 CPU
2.6
Data Formats
The H8SX CPU can process 1-bit, 4-bit BCD, 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.6.1 General Register Data Formats
Figure 2.12 shows the data formats in general registers.
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Section 2 CPU
1-bit data
RnH
7 0 76543210
Don't care
7 0 76543210
1-bit data
RnL
Don't care
7 43 Upper 0 Lower
4-bit BCD data
RnH
Don't care
7 43 Upper Lower 0
4-bit BCD data
RnL
7
Don't care
0
Byte data
RnH
Don't care
MSB
Byte data RnL
15
LSB
7 Don't care 0
MSB Word data Rn
MSB
LSB
0
LSB
Word data 15
MSB
En
0 LSB
Longword data 31
MSB
ERn
16 15 En
Rn
0 LSB
[Legend] ERn: General register ER En: General register E Rn: General register R RnH: General register RH
RnL: General register RL MSB: Most significant bit LSB: Least significant bit
Figure 2.12 General Register Data Formats
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Section 2 CPU
2.6.2
Memory Data Formats
Figure 2.13 shows the data formats in memory. The H8SX CPU can access word data and longword data which are stored at any addresses in memory. When word data begins at an odd address or longword data begins at an address other than a multiple of 4, a bus cycle is divided into two or more accesses. For example, when longword data begins at an odd address, the bus cycle is divided into byte, word, and byte accesses. In this case, these accesses are assumed to be individual bus cycles. However, instructions to be fetched, word and longword data to be accessed during execution of the stack manipulation, branch table manipulation, block transfer instructions, and MAC instruction should be located to even addresses. When SP (ER7) is used as an address register to access the stack, the operand size should be word size or longword size.
Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format
Byte data
Address L MSB
LSB
Word data
Address 2M MSB Address 2M + 1 LSB
Longword data
Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB
Figure 2.13 Memory Data Formats
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Section 2 CPU
2.7
Instruction Set
The H8SX CPU has 87 types of instructions. The instructions are classified by function as shown in table 2.1. The arithmetic operation, logic operation, shift, and bit manipulation instructions are called operation instruction in this manual. Table 2.1
Function Data transfer
Instruction Classification
Instructions MOV MOVFPE, MOVTPE POP, PUSH* LDM, STM MOVA
1
Size B/W/L B W/L L B/W* B B/W/L B B/W/L B L B/W W/L L W/L B
2
Types 6
Block transfer
EEPMOV MOVMD MOVSD
3
Arithmetic operations
ADD, ADDX, SUB, SUBX, CMP, NEG, INC, DEC DAA, DAS ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS MULU, DIVU, MULS, DIVS MULU/U*6, MULS/U*6 EXTU, EXTS TAS MAC*
6 6 6
27
-- -- -- B/W/L 4 8 20
6
LDMAC* , STMAC* CLRMAC* Logic operations Shift Bit manipulation
AND, OR, XOR, NOT
SHLL, SHLR, SHAL, SHAR, ROTL, ROTR, ROTXL, ROTXR B/W/L BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST BSET/EQ, BSET/NE, BCLR/EQ, BCLR/NE, BSTZ, BISTZ BFLD, BFST B B B
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Section 2 CPU
Function Branch
Instructions BRA/BS, BRA/BC, BSR/BS, BSR/BC Bcc* , JMP, BSR, JSR, RTS RTS/L BRA/S
4
Size B* -- L*5 -- -- L*
5 3
Types 9
System control
TRAPA, RTE, SLEEP, NOP RTE/L LDC, STC, ANDC, ORC, XORC
10
B/W/L Total 87
[Legend] B: Byte size W: Word size L: Longword size Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Size of data to be added with a displacement 3. Size of data to specify a branch condition 4. Bcc is the generic designation of a conditional branch instruction. 5. Size of general register to be restored 6. Only when the multiplier is available.
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Section 2 CPU
2.7.1
Instructions and Addressing Modes
Table 2.2 indicates the combinations of instructions and addressing modes that the H8SX CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes (1)
Addressing Mode @(d, RnL.B/ Rn.W/ @ERn @(d,ERn) ERn.L) SD SD SD @ERn/ @ERn/ @ERn/ @ERn SD S/D S/D* S/D* S/D* S S S S
2 2 1
Classification Data transfer
Instruction MOV MOVFPE, MOVTPE POP, PUSH LDM, STM MOVA*
4
Size B/W/L B B W/L L B/W B B/W/L B B B B B W/L
#xx S
Rn SD S/D S/D S/D S/D S
@aa:16/ @aa:8 @aa:32 -- SD
S SD* SD* SD*
3 3 3
Block transfer
EEPMOV MOVMD MOVSD ADD, CMP
Arithmetic operations
S
D S D
D D S SD SD D D S SD SD SD
D D S SD SD D D S SD SD
D D S SD SD D D S SD SD
D D S SD SD D D S SD SD
D D S
D D S SD SD
S S
SD S D
SUB
B B B B W/L
D D S
D D S SD SD
S S S S
SD SD
ADDX, SUBX B/W/L B/W/L B/W/L INC, DEC DAA, DAS B/W/L B ADDS, SUBS L
SD* D D D
5
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Section 2 CPU
Addressing Mode @(d, RnL.B/ Rn.W/ @ERn @(d,ERn) ERn.L) @ERn/ @ERn/ @ERn/ @ERn
Classification Arithmetic operations
Instruction MULXU, DIVXU MULU, DIVU MULXS, DIVXS MULS, DIVS NEG EXTU, EXTS TAS MAC*
12 12
Size B/W W/L B/W W/L B W/L W/L B -- -- -- -- B B W/L
#xx S:4 S:4 S:4 S:4
Rn SD SD SD SD D D D
@aa:16/ @aa:8 @aa:32 --
D D D D
D D D
D D D
D D D
D
D D D
CLRMAC* LDMAC* STMAC* Logic operations
12 12
O S D S D S SD D D D
6 7
AND, OR, XOR B
D S SD SD D D D D D D
D S SD SD D D D D D D
D S SD SD D D D D D D
D S SD SD D D D D D D
D S
D S SD SD
NOT Shift SHLL, SHLR
B W/L B W/L* B/W/L*
D D
D D D D
D D D D
SHAL, SHAR ROTL, ROTR ROTXL, ROTXR Bit manipulation BSET, BCLR, BNOT, BTST, BSET/cc, BCLR/cc
B W/L
D
D D
B
D
D
D
D
BAND, BIAND, B BOR, BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST, BSTZ, BISTZ
D
D
D
D
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Section 2 CPU
Addressing Mode @(d, RnL.B/ Rn.W/ @ERn @(d,ERn) ERn.L) S D S S
9
Classification Instruction Bit manipulation Branch System control BFLD BFST BRA/BS, BRA/BC* BSR/BS, BSR/BC* LDC (CCR, EXR) LDC (VBR, SBR) STC (CCR, EXR) STC (VBR, SBR) ANDC, ORC, XORC SLEEP NOP
8 8
Size B B B B B/W* L B/W* L B -- --
9
#xx
Rn D S
@ERn/ @ERn/ @ERn/ @ERn
@aa:16/ @aa:8 @aa:32 -- S D S S S D S S S
S
S S D D
S
S
S*
10
D
D
D*
11
D
S O O
[Legend] d: d:16 or d:32 S: Can be specified as a source operand. D: Can be specified as a destination operand. SD: Can be specified as either a source or destination operand or both. S/D: Can be specified as either a source or destination operand. S:4: 4-bit immediate data can be specified as a source operand. Notes: 1. Only @aa:16 is available. 2. @ERn+ as a source operand and @-ERn as a destination operand 3. Specified by ER5 as a source address and ER6 as a destination address for data transfer. 4. Size of data to be added with a displacement 5. Only @ERn- is available 6. When the number of bits to be shifted is 1, 2, 4, 8, or 16 7. When the number of bits to be shifted is specified by 5-bit immediate data or a general register 8. Size of data to specify a branch condition 9. Byte when immediate or register direct, otherwise, word 10. Only @ERn+ is available 11. Only @-ERn is available 12. Only when the multiplier is available.
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Section 2 CPU
Table 2.2
Combinations of Instructions and Addressing Modes (2)
Addressing Mode
@(RnL. B/Rn.W/
Classification Branch
ERn.L,
Instruction BRA/BS, BRA/BC BSR/BS, BSR/BC Bcc BRA BRA/S JMP BSR JSR
Size
@ERn
@(d,PC) PC)
@ @aa:24 aa:32
@@vec: @@ aa:8 7
--
-- -- -- -- -- -- -- --
O O
O O O O O* O O O O O O O O O O O O O
RTS, RTS/L -- System control TRAPA
--
RTE, RTE/L --
[Legend] d: d:8 or d:16 Note: * Only @(d:8, PC) is available.
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Section 2 CPU
2.7.2
Table of Instructions Classified by Function
Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in these tables is defined in table 2.3. Table 2.3 Operation Notation
Description General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register Vector base register Short address base register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move Logical not (logical complement) 8-, 16-, 24-, or 32-bit length
Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR VBR SBR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 Note: *
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Section 2 CPU
Table 2.4
Instruction MOV MOVFPE MOVTPE POP PUSH LDM
Data Transfer Instructions
Size B/W/L B B W/L W/L L Function #IMM (EAd), (EAs) (EAd) Transfers data between immediate data, general registers, and memory. (EAs) Rd Rs (EAs) @SP+ Rn Restores the data from the stack to a general register. Rn @-SP Saves general register contents on the stack. @SP+ Rn (register list) Restores the data from the stack to multiple general registers. Two, three, or four general registers which have serial register numbers can be specified.
STM
L
Rn (register list) @-SP Saves the contents of multiple general registers on the stack. Two, three, or four general registers which have serial register numbers can be specified.
MOVA
B/W
EA Rd Zero-extends and shifts the contents of a specified general register or memory data and adds them with a displacement. The result is stored in a general register.
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Section 2 CPU
Table 2.5
Instruction EEPMOV.B EEPMOV.W
Block Transfer Instructions
Size B Function Transfers a data block. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4 or R4L. B Transfers a data block. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4.
MOVMD.B
MOVMD.W
W
Transfers a data block. Transfers word data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of word data to be transferred is specified by R4.
MOVMD.L
L
Transfers a data block. Transfers longword data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of longword data to be transferred is specified by R4.
MOVSD.B
B
Transfers a data block with zero data detection. Transfers byte data which begins at a memory location specified by ER5 to a memory location specified by ER6. The number of byte data to be transferred is specified by R4. When zero data is detected during transfer, the transfer stops and execution branches to a specified address.
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Section 2 CPU
Table 2.6
Instruction ADD SUB
Arithmetic Operation Instructions
Size B/W/L Function (EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs addition or subtraction on data between immediate data, general registers, and memory. Immediate byte data cannot be subtracted from byte data in a general register. (EAd) #IMM C (EAd), (EAd) (EAs) C (EAd) Performs addition or subtraction with carry on data between immediate data, general registers, and memory. The addressing mode which specifies a memory location can be specified as register indirect with post-decrement or register indirect. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a general register. Rd (decimal adjust) Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 2-digit 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits, or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits, or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs unsigned multiplication on data in two general registers (32 bits x 32 bits upper 32 bits). Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits, or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 16 bits x 16 bits 16 bits, or 32 bits x 32 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers (32 bits x 32 bits upper 32 bits). Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder, or 32 bits / 16 bits 16-bit quotient and 16-bit remainder.
ADDX SUBX
B/W/L
INC DEC ADDS SUBS DAA DAS MULXU
B/W/L
L B
B/W
MULU
W/L
MULU/U
L
MULXS
B/W
MULS
W/L
MULS/U
L
DIVXU
B/W
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Section 2 CPU
Instruction DIVU
Size W/L
Function Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 16 bits 16-bit quotient, or 32 bits / 32 bits 32-bit quotient. Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder, or 32 bits / 16 bits 16-bit quotient and 16-bit remainder. Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 16 bits 16-bit quotient, or 32 bits / 32 bits 32-bit quotient. (EAd) - #IMM, (EAd) - (EAs) Compares data between immediate data, general registers, and memory and stores the result in CCR. 0 - (EAd) (EAd) Takes the two's complement (arithmetic complement) of data in a general register or the contents of a memory location. (EAd) (zero extension) (EAd) Performs zero-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be zero-extended. (EAd) (sign extension) (EAd) Performs sign-extension on the lower 8 or 16 bits of data in a general register or memory to word or longword size. The lower 8 bits to word or longword, or the lower 16 bits to longword can be sign-extended. @ERd - 0, 1 ( of @EAd) Tests memory contents, and sets the most significant bit (bit 7) to 1. (EAs) x (EAd) + MAC MAC Performs signed multiplication on memory contents and adds the result to MAC. 0 MAC Clears MAC to zero. Rs MAC Loads data from a general register to MAC. MAC Rd Stores data from MAC to a general register.
DIVXS
B/W
DIVS
W/L
CMP
B/W/L
NEG
B/W/L
EXTU
W/L
EXTS
W/L
TAS MAC
B --
CLRMAC LDMAC STMAC
-- -- --
Note: Only when the multiplier is available.
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Section 2 CPU
Table 2.7
Instruction AND
Logic Operation Instructions
Size B/W/L Function (EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs a logical AND operation on data between immediate data, general registers, and memory.
OR
B/W/L
(EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs a logical OR operation on data between immediate data, general registers, and memory.
XOR
B/W/L
(EAd) #IMM (EAd), (EAd) (EAs) (EAd) Performs a logical exclusive OR operation on data between immediate data, general registers, and memory.
NOT
B/W/L
(EAd) (EAd) Takes the one's complement of the contents of a general register or a memory location.
Table 2.8
Instruction SHLL SHLR
Shift Operation Instructions
Size B/W/L Function (EAd) (shift) (EAd) Performs a logical shift on the contents of a general register or a memory location. The contents of a general register or a memory location can be shifted by 1, 2, 4, 8, or 16 bits. The contents of a general register can be shifted by any bits. In this case, the number of bits is specified by 5-bit immediate data or the lower 5 bits of the contents of a general register.
SHAL SHAR
B/W/L
(EAd) (shift) (EAd) Performs an arithmetic shift on the contents of a general register or a memory location. 1-bit or 2-bit shift is possible.
ROTL ROTR ROTXL ROTXR
B/W/L
(EAd) (rotate) (EAd) Rotates the contents of a general register or a memory location. 1-bit or 2-bit rotation is possible.
B/W/L
(EAd) (rotate) (EAd) Rotates the contents of a general register or a memory location with the carry bit. 1-bit or 2-bit rotation is possible.
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Section 2 CPU
Table 2.9
Instruction BSET
Bit Manipulation Instructions
Size B Function 1 ( of ) Sets a specified bit in the contents of a general register or a memory location to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. if cc, 1 ( of ) If the specified condition is satisfied, this instruction sets a specified bit in a memory location to 1. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The Z flag status can be specified as a condition. 0 ( of ) Clears a specified bit in the contents of a general register or a memory location to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. if cc, 0 ( of ) If the specified condition is satisfied, this instruction clears a specified bit in a memory location to 0. The bit number can be specified by 3-bit immediate data, or by the lower three bits of a general register. The Z flag status can be specified as a condition. ( of ) ( of ) Inverts a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. ( of ) Z Tests a specified bit in the contents of a general register or a memory location and sets or clears the Z flag accordingly. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. C ( of ) C ANDs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C [ ( of )] C ANDs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. C ( of ) C ORs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BSET/cc
B
BCLR
B
BCLR/cc
B
BNOT
B
BTST
B
BAND
B
BIAND
B
BOR
B
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Section 2 CPU
Instruction BIOR
Size B
Function C [~ ( of )] C ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BXOR
B
C ( of ) C Exclusive-ORs the carry flag with a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BIXOR
B
C [~ ( of )] C Exclusive-ORs the carry flag with the inverse of a specified bit in the contents of a general register or a memory location and stores the result in the carry flag. The bit number is specified by 3-bit immediate data.
BLD
B
( of ) C Transfers a specified bit in the contents of a general register or a memory location to the carry flag. The bit number is specified by 3-bit immediate data.
BILD
B
~ ( of ) C Transfers the inverse of a specified bit in the contents of a general register or a memory location to the carry flag. The bit number is specified by 3-bit immediate data.
BST
B
C ( of ) Transfers the carry flag value to a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data.
BSTZ
B
Z ( of ) Transfers the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit immediate data.
BIST
B
C ( of ) Transfers the inverse of the carry flag value to a specified bit in the contents of a general register or a memory location. The bit number is specified by 3-bit immediate data.
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Section 2 CPU
Instruction BISTZ
Size B
Function Z ( of ) Transfers the inverse of the zero flag value to a specified bit in the contents of a memory location. The bit number is specified by 3-bit immediate data.
BFLD
B
(EAs) (bit field) Rd Transfers a specified bit field in memory location contents to the lower bits of a specified general register.
BFST
B
Rs (EAd) (bit field) Transfers the lower bits of a specified general register to a specified bit field in memory location contents.
Table 2.10 Branch Instructions
Instruction BRA/BS BRA/BC BSR/BS BSR/BC Bcc BRA/S -- -- B Size B Function Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a specified address. Tests a specified bit in memory location contents. If the specified condition is satisfied, execution branches to a subroutine at a specified address. Branches to a specified address if the specified condition is satisfied. Branches unconditionally to a specified address after executing the next instruction. The next instruction should be a 1-word instruction except for the block transfer and branch instructions. Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine. Returns from a subroutine, restoring data from the stack to multiple general registers.
JMP BSR JSR RTS RTS/L
-- -- -- -- --
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Section 2 CPU
Table 2.11 System Control Instructions
Instruction TRAPA RTE RTE/L SLEEP LDC Size -- -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Returns from an exception-handling routine, restoring data from the stack to multiple general registers. Causes a transition to a power-down state. #IMM CCR, (EAs) CCR, #IMM EXR, (EAs) EXR Loads immediate data or the contents of a general register or a memory location to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. L STC B/W Rs VBR, Rs SBR Transfers the general register contents to VBR or SBR. CCR (EAd), EXR (EAd) Transfers the contents of CCR or EXR to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. L ANDC ORC XORC NOP B B B -- VBR Rd, SBR Rd Transfers the contents of VBR or SBR to a general register. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter.
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Section 2 CPU
2.7.3
Basic Instruction Formats
The H8SX CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.14 shows examples of instruction formats.
(1) Operation field only op NOP, RTS, etc.
(2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc rn rm MOV.B @(d:16, Rn), Rm, etc.
Figure 2.14 Instruction Formats * Operation Field Indicates the function of the instruction, and specifies the addressing mode and operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. * Register Field Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. * Effective Address Extension 8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. * Condition Field Specifies the branch condition of Bcc instructions.
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Section 2 CPU
2.8
Addressing Modes and Effective Address Calculation
The H8SX CPU supports the 11 addressing modes listed in table 2.12. Each instruction uses a subset of these addressing modes. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2.12 Addressing Modes
No. Addressing Mode 1 2 3 4 5 Register direct Register indirect Register indirect with displacement Index register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Register indirect with pre-increment Register indirect with post-decrement 6 7 8 9 10 11 Absolute address Immediate Program-counter relative Program-counter relative with index register Memory indirect Extended memory indirect Symbol Rn @ERn @(d:2,ERn)/@(d:16,ERn)/@(d:32,ERn) @(d:16, RnL.B)/@(d:16,Rn.W)/@(d:16,ERn.L) @(d:32, RnL.B)/@(d:32,Rn.W)/@(d:32,ERn.L) @ERn* @*ERn @*ERn @ERn* @aa:8/@aa:16/@aa:24/@aa:32 #xx:3/#xx:4/#xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @(RnL.B,PC)/@(Rn.W,PC)/@(ERn.L,PC) @@aa:8 @@vec:7
2.8.1
Register Direct--Rn
The operand value is the contents of an 8-, 16-, or 32-bit general register which is specified by the register field in the instruction code. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
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Section 2 CPU
2.8.2
Register Indirect--@ERn
The operand value is the contents of the memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. In advanced mode, if this addressing mode is used in a branch instruction, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). 2.8.3 Register Indirect with Displacement --@(d:2, ERn), @(d:16, ERn), or @(d:32, ERn)
The operand value is the contents of a memory location which is pointed to by the sum of the contents of an address register (ERn) and a 16- or 32-bit displacement. ERn is specified by the register field of the instruction code. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. This addressing mode has a short format (@(d:2, ERn)). The short format can be used when the displacement is 1, 2, or 3 and the operand is byte data, when the displacement is 2, 4, or 6 and the operand is word data, or when the displacement is 4, 8, or 12 and the operand is longword data. 2.8.4 Index Register Indirect with Displacement--@(d:16,RnL.B), @(d:32,RnL.B), @(d:16,Rn.W), @(d:32,Rn.W), @(d:16,ERn.L), or @(d:32,ERn.L)
The operand value is the contents of a memory location which is pointed to by the sum of the following operation result and a 16- or 32-bit displacement: a specified bits of the contents of an address register (RnL, Rn, ERn) specified by the register field in the instruction code are zeroextended to 32-bit data and multiplied by 1, 2, or 4. The displacement is included in the instruction code and the 16-bit displacement is sign-extended when added to ERn. If the operand is byte data, ERn is multiplied by 1. If the operand is word or longword data, ERn is multiplied by 2 or 4, respectively.
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Section 2 CPU
2.8.5
Register Indirect with Post-Increment, Pre-Decrement, Pre-Increment, or Post-Decrement--@ERn+, @-ERn, @+ERn, or @ERn-
* Register indirect with post-increment--@ERn+ The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. * Register indirect with pre-decrement--@-ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is subtracted from the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. * Register indirect with pre-increment--@+ERn The operand value is the contents of a memory location which is pointed to by the following operation result: the value 1, 2, or 4 is added to the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After that, the operand value is stored in the address register. The value added is 1 for byte access, 2 for word access, or 4 for longword access. * Register indirect with post-decrement--@ERn- The operand value is the contents of a memory location which is pointed to by the contents of an address register (ERn). ERn is specified by the register field of the instruction code. After the memory location is accessed, 1, 2, or 4 is subtracted from the address register contents and the remainder is stored in the address register. The value subtracted is 1 for byte access, 2 for word access, or 4 for longword access. using this addressing mode, data to be written is the contents of the general register after calculating an effective address. If the same general register is specified in an instruction and two effective addresses are calculated, the contents of the general register after the first calculation of an effective address is used in the second calculation of an effective address. Example 1: MOV.W R0, @ER0+ When ER0 before execution is H'12345678, H'567A is written at H'12345678.
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Section 2 CPU
Example 2: MOV.B @ER0+, @ER0+ When ER0 before execution is H'00001000, H'00001000 is read and the contents is written at H'00001001. After execution, ER0 is H'00001002. 2.8.6 Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32
The operand value is the contents of a memory location which is pointed to by an absolute address included in the instruction code. There are 8-bit (@aa:8), 16-bit (@aa:16), 24-bit (@aa:24), and 32-bit (@aa:32) absolute addresses. To access the data area, the absolute address of 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) is used. For an 8-bit absolute address, the upper 24 bits are specified by SBR. For a 16bit absolute address, the upper 16 bits are sign-extended. A 32-bit absolute address can access the entire address space. To access the program area, the absolute address of 24 bits (@aa:24) or 32 bits (@aa:32) is used. For a 24-bit absolute address, the upper 8 bits are all assumed to be 0 (H'00). Table 2.13 shows the accessible absolute address ranges. Table 2.13 Absolute Address Access Ranges
Absolute Address Data area 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program area 24 bits (@aa:24) 32 bits (@aa:32) Normal Mode Middle Mode Advanced Mode Maximum Mode
A consecutive 256-byte area (the upper address is set in SBR) H'0000 to H'FFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF H'00000000 to H'00007FFF, H'FFFF8000 to H'FFFFFFFF H'00000000 to H'FFFFFFFF H'00000000 to H'00FFFFFF H'00000000 to H'00FFFFFF H'00000000 to H'FFFFFFFF
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Section 2 CPU
2.8.7
Immediate--#xx
The operand value is 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) data included in the instruction code. This addressing mode has short formats in which 3- or 4-bit immediate data can be used. When the size of immediate data is less than that of the destination operand value (byte, word, or longword) the immediate data is zero-extended. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, for specifying a bit number. The BFLD and BFST instructions contain 8-bit immediate data in the instruction code, for specifying a bit field. The TRAPA instruction contains 2-bit immediate data in the instruction code, for specifying a vector address. 2.8.8 Program-Counter Relative--@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of an 8- or 16-bit displacement in the instruction code and the 32-bit address of the PC contents. The 8-bit or 16-bit displacement is sign-extended to 32 bits when added to the PC contents. The PC contents to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). 2.8.9 Program-Counter Relative with Index Register--@(RnL.B, PC), @(Rn.W, PC), or @(ERn.L, PC)
This mode is used in the Bcc and BSR instructions. The operand value is a 32-bit branch address, which is the sum of the following operation result and the 32-bit address of the PC contents: the contents of an address register specified by the register field in the instruction code (RnL, Rn, or ERn) is zero-extended and multiplied by 2. The PC contents to which the displacement is added is the address of the first byte of the next instruction. In advanced mode, only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00).
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Section 2 CPU
2.8.10
Memory Indirect--@@aa:8
This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by an 8-bit absolute address in the instruction code. The upper bits of an 8-bit absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in other modes). In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00). Note that the top part of the address range is also used as the exception handling vector area. A vector address of an exception handling other than a reset or a CPU address error can be changed by VBR. Figure 2.15 shows an example of specification of a branch address using this addressing mode.
Specified by @aa:8
Branch address
Specified by @aa:8
Reserved Branch address
(a) Normal Mode
(b) Advanced Mode
Figure 2.15 Branch Address Specification in Memory Indirect Mode
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Section 2 CPU
2.8.11
Extended Memory Indirect--@@vec:7
This mode can be used by the JMP and JSR instructions. The operand value is a branch address, which is the contents of a memory location pointed to by the following operation result: the sum of 7-bit data in the instruction code and the value of H'80 is multiplied by 2 or 4. The address range to store a branch address is H'0100 to H'01FF in normal mode and H'000200 to H'0003FF in other modes. In assembler notation, an address to store a branch address is specified. In normal mode, the memory location is pointed to by word-size data and the branch address is 16 bits long. In other modes, the memory location is pointed to by longword-size data. In middle or advanced mode, the first byte of the longword-size data is assumed to be all 0 (H'00). 2.8.12 Effective Address Calculation
Tables 2.14 and 2.15 show how effective addresses are calculated in each addressing mode. The lower bits of the effective address are valid and the upper bits are ignored (zero extended or sign extended) according to the CPU operating mode. The valid bits in middle mode are as follows: * The lower 16 bits of the effective address are valid and the upper 16 bits are sign-extended for the transfer and operation instructions. * The lower 24 bits of the effective address are valid and the upper eight bits are zero-extended for the branch instructions.
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Section 2 CPU
Table 2.14 Effective Address Calculation for Transfer and Operation Instructions
No. 1
Addressing Mode and Instruction Format Immediate
op IMM
Effective Address Calculation
Effective Address (EA)
2
Register direct
op rm rn 31
General register contents
3
Register indirect
op
r
0
31
0
4
Register indirect with 16-bit displacement
op disp
r
31
General register contents
0 15
Sign extension
31
0
disp
+
31
0
Register indirect with 32-bit displacement
op
r
31
General register contents
0
+
31
0
disp
disp
5
Index register indirect with 16-bit displacement
31
0 Zero extension Contents of general register (RL, R, or ER) 1, 2, or 4 15
Sign extension
x +
31
0
op disp
r
31
0
disp
Index register indirect with 32-bit displacement
31
0 Zero extension Contents of general register (RL, R, or ER) 1, 2, or 4 0
disp
x +
31
0
op
r
31
disp
6
Register indirect with post-increment or post-decrement
op
r
31
General register contents
0
1, 2, or 4
31
0
Register indirect with pre-increment or pre-decrement
op
r
31
General register contents
0
1, 2, or 4
31
0
7
8-bit absolute address
31
op
aa
SBR
7
aa
0
31
0
16-bit absolute address
op
aa
31
Sign extension
15
aa
0
31
0
32-bit absolute address
op
aa
31
aa
0
31
0
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Section 2 CPU
Table 2.15 Effective Address Calculation for Branch Instructions
No. Addressing Mode and Instruction Format Register indirect
op
r
Effective Address Calculation
31
General register contents
Effective Address (EA)
0 31
0
1
2
Program-counter relative with 8-bit displacement
31
PC contents
0 7
Sign extension
31
0
disp
+
31
0
op
disp
Program-counter relative with 16-bit displacement
31
PC contents
0 15
Sign extension
op disp
31
0
disp
+
31
0
3
Program-counter relative with index register
31
Zero extension Contents of general register (RL, R, or ER)
0
op
r
31
PC contents
2
0
x +
31
0
4
24-bit absolute address
op aa
Zero 31 extension 23
0
aa
31
0
32-bit absolute address
op
aa
31
aa
0
31
0
5
Memory indirect
31
op aa
Zero extension
7
aa
0 0 31 0
31
Memory contents
6
Extended memory indirect
31
op
vec
Zero extension
7 1
0 vec
2 or 4
x
31
31
Memory contents
0
0
31
0
2.8.13
MOVA Instruction
The MOVA instruction stores the effective address in a general register. 1. Firstly, data is obtained by the addressing mode shown in item 2 of table 2.14. 2. Next, the effective address is calculated using the obtained data as the index by the addressing mode shown in item 5 of table 2.14. The obtained data is used instead of the general register. The result is stored in a general register. For details, see H8SX Family Software Manual.
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Section 2 CPU
2.9
Processing States
The H8SX CPU has five main processing states: the reset state, exception-handling state, program execution state, bus-released state, and program stop state. Figure 2.16 indicates the state transitions. * Reset state In this state the CPU and internal peripheral modules are all initialized and stopped. When the RES input goes low, all current processing stops and the CPU enters the reset state. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. For details, see section 6, Exception Handling. The reset state can also be entered by a watchdog timer overflow when available. * Exception-handling state The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to activation of an exception source, such as, a reset, trace, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception handling vector table and branches to that address. For further details, see section 6, Exception Handling. * Program execution state In this state the CPU executes program instructions in sequence. * Bus-released state The bus-released state occurs when the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts operations. * Program stop state This is a power-down state in which the CPU stops operating. The program stop state occurs when a SLEEP instruction is executed or the CPU enters hardware standby mode. For details, see section 27, Power-Down Modes.
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Section 2 CPU
Reset state*
RES = high Exception-handling state Request for exception handling STBY = high, RES = low Interrupt request Bus-released state Bus request Bus request End of bus request Program stop state SLEEP instruction End of bus request
End of exception handling
Program execution state
Note:
A transition to hardware standby mode occurs whenever the STBY signal goes low. * A transition to the reset state occurs when the RES signal goes low in all states except hardware standby mode. A transition can also be made to the reset state when the watchdog timer overflows.
Figure 2.16 State Transitions
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1 Operating Mode Selection
This LSI has seven operating modes (modes 1, 2, 3, 4, 5, 6, and 7). The operating mode is selected by the setting of mode pins MD2 to MD0. Table 3.1 lists MCU operating mode settings. Table 3.1 MCU Operating Mode Settings
CPU Operating Mode Advanced mode Address Space LSI Initiation Mode On-Chip ROM Enabled Enabled External Data Bus Width Default Max.
MCU Operating Mode MD2 1 2 3 0 0 0
MD1 0 1 1
MD0 1 0 1
16 Mbytes User boot mode Boot mode

16 bits 8 bits 8 bits
16 bits 16 bits 16 bits
Boundary scan Enabled enabled single-chip mode On-chip ROM disabled extended mode On-chip ROM enabled extended mode Single-chip mode Disabled Disabled Enabled
4 5 6
1 1 1
0 0 1
0 1 0
16 bits 16 bits 16 bits
7
1
1
1
Enabled
16 bits
In this LSI, an advanced mode as the CPU operating mode and a 16-Mbyte address space are available. The initial external bus widths are 8 bits or 16 bits. As the LSI initiation mode, the external extended mode, on-chip ROM initiation mode, or single-chip initiation mode can be selected. Modes 1 and 2 are the user boot mode and the boot mode, respectively, in which the flash memory can be programmed and erased. For details on the user boot mode and boot mode, see section 24, Flash Memory.
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Section 3 MCU Operating Modes
Mode 3 is the boundary scan function enabled single-chip mode. For details on the boundary scan function, see section 25, Boundary Scan. Mode 7 is a single-chip initiation mode. All I/O ports can be used as general input/output ports. The external address space cannot be accessed in the initial state, but setting the EXPE bit in the system control register (SYSCR) to 1 enables to use the external address space. After the external address space is enabled, ports H and I can be used as a data bus and ports D, E, and F as an address output bus by specifying the data direction register (DDR) for each port. When the external address space is not in use, ports J and K can be used by setting the PCJKE bit in the port function control register D (PFCRD) to 1. Modes 4 to 6 are external extended modes, in which the external memory and devices can be accessed. In the external extended modes, the external address space can be designated as 8-bit or 16-bit address space for each area by the bus controller after starting program execution. If 16-bit address space is designated for any one area, it is called the 16-bit bus widths mode. If 8bit address space is designated for all areas, it is called the 8-bit bus width mode.
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Section 3 MCU Operating Modes
3.2
Register Descriptions
The following registers are related to the operating mode setting. * Mode control register (MDCR) * System control register (SYSCR) 3.2.1 Mode Control Register (MDCR)
MDCR indicates the current operating mode. When MDCR is read from, the states of signals MD3 to MD0 are latched. Latching is released by a reset.
Bit Bit Name Initial Value R/W
Bit Bit Name Initial Value R/W
15 0 R
7 0 R
14 1 R
6 1 R
13 0 R
5 0 R
12 1 R
4 1 R
11 MDS3 Undefined* R
3 Undefined* R
10 MDS2 Undefined* R
2 Undefined* R
9 MDS1 Undefined* R
1 Undefined* R
8 MDS0 Undefined* R
0 Undefined* R
Note: * Determined by pins MD2 to MD0.
Bit 15 14 13 12 11 10 9 8
Bit Name MDS3 MDS2 MDS1 MDS0
Initial Value R/W 0 1 0 1 Undefined* Undefined* Undefined* Undefined* R R R R R R R R
Descriptions Reserved These are read-only bits and cannot be modified.
Mode Select 3 to 0 These bits indicate the operating mode selected by the mode pins (MD2 to MD0) (see table 3.2). When MDCR is read, the signal levels input on pins MD2 to MD0 are latched into these bits. These latches are released by a reset.
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Section 3 MCU Operating Modes
Bit 7 6 5 4 3 2 1 0 Note: *
Bit Name
Initial Value R/W 0 1 0 1 Undefined* Undefined* Undefined* Undefined* R R R R R R R R
Descriptions Reserved These are read-only bits and cannot be modified.
Determined by pins MD2 to MD0.
Table 3.2
Settings of Bits MDS3 to MDS0
Mode Pins MD2 0 0 0 1 1 1 1 MD1 0 1 1 0 0 1 1 MD0 1 0 1 0 1 0 1 MDS3 1 1 0 0 0 0 0 MDS2 1 1 1 0 0 1 1 MDCR MDS1 0 0 0 1 0 0 0 MDS0 1 0 0 0 1 1 0
MCU Operating Mode 1 2 3 4 5 6 7
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Section 3 MCU Operating Modes
3.2.2
System Control Register (SYSCR)
SYSCR controls MAC saturation operation, selects bus width mode for instruction fetch, sets external bus mode, enables/disables the on-chip RAM, and selects the DTC address mode.
Bit Bit Name Initial Value R/W
Bit Bit Name Initial Value R/W
15 1 R/W
7 0 R/W
14 1 R/W
6 0 R/W
13 MACS 0 R/W
5 0 R/W
12 1 R/W
4 0 R/W
11 FETCHMD 0 R/W
3 0 R/W
10 Undefined* R
2 0 R/W
9 EXPE Undefined* R/W
1 DTCMD 1 R/W
8 RAME 1 R/W
0 1 R/W
Note: * The initial value depends on the startup mode.
Bit 15 14 13
Bit Name MACS
Initial Value 1 1 0
R/W R/W R/W R/W
Descriptions Reserved These bits are always read as 1. The write value should always be 1. MAC Saturation Operation Control Selects either saturation operation or non-saturation operation for the MAC instruction. 0: MAC instruction is non-saturation operation 1: MAC instruction is saturation operation
12
1
R/W
Reserved This bit is always read as 1. The write value should always be 1.
11
FETCHMD 0
R/W
Instruction Fetch Mode Select This LSI can prefetch an instruction in units of 16 bits or 32 bits. Select the bus width for instruction fetch depending on the used memory for the storage of programs. 0: 32-bit mode 1: 16-bit mode
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Section 3 MCU Operating Modes
Bit 10
Initial Bit Name Value
1
R/W
Descriptions Reserved This bit is fixed at 1 in on-chip ROM enabled mode, and 0 in on-chip ROM disabled mode. This bit cannot be changed.
Undefined* R
9
EXPE
Undefined*1 R/W
External Bus Mode Enable Selects external bus mode. In external extended mode, this bit is fixed 1 and cannot be changed. In single-chip mode, the initial value of this bit is 0, and can be read from or written to when PCKJE = 0. Do not write to this 2 bit when PCKJE = 1* . When writing 0 to this bit after reading EXPE = 1, an external bus cycle should not be executed. The external bus cycle may be carried out in parallel with the internal bus cycle depending on the setting of the write data buffer function and the state the EXDMAC releases the bus mastership. 0: External bus disabled 1: External bus enabled
8
RAME
1
R/W
RAM Enable Enables or disables the on-chip RAM. This bit is initialized when the reset state is released. Do not write 0 during access to the on-chip RAM. 0: On-chip RAM disabled 1: On-chip RAM enabled
7 to 2
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
1
DTCMD
1
R/W
DTC Mode Select Selects DTC operating mode. 0: DTC is in full-address mode 1: DTC is in short address mode
0
1
R/W
Reserved This bit is always read as 1. The write value should always be 1.
Notes: 1. The initial value depends on the LSI initiation mode. 2. For details on the settings of the EXPE and PCJKE bits when the external address space is in use, see section 13.3.12, Port Function Control Register D (PFCRD).
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Section 3 MCU Operating Modes
3.3
3.3.1
Operating Mode Descriptions
Mode 1
This is the user boot mode for the flash memory. The LSI operates in the same way as in mode 7 except for programming and erasing of the flash memory. For details, see section 24, Flash Memory. 3.3.2 Mode 2
This is the boot mode for the flash memory. The LSI operates in the same way as in mode 7 except for programming and erasing of the flash memory. For details, see section 24, Flash Memory. 3.3.3 Mode 3
This is the boundary scan function enabled single-chip activation mode. The operation is the same as mode 7 except for the boundary scan function. For details on the boundary scan function, see section 25, Boundary Scan. 3.3.4 Mode 4
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is disabled. The initial bus width mode immediately after a reset is 16 bits, with 16-bit access to all areas. Ports D, E, and F function as an address bus, ports H and I function as a data bus, and parts of ports A and B function as bus control signals. However, if all areas are designated as an 8-bit access space by the bus controller, the bus mode switches to 8 bits, and only port H functions as a data bus.
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Section 3 MCU Operating Modes
3.3.5
Mode 5
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is disabled. The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas. Ports D, E, and F function as an address bus, port H functions as a data bus, and parts of ports A and B function as bus control signals. However, if any area is designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits, and ports H and I function as a data bus. 3.3.6 Mode 6
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is enabled. The initial bus width mode immediately after a reset is eight bits, with 8-bit access to all areas. Ports D, E, and F function as input ports, but they can be used as an address bus by specifying the data direction register (DDR) for each port. For details, see section 13, I/O Ports. Port H functions as a data bus, and parts of ports A and B function as bus control signals. However, if any area is designated as a 16-bit access space by the bus controller, the bus width mode switches to 16 bits, and ports H and I function as a data bus. 3.3.7 Mode 7
The CPU operating mode is advanced mode in which the address space is 16 Mbytes, and the onchip ROM is enabled. All I/O ports can be used as general input/output ports. The external address space cannot be accessed in the initial state, but setting the EXPE bit in the system control register (SYSCR) to 1 enables the external address space. After the external address space is enabled, ports H and I can be used as a data bus and ports D, E, and F as an address output bus by specifying the data direction register (DDR) for each port. When the external address space is not in use, ports J and K can be used by setting the PCJKE bit in the port function control register D (PFCRD) to 1. For details, see section 13, I/O Ports.
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Section 3 MCU Operating Modes
3.3.8
Pin Functions
Table 3.3 lists the pin functions in each operating mode. Table 3.3
MCU Operating Mode 1 2 3 4 5 6 7 PA7 P*/C P*/C P*/C P/C* P/C* P/C* P*/C
Pin Functions in Each Operating Mode (Advanced Mode)
Port A PA6 to PA3 P*/C P*/C P*/C P/C* P/C* P/C* P*/C PA2 to PA0 P*/C P*/C P*/C P*/C P*/C P*/C P*/C PB3 to PB1 P*/C P*/C P*/C P*/C P*/C P*/C P*/C PB0 P*/C P*/C P*/C P/C* P/C* P*/C P*/C Port D P*/A P*/A P*/A A A P*/A P*/A Port E P*/A P*/A P*/A A A P*/A P*/A Port B Port F PF4 to PF0 P*/A P*/A P*/A A A P*/A P*/A Port H P*/D P*/D P*/D D D D P*/D Port I P*/D P*/D P*/D P/D* P*/D P*/D P*/D
[Legend] P: I/O port A: Address bus output D: Data bus input/output C: Control signals, clock input/output *: Immediately after a reset
3.4
3.4.1
Address Map
Address Map
Figures 3.1 to 3.3 show the address map in each operating mode.
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Section 3 MCU Operating Modes
Modes 1 and 2 User boot mode, boot mode (Advanced mode)
H'000000
Modes 3 and 7 Boundary scan enabled single-chip mode, single-chip mode (Advanced mode) H'000000 H'000000
Modes 4 and 5 On-chip ROM disabled extended mode (Advanced mode)
On-chip ROM
On-chip ROM
H'080000
H'100000
Access prohibited area
H'080000
H'100000
Access prohibited area
External address space
External address space/ reserved area*1*3
External address space/ reserved area*1*3
H'FD9000 Reserved area*3 H'FDC000 External address space/ reserved area*1*3
H'FEC000
H'FD9000 Reserved area*3 H'FDC000 External address space/ reserved area*1*3 H'FEC000
Reserved areac
H'FD9000 Reserved area*3 H'FDC000 External address space H'FEC000 Reserved area*3
Reserved area*3
H'FF2000 On-chip RAM*2
H'FF2000
On-chip RAM/
External address space*4
H'FF2000 On-chip RAM/
External address space*4
H'FFC000 External address space/ reserved area*1*3 H'FFEA00 On-chip I/O registers H'FFFF00 H'FFFF20
H'FFFFFF
Notes:1. 2. 3. 4.
H'FFC000 External address space/ reserved area*1*3 H'FFEA00 On-chip I/O registers H'FFFF00 H'FFFF20 H'FFFFFF External address space/ reserved area*1*3 On-chip I/O registers
H'FFC000 External address space H'FFEA00 On-chip I/O registers H'FFFF00 External address space H'FFFF20
H'FFFFFF
External address space/ reserved area*1*3 On-chip I/O registers
On-chip I/O registers
This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. The on-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. Do not access the reserved areas. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
Figure 3.1 Address Map in Each Operating Mode of H8SX/1658R and 1658M (1)
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Section 3 MCU Operating Modes
Mode 6 On-chip ROM enabled extended mode (Advanced mode)
H'000000
On-chip ROM
H'100000
External address space
H'FD9000
Access prohibited area
H'FDC000
External address space
H'FEC000 H'FEE000 Reserved area*1
On-chip RAM/
External address space*2
H'FFC000
External address space H'FFEA00
On-chip I/O registers
H'FFFF00
External address space
H'FFFF20
On-chip I/O registers
H'FFFFFF
Notes: 1. Do not access the reserved area. 2. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
Figure 3.1 Address Map in Each Operating Mode of H8SX/1658R and H8SX/1658M (2)
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Section 3 MCU Operating Modes
Modes 1 and 2 User boot mode, boot mode (Advanced mode)
H'000000
Modes 3 and 7 Boundary scan enabled single-chip mode, single-chip mode (Advanced mode) H'000000 H'000000
Modes 4 and 5 On-chip ROM disabled extended mode (Advanced mode)
On-chip ROM
On-chip ROM
H'080000
H'100000
Access prohibited area
H'080000
H'100000
Access prohibited area
External address space
External address space/ reserved area*1*3
External address space/ reserved area*1*3
H'FD9000 Access prohibited area H'FDC000 External address space/ reserved area*1*3
H'FEC000
H'FD9000 Access prohibited area H'FDC000 External address space/ reserved area*1*3 H'FEC000
Access prohibited area
H'FD9000 Access prohibited area H'FDC000 External address space H'FEC000 Access prohibited area H'FF2000 On-chip RAM/
External address space*4
Access prohibited area
H'FF2000 On-chip RAM*2
H'FF2000
On-chip RAM/
External address space*4
H'FFC000 External address space/ reserved area*1*3 H'FFEA00 On-chip I/O registers H'FFFF00 H'FFFF20
H'FFFFFF
Notes:1. 2. 3. 4.
H'FFC000 External address space/ reserved area*1*3 H'FFEA00 On-chip I/O registers H'FFFF00 H'FFFF20 H'FFFFFF External address space/ reserved area*1*3 On-chip I/O registers
H'FFC000 External address space H'FFEA00 On-chip I/O registers H'FFFF00 External address space H'FFFF20
H'FFFFFF
External address space/ reserved area*1*3 On-chip I/O registers
On-chip I/O registers
This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. The on-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. Do not access the reserved areas. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
Figure 3.2 Address Map in Each Operating Mode of H8SX/1654R and H8SX/1654M (1)
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Section 3 MCU Operating Modes
Mode 6 On-chip ROM enabled extended mode (Advanced mode)
H'000000
On-chip ROM
H'080000
H'100000
Access prohibited area
External address space
H'FD9000 Access prohibited area H'FDC000 External address space
Reserved area*1
H'FEC000
H'FF2000
On-chip RAM/
External address space*2
H'FFC000 External address space H'FFEA00 On-chip I/O registers H'FFFF00 External address space H'FFFF20
H'FFFFFF
Notes: 1. Do not access the reserved area. 2. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
On-chip I/O registers
Figure 3.2 Address Map in Each Operating Mode of H8SX/1654R and H8SX/1654M (2)
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Section 3 MCU Operating Modes
Modes 1 and 2 User boot mode, boot mode (Advanced mode) H'000000
Modes 3 and 7 Boundary scan enabled single-chip mode, single-chip mode (Advanced mode) H'000000 H'000000
Modes 4 and 5 On-chip ROM disabled extended mode (Advanced mode)
On-chip ROM
On-chip ROM
H'060000 H'100000
Access prohibited area
H'060000 H'100000
Access prohibited area External address space
External address space/ reserved area*1*3
External address space/ reserved area*1*3
H'FD9000 Access prohibited area H'FDC000 External address space/ reserved area*1*3 H'FEC000 Reserved area*3
H'FD9000 Access prohibited area H'FDC000 External address space/ reserved area*1*3 H'FEC000 Reserved area*3
H'FD9000 Access prohibited area H'FDC000 External address space H'FEC000 Reserved area*3
H'FF2000 On-chip RAM*2
H'FF2000 On-chip RAM/
External address space*4
H'FF2000 On-chip RAM/
External address space*4
H'FFC000 External address space/ reserved area*1*3 H'FFEA00 On-chip I/O registers H'FFFF00 H'FFFF20 H'FFFFFF External address space/ reserved area*1*3 On-chip I/O registers
H'FFC000 External address space/ reserved area*1*3 H'FFEA00 On-chip I/O registers H'FFFF00 H'FFFF20 H'FFFFFF External address space/ reserved area*1*3 On-chip I/O registers
H'FFC000 External address space H'FFEA00 On-chip I/O registers H'FFFF00 External address space H'FFFF20 H'FFFFFF On-chip I/O registers
Notes: 1. This area is specified as the external address space when EXPE = 1 and the reserved area when EXPE = 0. 2. The on-chip RAM is used for flash memory programming. Do not clear the RAME bit in SYSCR to 0. 3. Do not access the reserved areas. 4. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
Figure 3.3 Address Map in Each Operating Mode of H8SX/1653R and 1653M (1)
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Section 3 MCU Operating Modes
Mode 6 On-chip ROM enabled extended mode (Advanced mode)
H'000000
On-chip ROM
H'060000
H'100000
Access prohibited area
External address space
H'FD9000 Access prohibited area H'FDC000 External address space
H'FEC000
Access prohibited area
H'FF2000
On-chip RAM/
External address space*2
H'FFC000 Reserved area*1 H'FFEA00 On-chip I/O registers H'FFFF00 External address space H'FFFF20
H'FFFFFF
Notes: 1. Do not access the reserved area. 2. This area is specified as the external address space by clearing the RAME bit in SYSCR to 0.
On-chip I/O registers
Figure 3.3 Address Map in Each Operating Mode of H8SX/1653R and 1653M (2)
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Section 3 MCU Operating Modes
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Section 4 Reset
Section 4 Reset
4.1 Types of Reset
There are three types of reset: a pin reset, power-on reset*, voltage-monitoring reset*, deep software standby reset, and watchdog timer reset. Table 4.1 shows the reset names and sources. The internal state and pins are initialized by a reset. Figure 4.1 shows the reset targets to be initialized. When using power-on reset* and voltage monitoring reset*, RES pin must be fixed high. Table 4.1
Reset Name Pin reset Power-on reset* Voltage-monitoring reset* Deep software standby reset Watchdog timer reset
Reset Names And Sources
Source Voltage input to the RES pin is driven low. Vcc rises or lowers Vcc falls (voltage-detection: Vdet) Deep software standby mode is canceled by an interrupt. The watchdog timer overflows.
Note: * Supported only by the H8SX/1658M Group.
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Section 4 Reset
RES
Pin reset
Power-on rest circuit registers* (RSTSR.PORF)
Registers for voltage-monitoring* Vcc Power-on reset circuit* Power-on reset RSTSR.LVDF LVDCR.LVDE LVDRI Registers related to power-down mode RSTSR.DPSRSTF DPSBYCR, DPSWCR DPSIER, DPSIFR DPSIEGR, DPSBKRn
Voltage detection circuit*
Voltage-monitoring reset
Deep software standby reset generation circuit
Deep software standby reset
RSTCSR for WDT
Watchdog timer
Watchdog timer reset
Internal state other than above, and pin states.
Note: * Supported only by the H8SX/1658M Group.
Figure 4.1 Block Diagram of Reset Circuit
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Section 4 Reset
Note that some registers are not initialized by any of the reset. The following describes the CPU internal registers. The PC, one of the CPU internal registers, is initialized by loading the start address from vector addresses with the reset exception handling. At this time, the T bit in EXR is cleared to 0 and the I bits in EXR and CCR are set to 1. The general registers, MAC, and other bits in CCR are not initialized. The initial value of the SP (ER7) is undefined. The SP should be initialized using the MOV.L instruction immediately after a reset. For details, see section 2, CPU. For other registers that are not initialized by a reset, see register descriptions in each section. When a reset is canceled, the reset exception handling is started. For the reset exception handling, see section 6.3, Reset.
4.2
Input/Output Pin
Table 4.2 shows the pin related to reset. Table 4.2
Pin Name Reset
Pin Configuration
Symbol RES I/O Input Function Reset input
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Section 4 Reset
4.3
Register Descriptions
This LSI has the following registers for reset. * Reset status register (RSTSR) * Reset control/status register (RSTCSR) 4.3.1 Reset Status Register (RSTSR)
RSTSR indicates a source for generating an internal reset and voltage monitoring interrupt.
Bit Bit name Initial value:
7 DPSRSTF 0 R/(W)*1
6
5
4
3
2
LVDF*2 0*3
1
0*3
0
PORF*2 0*3
0 R/W
0 R/W
0 R/W
0 R/W
R/W: Note: 1. 2. 3. 4. 5.
R/W*4
R/W
R/W*5
Only 0 can be written to clear the flag. Supported only by the H8SX/1658M Group. Initial value is undefined in the H8SX/1658M Group. Only 0 can be written to clear the flag in the H8SX/1658M Group. Only read is possible in the H8SX/1658M Group.
Bit 7
Bit Name DPSRSTF
Initial Value 0
R/W R/(W)*
1
Description Deep Software Standby Reset Flag Indicates that deep software standby mode is canceled by an interrupt source specified with DPSIER or DPSIEGR and an internal reset is generated. [Setting condition] When deep software standby mode is canceled by an interrupt source. [Clearing conditions] * * When this bit is read as 1 and then written by 0.
2 When a pin reset, power-on reset* and voltage2 monitoring reset* is generated.
6 to 3
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
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Section 4 Reset
*
H8SX/1658R Group
All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.
2 to 0
*
2
H8SX/1658M Group
LVDF Undefined R/(W)*1 LVD Flag This bit indicates that the voltage detection circuit has detected a low voltage (Vcc at or below Vdet). [Setting condition] Vcc falling to or below Vdet. [Clearing condition] * After Vcc has exceeded Vdet and the specified stabilization period has elapsed, writing 0 to the bit after reading it as 1. Generation of a pin reset or power-on reset.
* 1 0 -- PORF Undefined Undefined R/W R
Reserved The write value should always be 0. Power-on Reset Flag This bit indicates that a power-on reset has been generated. [Setting condition] Generation of a power-on reset [Clearing condition] Generation of a pin reset
Note:
1. Only 0 can be written to clear the flag. 2. Supported only by the H8SX/1658M Group.
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Section 4 Reset
4.3.2
Reset Control/Status Register (RSTCSR)
RSTCSR controls an internal reset signal generated by the watchdog timer and selects the internal reset signal type. RSTCSR is initialized to H'1F by a pin reset or a deep software standby reset, but not by the internal reset signal generated by a WDT overflow.
Bit Bit name Initial value: 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 0 R/W 4 1 R 3 1 R 2 1 R 1 1 R 0 1 R
R/W:
Note: * Only 0 can be written to clear the flag.
Bit 7
Bit Name
Initial Value
R/W
Description
WOVF 0
R/(W)* Watchdog Timer Overflow Flag This bit is set when TCNT overflows in watchdog timer mode, but not set in interval timer mode. Only 0 can be written to. [Setting condition] When TCNT overflows (H'FF H'00) in watchdog timer mode. [Clearing condition] When this bit is read as 1 and then written by 0. (The flag must be read after writing of 0, when this bit is cleared by the CPU using an interrupt.)
6
RSTE
0
R/W
Reset Enable Selects whether or not the LSI internal state is reset by a TCNT overflow in watchdog timer mode. 0: Internal state is not reset when TCNT overflows. (Although this LSI internal state is not reset, TCNT and TCSR of the WDT are reset.) 1: Internal state is reset when TCNT overflows.
5
0
R/W
Reserved Although this bit is readable/writable, operation is not affected by this bit.
4 to 0 Note: *
1
R
Reserved These are read-only bits but cannot be modified.
Only 0 can be written to clear the flag.
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Section 4 Reset
4.4
Pin Reset
This is a reset generated by the RES pin. When the RES pin is driven low, all the processing in progress is aborted and the LSI enters a reset state. In order to firmly reset the LSI, the STBY pin should be set to high and the RES pin should be held low at least for 20 ms at a power-on. During operation, the RES pin should be held low at least for 20 states.
4.5
Power-on Reset (POR) (H8SX/1658M Group)
This is an internal reset generated by the power-on reset circuit. If RES is in the high-level state when power is supplied, a power-on reset is generated. After Vcc has exceeded Vpor and the specified period (power-on reset time) has elapsed, the chip is released from the power-on reset state. The power-on reset time is a period for stabilization of the external power supply and the LSI circuit. If RES is at the high-level when the power-supply voltage (Vcc) falls to or below Vpor, a poweron reset is generated. The chip is released after Vcc has risen above Vpor and the power-on reset time has elapsed. After a power-on reset has been generated, the PORF bit in RSTSR is set to 1. The PORF bit is in a read-only register and is only initialized by a pin reset. Figure 4.2 shows the operation of a power-on reset.
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Section 4 Reset
Vpor*1
External power supply Vcc
Reset state
Reset state
RES pin POR signal ("L" is valid)
Vcc
Vcc
V V
Reset signal Vcc ("L" is valid) Pin reset and OR signal for POR
V
tPOR*2
Set Set
tPOR*2
PORF
Vcc
Notes: For details of the electrical characteristics, see section 29, Electrical Characteristics. 1. VPOR shows a level of power-on reset detection level. 2. TPOR shows a time for power-on reset.
Figure 4.2 Operation of a Power on Reset
4.6
Power Supply Monitoring Reset (H8SX/1658M Group)
This is an internal reset generated by the power-supply detection circuit. When Vcc falls below Vdet in the state where the LVDE bit in LVDCR has been set to 1 and the LVDRI bit has been cleared to 0, a voltage-monitoring reset is generated. When Vcc subsequently rises above Vdet, release from the voltage-monitoring reset proceeds after a specified time has elapsed. For details of the voltage-monitoring reset, see section 5, Voltage Detection Circuit (LVD), and section 29, Electrical Characteristics.
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Section 4 Reset
4.7
Deep Software Standby Reset
This is an internal reset generated when deep software standby mode is canceled by an interrupt. When deep software standby mode is canceled, a deep software standby reset is generated, and simultaneously, clock oscillation starts. After the time specified with DPSWCR has elapsed, the deep software standby reset is canceled. For details of the deep software standby reset, see section 27, Power-Down Modes.
4.8
Watchdog Timer Reset
This is an internal reset generated by the watchdog timer. When the RSTE bit in RSTCSR is set to 1, a watchdog timer reset is generated by a TCNT overflow. After a certain time, the watchdog timer reset is canceled. For details of the watchdog timer reset, see section 17, Watchdog Timer (WDT).
4.9
Determination of Reset Generation Source
Reading RSTCSR, RSTSR, and LVDCR* of the voltage detection circuit determines which reset was used to execute the reset exception handling. Figure 4.2 shows an example the flow to identify a reset generation source. Note: * Supported only by the H8SX/1658M Group.
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Section 4 Reset
Reset exception handling
RSTCSR.RSTE=1 and RSTCSR.WOVF=1
No
Yes
RSTSR. DPSRSTF=1
No
Yes
LVDCR.LVDE=1 & LVDCR.LCDRI=0 & RSTSR.LVDF=1
No
Yes
RSTSR. PORF=1
No
Yes
Watchdog timer reset
Deep software standby reset
Voltage monitoring reset*
Power-on reset*
Pin reset
Note:
* Supported only by the H8SX/1658M Group.
Figure 4.3 Example of Reset Generation Source Determination Flow
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Section 5 Voltage Detection Circuit (LVD)
Section 5 Voltage Detection Circuit (LVD)
The voltage detection circuit (LVD) is only supported by the H8SX/1658M Group. This circuit is used to monitor Vcc. The LVD is capable of internally resetting the LSI when Vcc falls and crosses the voltage detection level. An interrupt can also be generated.
5.1
*
Features
Voltage-detection circuit Capable of detecting the power-supply voltage (Vcc) becoming less than or equal to Vdet. Capable of generating an internal reset or interrupt when a low voltage is detected.
A block diagram of the voltage detection circuit is shown in figure 5.1.
Vcc
On-chip reference voltage (for sensing Vdet)
+ -
Power-supply stabilization time generation circuit
LVDMON
LVDF LVDE LVDRI
Reset / interrupt control circuit
Voltage-monitoring reset Voltage-monitoring interrupt
[Legend] LVDE: LVDRI: LVDMON: LVDF:
LVD enable LVD reset / interrupt select LVD monitor LVD flag
Figure 5.1 Block Diagram of Voltage-Detection Circuit
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Section 5 Voltage Detection Circuit (LVD)
5.2
Register Descriptions
The registers of the voltage detection circuit are listed below. * * Voltage detection control register (LVDCR) Reset status register (RSTSR) Voltage Detection Control Register (LVDCR)
5.2.1
The LVDCR controls the voltage-detection circuit. LVDE, LVDRI, and LVDMON are initialized by a pin reset or power-on reset
Bit Bit name Initial value: R/W: 7 LVDE 0 R/W 6 LVDRI 0 R/W 5 -- 0 R/W 4 LVDMON 0 R 3 -- 0 R/W 2 -- 0 R/W 1 -- 0 R/W 0 -- 0 R/W
Bit 7
Bit Name LVDE
Initial Value 0
R/W R/W
Description LVD Enable This bit enables or disables issuing of a reset or interrupt by the voltage-detection circuit. 0: Disabled 1: Enabled
6
LVDRI
0
R/W
LVD Reset/Interrupt Select This bit selects whether an internal reset or interrupt is generated when the voltage detection circuit detects a low voltage. When modifying the LVDRI bit, ensure that low-voltage detection is in the disabled state (the LVDE bit is cleared to 0). 0: A reset is generated when a voltage is detected. 1: An interrupt is generated when a low voltage is detected.
5
--
0
R/W
Reserved This bit is always read as 0 and the write value should always be 0.
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Section 5 Voltage Detection Circuit (LVD)
Bit 4
Bit Name LVDMON
Initial Value 0
R/W R
Description LVD Monitor This bit monitors the voltage level. This bit is valid when the LVDE bit is 1 and read as 0 when the LVDE bit is 0. Writing to this bit is ineffective. 0: Vcc must fall below Vdet. 1: Vcc must rise above Vdet.
3 to 0
--
0
R/W
Reserved These bits are always read as 0 and the write value should always be 0.
5.2.2
Reset Status Register (RSTSR)
RSTSR indicates the source of an internal reset or voltage monitoring interrupt.
Bit Bit name Initial value: R/W: Note: * 7 DPSRSTF 0 R/(W)* 6 -- 0 R/W 5 -- 0 R/W 4 -- 0 R/W 3 -- 0 R/W 2 LVDF Undefined R/(W)* 1 -- Undefined R/W 0 PORF Undefined R
To clear the flag, only 0 should be written to.
Bit 7
Bit Name DPSRSTF
Initial Value 0
R/W R/W*
Description Deep Software Standby Reset Flag This bit indicates release from deep software standby mode due to the interrupt source selected by DPSIER and DPSIEGR, and generation of an internal reset. [Setting condition] Release from deep software standby mode due to an interrupt source. [Clearing condition] * * Writing 0 to the bit after reading it as1. Generation of a pin reset, power on reset, or voltage monitoring reset.
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Section 5 Voltage Detection Circuit (LVD)
Bit 6 to 3
Bit Name --
Initial Value All 0
R/W R/W
Description Reserved These bits are always read as 0 and the write value should always be 0.
2
LVDF
Undefined
R/(W)*
LVD Flag This bit indicates that the voltage detection circuit has detected a low voltage (Vcc at or below Vdet). [Setting condition] Vcc falling to or below Vdet. [Clearing condition] * After Vcc has exceeded Vdet and the specified stabilization period has elapsed, writing 0 to the bit after reading it as 1. Generation of a pin reset or power-on reset.
* 1 0 -- PORF Undefined Undefined R/W R
Reserved The write value should always be 0. Power-on Reset Flag This bit indicates that a power-on reset has been generated. [Setting condition] Generation of a power-on reset [Clearing condition] Generation of a pin reset
Note:
*
To clear the flag, only 0 should be written to.
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Section 5 Voltage Detection Circuit (LVD)
5.3
5.3.1
Voltage Detection Circuit
Voltage Monitoring Reset
Figure 5.2 shows the timing of a voltage monitoring reset by the voltage-detection circuit. When Vcc falls below Vdet in the state where the LVDE bit in LVDCR has been set to 1 and the LVDRI bit has been cleared to 0, the LVDF bit is set to 1 and the voltage-detection circuit generates a voltage monitoring reset. Next, after Vcc has risen above Vdet, release from the voltage-monitoring reset takes place after a period for stabilization (tpor) has elapsed. The period for stabilization (tpor) is a time that is generated by the voltage detection circuit in order to stabilize the Vcc and the internal circuit of the LSI. When a voltage-monitoring reset is generated, the LVDF bit is set to 1. For details, see section 29, Electrical Characteristics.
Vcc Vdet Vpor
Write 1 LVDE LVDRI Stabilization time (tPOR) Internal reset signal (Low) Write 0
Figure 5.2 Timing of the Voltage-Monitoring Reset
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Section 5 Voltage Detection Circuit (LVD)
5.3.2
Voltage Monitoring Interrupt
Figure 5.3 shows the timing of a voltage monitoring interrupt by the voltage-detection circuit. When Vcc falls below the Vdet in a state where the LVDE and LVDRI bits in LVDCR are both set to 1, the LVDF bit is set to 1 and a voltage monitoring interrupt is requested. The voltage monitoring interrupt signal is internally connected to IRQ14-B, so the IRQ14F bit in the ISR is set to 1 when the interrupt is generated. As for the IRQ14 setting, set both the ITS14 bit in PFCRB and the IRQ14E bit in the IER to 1, and the IRQ14SR and IRQ14SF bits in the ISCR to 01 (interrupt request on falling edge). Figure 5.4 shows the procedure for setting the voltage-monitoring interrupt.
Vcc Vdet Vpor
Write 1 LVDE LVDRI Stabilization time (tPOR) Voltage-monitoring signal Write 1
Set LVDF Voltage-monitoring interrupt signal (IRQ14)
Write 0 after reading as 1
Set
IRQ14F
Figure 5.3 Timing of the Voltage-Monitoring Interrupt
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Section 5 Voltage Detection Circuit (LVD)
Start program Voltage monitoring interrupt (IRQ14) disabled IER.IRQ14E = write 0
LVDCR.LVDRI = write 1
LVDCR.LVDE = write 1 Voltage detection and IRQ register settings PFCRB.ITS14 = write 1
ISCR setting (IRQ14SR = 0, IRQ14SF = 1)
If the flag has been set to 1 before the voltage-monitoring interrupt is enabled, clear it by writing 0 after having read it as 1.
ISR.IRQ14F = clear
LVDCR. LVDMON = 1 Yes
No (Vcc low)
(Vcc high)
Processing for lowered Vcc
Clear RSTSR.LVDF* Voltage-monitoring interrupt (IRQ14) enabled
IER.IRQ14E = write 1
Interrupt generation when a low voltage is detected
Processing for lowered Vcc Note: * When the LVDF cannot be cleared despite Vcc being at a higher electrical potential than Vdet (LVDMON = 1), the voltage-detection circuit is in the state of waiting for stabilization. Clear the bit again after the stabilization time (tPOR) has elapsed.
Figure 5.4 Example of the Procedure for Setting the Voltage-Monitoring Interrupt
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Section 5 Voltage Detection Circuit (LVD)
5.3.3
Release from Deep Software Standby Mode by the Voltage-Detection Circuit
If the LVDE and LVDRI bits in LVDCR and the DLVDIE bit in DPSIER have all been set to 1 during a period in deep software standby mode, the voltage-detection circuit requests release from deep software standby mode when Vcc falls to or below Vdet. This sets the DLVDIF bit in DPSIFR to 1, thus producing release from the deep software standby mode. For the deep software standby mode, see section 27, Power-Down Modes. 5.3.4 Voltage Monitor
The result of voltage detection by the voltage-detection circuit can be monitored by checking the value of the LVDMON bit in LVDCR. When the LVDMON bit has been enabled by setting the LVDE bit, 0 indicates that Vcc is at or below Vdet and 1 indicates that Vcc is above Vdet. This bit should be read while the voltage-monitoring reset has been disabled by setting the LVDRI bit to 1. Before clearing the LVDF bit in RSTSR to 0, confirm that the LVDMON bit is set to 1 (indicating that Vcc is above Vdet). When it is impossible to clear the LVDF bit despite the LVDMON bit being 1, the voltage-detection circuit is in the state of waiting for stabilization. In such cases, clear the bit again after the stabilization time (tpor) has elapsed.
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Section 6 Exception Handling
Section 6 Exception Handling
6.1 Exception Handling Types and Priority
As table 6.1 indicates, exception handling is caused by a reset, a trace, an address error, an interrupt, a trap instruction, a sleep instruction, and an illegal instruction (general illegal instruction or slot illegal instruction). Exception handling is prioritized as shown in table 6.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Exception sources, the stack structure, and operation of the CPU vary depending on the interrupt control mode. For details on the interrupt control mode, see section 7, Interrupt Controller. Table 6.1
Priority High
Exception Types and Priority
Exception Type Reset Exception Handling Start Timing Exception handling starts at the timing of level change from low to high on the RES pin, when deep software standby mode is canceled, or when the watchdog timer overflows. The CPU enters the reset state when the RES pin is low. Exception handling starts when an undefined code is executed. Exception handling starts after execution of the current instruction or exception handling, if the trace (T) bit in EXR is set to 1. After an address error has occurred, exception handling starts on completion of instruction execution. Exception handling starts after execution of the current instruction or exception handling, if an interrupt request has occurred.*2 Exception handling starts by execution of a sleep instruction (SLEEP), if the SSBY bit in SBYCR is set to 0 and the SLPIE bit in SBYCR is set to 1. Exception handling starts by execution of a trap instruction (TRAPA).
Illegal instruction Trace*1
Address error Interrupt
Sleep instruction
Trap instruction*3 Low
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests and sleep instruction exception handling requests are accepted at all times in program execution state.
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Section 6 Exception Handling
6.2
Exception Sources and Exception Handling Vector Table
Different vector table address offsets are assigned to different exception sources. The vector table addresses are calculated from the contents of the vector base register (VBR) and vector table address offset of the vector number. The start address of the exception service routine is fetched from the exception handling vector table indicated by this vector table address. Table 6.2 shows the correspondence between the exception sources and vector table address offsets. Table 6.3 shows the calculation method of exception handling vector table addresses. Table 6.2 Exception Handling Vector Table
Vector Table Address Offset*1 Exception Source Reset Reserved for system use Vector Number 0 1 2 3 Illegal instruction Trace Reserved for system use Interrupt (NMI) Trap instruction (#0) (#1) (#2) (#3) CPU address error DMA address error*3 UBC break interrupt Reserved for system use 4 5 6 7 8 9 10 11 12 13 14 15 17 18 Normal Mode*
2
Advanced, Middle*2, Maximum*2 Modes H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0044 to H'0047 H'0048 to H'004B
H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0005 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0022 to H'0023 H'0024 to H'0025
Sleep interrupt
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Section 6 Exception Handling
Vector Table Address Offset*1 Exception Source Reserved for system use Vector Number 19 23 24 63 64 65 66 67 68 69 70 71 72 73 74 75 76 79 80 255 Normal Mode*
2
Advanced, Middle*2, Maximum*2 Modes H'004C to H'004F H'005C to H'005F H'0060 to H'0063 H'00FC to H'00FF H'0100 to H'0103 H'0104 to H'0107 H'0108 to H'010B H'010C to H'010F H'0110 to H'0113 H'0114 to H'0117 H'0118 to H'011B H'011C to H'011F H'0120 to H'0123 H'0124 to H'0127 H'0128 to H'012B H'012C to H'012F H'0130 to H'0133 H'013C to H'013F H'0140 to H'0143 H'03FC to H'03FF
H'0026 to H'0027 H'002E to H'002F H'0030 to H'0031 H'007E to H'007F H'0080 to H'0081 H'0082 to H'0083 H'0084 to H'0085 H'0086 to H'0087 H'0088 to H'0089 H'008A to H'008B H'008C to H'008D H'008E to H'008F H'0090 to H'0091 H'0092 to H'0093 H'0094 to H'0095 H'0096 to H'0097 H'0098 to H'0099 H'009E to H'009F H'00A0 to H'00A1 H'01FE to H'01FF
User area (not used)
External interrupt
IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11
Reserved for system use
Internal interrupt*4
Notes: 1. 2. 3. 4.
Lower 16 bits of the address. Not available in this LSI. A DMA address error is generated by the DTC, DMAC, and EXDMAC. For details of internal interrupt vectors, see section 7.5, Interrupt Exception Handling Vector Table.
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Section 6 Exception Handling
Table 6.3
Calculation Method of Exception Handling Vector Table Address
Calculation Method of Vector Table Address Vector table address = (vector table address offset) Vector table address = VBR + (vector table address offset)
Exception Source Reset, CPU address error Other than above
[Legend] VBR: Vector base register Vector table address offset: See table 6.2.
6.3
Reset
A reset has priority over any other exception. When the RES pin goes low, all processing halts and this LSI enters the reset state. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms with the STBY pin driven high when the power is turned on. When operation is in progress, hold the RES pin low for at least 20 cycles. The chip can also be reset by the overflow that is generated in watchdog timer mode of the watchdog timer. For details, see section 27, Power-Down Modes, and section 17, Watchdog Timer (WDT). A reset initializes the internal state of the CPU and the registers of the on-chip peripheral modules. The interrupt control mode is 0 immediately after a reset. 6.3.1 Reset Exception Handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized, VBR is cleared to H'00000000, the T bit is cleared to 0 in EXR, and the I bits are set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 6.1 and 6.2 show examples of the reset sequence.
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Section 6 Exception Handling
6.3.2
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx: 32, SP). 6.3.3 On-Chip Peripheral Functions after Reset Release
After the reset state is released, MSTPCRA and MSTPCRB are initialized to H'0FFF and H'FFFF, respectively, and all modules except the EXDMAC, DTC, and DMAC enter module stop mode. Consequently, on-chip peripheral module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is canceled.
First instruction prefetch
Vector fetch
Internal operation
I
RES
Internal address bus
(1)
(3)
Internal read signal
Internal write signal Internal data bus (2)
High
(4)
(1): Reset exception handling vector address (when reset, (1) = H'000000) (2): Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)) (4) First instruction in the exception handling routine
Figure 6.1 Reset Sequence (On-chip ROM Enabled Advanced Mode)
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Section 6 Exception Handling
Vector fetch
Internal First instruction operation prefetch
*
B
*
*
RES
Address bus
(1)
(3)
(5)
RD
HWR, LWR
High
D15 to D0
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1) = H'000000, (3) = H'000002) (2)(4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2)(4)) (6) First instruction in the exception handling routine Note: * Seven program wait cycles are inserted.
Figure 6.2 Reset Sequence (16-Bit External Access in On-chip ROM Disabled Advanced Mode)
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Section 6 Exception Handling
6.4
Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. Before changing interrupt control modes, the T bit must be cleared. For details on interrupt control modes, see section 7, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is not affected by interrupt masking by CCR. Table 6.4 shows the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by clearing the T bit in EXR to 0 during the trace exception handling. However, the T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Interrupts are accepted even within the trace exception handling routine. Table 6.4 Status of CCR and EXR after Trace Exception Handling
CCR Interrupt Control Mode 0 2 I UI I2 to I0 EXR T
Trace exception handling cannot be used. 1 0
[Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value.
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Section 6 Exception Handling
6.5
6.5.1
Address Error
Address Error Source
Instruction fetch, stack operation, or data read/write shown in table 6.5 may cause an address error.
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Section 6 Exception Handling
Table 6.5
Bus Cycle and Address Error
Bus Cycle
Type Instruction fetch
Bus Master CPU
Description Fetches instructions from even addresses Fetches instructions from odd addresses
Address Error No (normal) Occurs
Fetches instructions from areas other than on-chip No (normal) 1 peripheral module space* Fetches instructions from on-chip peripheral module space*1 Occurs
Fetches instructions from external memory space Occurs in single-chip mode Fetches instructions from access prohibited area.*2 Stack operation CPU Accesses stack when the stack pointer value is even address Accesses stack when the stack pointer value is odd address. Data read/write CPU Accesses word data from even addresses Accesses word data from odd addresses Accesses external memory space in single-chip mode Accesses to access prohibited area* Data read/write DTC or DMAC
2
Occurs No (normal) Occurs No (normal) No (normal) Occurs Occurs No (normal) No (normal) Occurs Occurs No (normal) No (normal) Occurs Occurs No (normal) Occurs
Accesses word data from even addresses Accesses word data from odd addresses Accesses external memory space in single-chip mode Accesses to access prohibited area*2
Data read/write EXDMAC
Accesses word data from even addresses Accesses word data from odd addresses Accesses external memory space in single-chip mode Accesses access prohibited area*2 Accesses external memory space Accesses areas other than external memory space
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Section 6 Exception Handling
Bus Cycle Type Bus Master Description Address access space is the external memory space for single address transfer Address Error No (normal)
Single address DMAC/ transfer EXDMAC
Address access space is not the external memory Occurs space for single address transfer Notes: 1. For on-chip peripheral module space, see section 9, Bus Controller (BSC). 2. For the access prohibited area, refer to figure 3.1, Address Map (Advanced Mode) in section 3.4, Address Map.
6.5.2
Address Error Exception Handling
When an address error occurs, address error exception handling starts after the bus cycle causing the address error ends and current instruction execution completes. The address error exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the address error is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Even though an address error occurs during a transition to an address error exception handling, the address error is not accepted. This prevents an address error from occurring due to stacking for exception handling, thereby preventing infinitive stacking. If the SP contents are not a multiple of 2 when an address error exception handling occurs, the stacked values (PC, CCR, and EXR) are undefined. When an address error occurs, the following is performed to halt the DTC, DMAC, and EXDMAC. * * * * The ERR bit of DTCCR in the DTC is set to 1. The ERRF bit of DMDR_0 in the DMAC is set to 1. The ERRF bit of EDMDR_0 in the EXDMAC is set to 1. The DTE bits of DMDRs for all channels in the DMAC are cleared to 0 to forcibly terminate transfer. * The DTE bits of EDMDR for all channels in the EXDMAC are cleared to 0 to forcibly terminate transfer.
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Section 6 Exception Handling
Table 6.6 shows the state of CCR and EXR after execution of the address error exception handling. Table 6.6 Status of CCR and EXR after Address Error Exception Handling
CCR Interrupt Control Mode 0 2 I 1 1 UI T 0 EXR I2 to I0 7
[Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value.
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Section 6 Exception Handling
6.6
6.6.1
Interrupts
Interrupt Sources
Interrupt sources are NMI, UBC break interrupt, IRQ0 to IRQ11, and on-chip peripheral modules, as shown in table 6.7. Table 6.7
Type NMI UBC break interrupt IRQ0 to IRQ11 Voltage-detection circuit On-chip peripheral module
Interrupt Sources
Source NMI pin (external input) User break controller (UBC) Pins IRQ0 to IRQ11 (external input) Voltage-detection circuit (LVD)* DMA controller (DMAC) EXDMA controller (EXDMAC) Watchdog timer (WDT) A/D converter 16-bit timer pulse unit (TPU) 8-bit timer (TMR) Serial communications interface (SCI) I C bus interface 2 (IIC2) USB function module (USB)
2
Number of Sources 1 1 12 1 8 8 1 2 52 16 24 2 5
Note:
*
Supported only by the H8SX/1658M Group.
Different vector numbers and vector table offsets are assigned to different interrupt sources. For vector number and vector table offset, refer to table 7.2, Interrupt Sources, Vector Address Offsets, and Interrupt Priority in section 7, Interrupt Controller. 6.6.2 Interrupt Exception Handling
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI or sleep interrupt to eight priority/mask levels to enable multiple-interrupt control. The source to start interrupt exception handling and the vector address differ depending on the product. For details, refer to section 7, Interrupt Controller. The interrupt exception handling is as follows:
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Section 6 Exception Handling
1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the interrupt source is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address.
6.7
Instruction Exception Handling
There are three instructions that cause exception handling: trap instruction, sleep instruction, and illegal instruction. 6.7.1 Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The trap instruction exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the vector number specified in the TRAPA instruction is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. A start address is read from the vector table corresponding to a vector number from 0 to 3, as specified in the instruction code.
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Section 6 Exception Handling
Table 6.8 shows the state of CCR and EXR after execution of trap instruction exception handling. Table 6.8 Status of CCR and EXR after Trap Instruction Exception Handling
CCR Interrupt Control Mode 0 2 I 1 1 UI T 0 EXR I2 to I0
[Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value.
6.7.2
Sleep Instruction Exception Handling
The sleep instruction exception handling starts when a sleep instruction is executed with the SSBY bit in SBYCR set to 0 and the SLPIE bit in SBYCR set to 1. The sleep instruction exception handling can always be executed in the program execution state. In the exception handling, the CPU operates as follows. 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the vector number specified in the SLEEP instruction is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address. Bus masters other than the CPU may gain the bus mastership after a sleep instruction has been executed. In such cases the sleep instruction will be started when the transactions of a bus master other than the CPU has been completed and the CPU has gained the bus mastership. Table 6.9 shows the state of CCR and EXR after execution of sleep instruction exception handling. For the detail, see section 27.10, Sleep Instruction Exception Handling.
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Section 6 Exception Handling
Table 6.9
Status of CCR and EXR after Sleep Instruction Exception Handling
CCR EXR T 0 I2 to I0 7
Interrupt Control Mode 0 2
I 1 1
UI
[Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value.
6.7.3
Exception Handling by Illegal Instruction
The illegal instructions are general illegal instructions and slot illegal instructions. The exception handling by the general illegal instruction starts when an undefined code is executed. The exception handling by the slot illegal instruction starts when a particular instruction (e.g. its code length is two words or more, or it changes the PC contents) at a delay slot (immediately after a delayed branch instruction) is executed. The exception handling by the general illegal instruction and slot illegal instruction is always executable in the program execution state. The exception handling is as follows: 1. The contents of PC, CCR, and EXR are saved in the stack. 2. The interrupt mask bit is updated and the T bit is cleared to 0. 3. An exception handling vector table address corresponding to the occurred exception is generated, the start address of the exception service routine is loaded from the vector table to PC, and program execution starts from that address.
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Section 6 Exception Handling
Table 6.10 shows the state of CCR and EXR after execution of illegal instruction exception handling. Table 6.10 Status of CCR and EXR after Illegal Instruction Exception Handling
CCR Interrupt Control Mode 0 2 I 1 1 UI T 0 EXR I2 to I0
[Legend] 1: Set to 1 0: Cleared to 0 : Retains the previous value.
6.8
Stack Status after Exception Handling
Figure 6.3 shows the stack after completion of exception handling.
Advanced mode
SP
EXR Reserved*
SP
CCR PC (24 bits)
CCR PC (24 bits)
Interrupt control mode 0
Interrupt control mode 2
Note: * Ignored on return.
Figure 6.3 Stack Status after Exception Handling
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Section 6 Exception Handling
6.9
Usage Note
When performing stack-manipulating access, this LSI assumes that the lowest address bit is 0. The stack should always be accessed by a word transfer instruction or a longword transfer instruction, and the value of the stack pointer (SP: ER7) should always be kept even. Use the following instructions to save registers:
PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn)
Performing stack manipulation while SP is set to an odd value leads to an address error. Figure 6.4 shows an example of operation when the SP value is odd.
Address
CCR
SP
PC
SP
R1L
H'FFFEFA H'FFFEFB
PC
H'FFFEFC H'FFFEFD H'FFFEFE
SP
H'FFFEFF
TRAPA instruction executed SP set to H'FFFEFF
MOV.B R1L, @-ER7 executed Contents of CCR lost
Data saved above SP
(Address error occurred)
[Legend]
CCR : PC : R1L : SP :
Condition code register Program counter General register R1L Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Figure 6.4 Operation when SP Value Is Odd
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Section 6 Exception Handling
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Section 7 Interrupt Controller
Section 7 Interrupt Controller
7.1 Features
* Two interrupt control modes Any of two interrupt control modes can be set by means of bits INTM1 and INTM0 in the interrupt control register (INTCR). * Priority can be assigned by the interrupt priority register (IPR) IPR provides for setting interrupt priory. Eight levels can be set for each module for all interrupts except for the interrupt requests listed below. The following seven interrupt requests are given priority of 8, therefore they are accepted at all times. NMI Illegal instructions Trace Trap instructions CPU address error DMA address error (occurred in the DTC, DMAC, and EXDMAC) Sleep instruction * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Thirteen external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge detection can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ11 to IRQ0. * DTC and DMAC control DTC and DMAC can be activated by means of interrupts. * CPU priority control function The priority levels can be assigned to the CPU, DTC, and DMAC, EXDMAC. The priority level of the CPU can be automatically assigned on an exception generation. Priority can be given to the CPU interrupt exception handling over that of the DTC, DMAC, and EXDMAC transfer.
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Section 7 Interrupt Controller
A block diagram of the interrupt controller is shown in figure 7.1.
INTM1, INTM0 INTCR NMIEG IPR I I2 to I0 NMI input IRQ11 to IRQ0 input LVD* IRQ input unit IRQ14 input ISCR IER SSIER DMAC activation permission CPU interrupt request CPU vector Priority determination
CPU
CCR EXR
NMI input unit ISR
DMAC DMAC priority control DMDR
Internal interrupt sources WOVI to RESUME
Source selector
CPU priority DTC activation request DTCER DTCCR CPUPCR DTC priority Interrupt controller [Legend] INTCR: Interrupt control register CPUPCR: CPU priority control register IRQ sense control register ISCR: IRQ enable register IER: IRQ status register ISR: SSIER: IPR: DTCER: DTCCR: Software standby release IRQ enable register Interrupt priority register DTC enable register DTC control register DTC priority control DTC vector Activation request clear signal DTC
Note: * Supported only by the H8SX/1658M Group.
Figure 7.1 Block Diagram of Interrupt Controller
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Section 7 Interrupt Controller
7.2
Input/Output Pins
Table 7.1 shows the pin configuration of the interrupt controller. Table 7.1
Name NMI IRQ11 to IRQ0
Pin Configuration
I/O Input Input Function Nonmaskable External Interrupt Rising or falling edge can be selected. Maskable External Interrupts Rising, falling, or both edges, or level sensing, can be independently selected.
7.3
Register Descriptions
The interrupt controller has the following registers. * Interrupt control register (INTCR) * CPU priority control register (CPUPCR) * Interrupt priority registers A to C, E to O, Q, and R (IPRA to IPRC, IPRE to IPRO, IPRQ, and IPRR) * IRQ enable register (IER) * IRQ sense control registers H and L (ISCRH, ISCRL) * IRQ status register (ISR) * Software standby release IRQ enable register (SSIER)
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Section 7 Interrupt Controller
7.3.1
Interrupt Control Register (INTCR)
INTCR selects the interrupt control mode, and the edge to detect NMI.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 0 R 1 0 R 0 0 R
Bit 7 6 5 4
Bit Name INTM1 INTM0
Initial Value 0 0 0 0
R/W R R R/W R/W
Description Reserved These are read-only bits and cannot be modified. Interrupt Control Select Mode 1 and 0 These bits select either of two interrupt control modes for the interrupt controller. 00: Interrupt control mode 0 Interrupts are controlled by I bit in CCR. 01: Setting prohibited. 10: Interrupt control mode 2 Interrupts are controlled by bits I2 to I0 in EXR, and IPR. 11: Setting prohibited.
3
NMIEG
0
R/W
NMI Edge Select Selects the input edge for the NMI pin. 0: Interrupt request generated at falling edge of NMI input 1: Interrupt request generated at rising edge of NMI input
2 to 0
All 0
R
Reserved These are read-only bits and cannot be modified.
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Section 7 Interrupt Controller
7.3.2
CPU Priority Control Register (CPUPCR)
CPUPCR sets whether or not the CPU has priority over the DTC, DMAC, and EXDMAC. The interrupt exception handling by the CPU can be given priority over that of the DTC, DMAC, and EXDMAC transfer. The priority level of the DTC is set by bits DTCP2 to DTCP0 in CPUPCR. The priority level of the DMAC and EXDMAC are set by the DMAC and EXDMAC control registers for each channel.
Bit Bit Name Initial Value R/W 7 CPUPCE 0 R/W 6 DTCP2 0 R/W 5 DTCP1 0 R/W 4 DTCP0 0 R/W 3 IPSETE 0 R/W 2 CPUP2 0 R/(W)* 1 CPUP1 0 R/(W)* 0 CPUP0 0 R/(W)*
Note: * When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified.
Bit 7
Bit Name CPUPCE
Initial Value 0
R/W R/W
Description CPU Priority Control Enable Controls the CPU priority control function. Setting this bit to 1 enables the CPU priority control over the DTC, DMAC, and EXDMAC. 0: CPU always has the lowest priority 1: CPU priority control enabled
6 5 4
DTCP2 DTCP1 DTCP0
0 0 0
R/W R/W R/W
DTC Priority Level 2 to 0 These bits set the DTC priority level. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest)
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Section 7 Interrupt Controller
Bit 3
Bit Name IPSETE
Initial Value 0
R/W R/W
Description Interrupt Priority Set Enable Controls the function which automatically assigns the interrupt priority level of the CPU. Setting this bit to 1 automatically sets bits CPUP2 to CPUP0 by the CPU interrupt mask bit (I bit in CCR or bits I2 to I0 in EXR). 0: Bits CPUP2 to CPUP0 are not updated automatically 1: The interrupt mask bit value is reflected in bits CPUP2 to CPUP0
2 1 0
CPUP2 CPUP1 CPUP0
0 0 0
R/(W)* CPU Priority Level 2 to 0 R/(W)* These bits set the CPU priority level. When the CPUPCE R/(W)* is set to 1, the CPU priority control function over the DTC, DMAC, and EXDMAC becomes valid and the priority of CPU processing is assigned in accordance with the settings of bits CPUP2 to CPUP0. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest)
Note:
*
When the IPSETE bit is set to 1, the CPU priority is automatically updated, so these bits cannot be modified.
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Section 7 Interrupt Controller
7.3.3
Interrupt Priority Registers A to C, E to O, Q, and R (IPRA to IPRC, IPRE to IPRO, IPRQ, and IPRR)
IPR sets priory (levels 7 to 0) for interrupts other than NMI. Setting a value in the range from B'000 to B'111 in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 assigns a priority level to the corresponding interrupt. For the correspondence between the interrupt sources and the IPR settings, see Table 7.2.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 0 R 7 0 R 14 IPR14 1 R/W 6 IPR6 1 R/W 13 IPR13 1 R/W 5 IPR5 1 R/W 12 IPR12 1 R/W 4 IPR4 1 R/W 11 0 R 3 0 R 10 IPR10 1 R/W 2 IPR2 1 R/W 9 IPR9 1 R/W 1 IPR1 1 R/W 8 IPR8 1 R/W 0 IPR0 1 R/W
Bit 15 14 13 12
Bit Name IPR14 IPR13 IPR12
Initial Value 0 1 1 1
R/W R R/W R/W R/W
Description Reserved This is a read-only bit and cannot be modified. Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest)
11
0
R
Reserved This is a read-only bit and cannot be modified.
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Section 7 Interrupt Controller
Bit 10 9 8
Bit Name IPR10 IPR9 IPR8
Initial Value 1 1 1
R/W R/W R/W R/W
Description Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest)
7 6 5 4
IPR6 IPR5 IPR4
0 1 1 1
R R/W R/W R/W
Reserved This is a read-only bit and cannot be modified. Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest)
3 2 1 0
IPR2 IPR1 IPR0
0 1 1 1
R R/W R/W R/W
Reserved This is a read-only bit and cannot be modified. Sets the priority level of the corresponding interrupt source. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest)
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Section 7 Interrupt Controller
7.3.4
IRQ Enable Register (IER)
IER enables interrupt requests IRQ14, and IRQ11 to IRQ0.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 0 R/W 7 IRQ7E 0 R/W 14 IRQ14E* 0 R/W 6 IRQ6E 0 R/W 13 0 R/W 5 IRQ5E 0 R/W 12 0 R/W 4 IRQ4E 0 R/W 11 IRQ11E 0 R/W 3 IRQ3E 0 R/W 10 IRQ10E 0 R/W 2 IRQ2E 0 R/W 9 IRQ9E 0 R/W 1 IRQ1E 0 R/W 8 IRQ8E 0 R/W 0 IRQ0E 0 R/W
Note: * Supported only by the H8SX/1658M Group.
Bit 15
Bit Name
Initial Value All 0
R/W R/W
Description Reserved These bits are always read as 0. The write value should always be 0.
14
IRQ14E*
0
R/W
IRQ14 Enable The IRQ14 interrupt request is enabled when this bit is 1. The IRQ14 is internally connected to the voltagedetection interrupt.
13 to 12
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
11 10 9 8 7
IRQ11E IRQ10E IRQ9E IRQ8E IRQ7E
0 0 0 0 0
R/W R/W R/W R/W R/W
IRQ11 Enable The IRQ10 interrupt request is enabled when this bit is 1. IRQ10 Enable The IRQ11 interrupt request is enabled when this bit is 1. IRQ9 Enable The IRQ9 interrupt request is enabled when this bit is 1. IRQ8 Enable The IRQ8 interrupt request is enabled when this bit is 1. IRQ7 Enable The IRQ7 interrupt request is enabled when this bit is 1.
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Section 7 Interrupt Controller
Bit 6 5 4 3 2 1 0 Note: *
Bit Name IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
Initial Value 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Description IRQ6 Enable The IRQ6 interrupt request is enabled when this bit is 1. IRQ5 Enable The IRQ5 interrupt request is enabled when this bit is 1. IRQ4 Enable The IRQ4 interrupt request is enabled when this bit is 1. IRQ3 Enable The IRQ3 interrupt request is enabled when this bit is 1. IRQ2 Enable The IRQ2 interrupt request is enabled when this bit is 1. IRQ1 Enable The IRQ1 interrupt request is enabled when this bit is 1. IRQ0 Enable The IRQ0 interrupt request is enabled when this bit is 1.
Supported only by the H8SX/1658M Group.
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Section 7 Interrupt Controller
7.3.5
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
ISCR selects the source that generates an interrupt request from IRQ14 and IRQ11 to IRQ0 input. Upon changing the setting of ISCR, IRQnF (n = 0 to 11, 14) in ISR is often set to 1 accidentally through an internal operation. In this case, an interrupt exception handling is executed if an IRQn interrupt request is enabled. In order to prevent such an accidental interrupt from occurring, the setting of ISCR should be changed while the IRQn interrupt is disabled, and then the IRQnF in ISR should be cleared to 0. * ISCRH
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 0 R/W 7 IRQ11SR 0 R/W 14 0 R/W 6 IRQ11SF 0 R/W 13 IRQ14SR* 0 R/W 5 IRQ10SR 0 R/W 12 IRQ14SF* 0 R/W 4 IRQ10SF 0 R/W 11 0 R/W 3 IRQ9SR 0 R/W 10 0 R/W 2 IRQ9SF 0 R/W 9 0 R/W 1 IRQ8SR 0 R/W 8 0 R/W 0 IRQ8SF 0 R/W
* ISCRL
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 IRQ7SR 0 R/W 7 IRQ3SR 0 R/W 14 IRQ7SF 0 R/W 6 IRQ3SF 0 R/W 13 IRQ6SR 0 R/W 5 IRQ2SR 0 R/W 12 IRQ6SF 0 R/W 4 IRQ2SF 0 R/W 11 IRQ5SR 0 R/W 3 IRQ1SR 0 R/W 10 IRQ5SF 0 R/W 2 IRQ1SF 0 R/W 9 IRQ4SR 0 R/W 1 IRQ0SR 0 R/W 8 IRQ4SF 0 R/W 0 IRQ0SF 0 R/W
Note: * Supported only by the H8SX/1658M Group.
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Section 7 Interrupt Controller
* ISCRH
Bit 15 to 14 Bit Name Initial Value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 13 12 IRQ14SR* 0 IRQ14SF* 0 R/W R/W IRQ14 Sense Control Rise IRQ14 Sense Control Fall IRQ14 is used as the LVD voltage-monitoring interrupt*. When used as IRQ14, set the interrupt request at falling edge. 00: Initial value 01: Interrupt request generated at falling edge of IRQ14 10: Setting prohibited 11: Setting prohibited 11 to 8 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 7 6 IRQ11SR IRQ11SF 0 0 R/W R/W IRQ11 Sense Control Rise IRQ11 Sense Control Fall 00: Interrupt request generated by low level of IRQ11 01: Interrupt request generated at falling edge of IRQ11 10: Interrupt request generated at rising edge of IRQ11 11: Interrupt request generated at both falling and rising edges of IRQ11 5 4 IRQ10SR IRQ10SF 0 0 R/W R/W IRQ10 Sense Control Rise IRQ10 Sense Control Fall 00: Interrupt request generated by low level of IRQ10 01: Interrupt request generated at falling edge of IRQ10 10: Interrupt request generated at rising edge of IRQ10 11: Interrupt request generated at both falling and rising edges of IRQ10
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Section 7 Interrupt Controller
Bit 3 2
Bit Name IRQ9SR IRQ9SF
Initial Value 0 0
R/W R/W R/W
Description IRQ9 Sense Control Rise IRQ9 Sense Control Fall 00: Interrupt request generated by low level of IRQ9 01: Interrupt request generated at falling edge of IRQ9 10: Interrupt request generated at rising edge of IRQ9 11: Interrupt request generated at both falling and rising edges of IRQ9
1 0
IRQ8SR IRQ8SF
0 0
R/W R/W
IRQ8 Sense Control Rise IRQ8 Sense Control Fall 00: Interrupt request generated by low level of IRQ8 01: Interrupt request generated at falling edge of IRQ8 10: Interrupt request generated at rising edge of IRQ8 11: Interrupt request generated at both falling and rising edges of IRQ8
Note:
Supported only by the H8SX/1658M Group.
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Section 7 Interrupt Controller
* ISCRL
Bit 15 14 Bit Name IRQ7SR IRQ7SF Initial Value 0 0 R/W R/W R/W Description IRQ7 Sense Control Rise IRQ7 Sense Control Fall 00: Interrupt request generated by low level of IRQ7 01: Interrupt request generated at falling edge of IRQ7 10: Interrupt request generated at rising edge of IRQ7 11: Interrupt request generated at both falling and rising edges of IRQ7 13 12 IRQ6SR IRQ6SF 0 0 R/W R/W IRQ6 Sense Control Rise IRQ6 Sense Control Fall 00: Interrupt request generated by low level of IRQ6 01: Interrupt request generated at falling edge of IRQ6 10: Interrupt request generated at rising edge of IRQ6 11: Interrupt request generated at both falling and rising edges of IRQ6 11 10 IRQ5SR IRQ5SF 0 0 R/W R/W IRQ5 Sense Control Rise IRQ5 Sense Control Fall 00: Interrupt request generated by low level of IRQ5 01: Interrupt request generated at falling edge of IRQ5 10: Interrupt request generated at rising edge of IRQ5 11: Interrupt request generated at both falling and rising edges of IRQ5 9 8 IRQ4SR IRQ4SF 0 0 R/W R/W IRQ4 Sense Control Rise IRQ4 Sense Control Fall 00: Interrupt request generated by low level of IRQ4 01: Interrupt request generated at falling edge of IRQ4 10: Interrupt request generated at rising edge of IRQ4 11: Interrupt request generated at both falling and rising edges of IRQ4 7 6 IRQ3SR IRQ3SF 0 0 R/W R/W IRQ3 Sense Control Rise IRQ3 Sense Control Fall 00: Interrupt request generated by low level of IRQ3 01: Interrupt request generated at falling edge of IRQ3 10: Interrupt request generated at rising edge of IRQ3 11: Interrupt request generated at both falling and rising edges of IRQ3
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Section 7 Interrupt Controller
Bit 5 4
Bit Name IRQ2SR IRQ2SF
Initial Value 0 0
R/W R/W R/W
Description IRQ2 Sense Control Rise IRQ2 Sense Control Fall 00: Interrupt request generated by low level of IRQ2 01: Interrupt request generated at falling edge of IRQ2 10: Interrupt request generated at rising edge of IRQ2 11: Interrupt request generated at both falling and rising edges of IRQ2
3 2
IRQ1SR IRQ1SF
0 0
R/W R/W
IRQ1 Sense Control Rise IRQ1 Sense Control Fall 00: Interrupt request generated by low level of IRQ1 01: Interrupt request generated at falling edge of IRQ1 10: Interrupt request generated at rising edge of IRQ1 11: Interrupt request generated at both falling and rising edges of IRQ1
1 0
IRQ0SR IRQ0SF
0 0
R/W R/W
IRQ0 Sense Control Rise IRQ0 Sense Control Fall 00: Interrupt request generated by low level of IRQ0 01: Interrupt request generated at falling edge of IRQ0 10: Interrupt request generated at rising edge of IRQ0 11: Interrupt request generated at both falling and rising edges of IRQ0
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Section 7 Interrupt Controller
7.3.6
IRQ Status Register (ISR)
ISR is an IRQ14 and IRQ11 to IRQ0 interrupt request register.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: 15 0 R/(W)* 7 IRQ7F 0 R/(W)* 14 IRQ14F*2 0 R/(W)* 6 IRQ6F 0 R/(W)* 13 0 R/(W)* 5 IRQ5F 0 R/(W)* 12 0 R/(W)* 4 IRQ4F 0 R/(W)* 11 IRQ11F 0 R/(W)* 3 IRQ3F 0 R/(W)* 10 IRQ10F 0 R/(W)* 2 IRQ2F 0 R/(W)* 9 IRQ9F 0 R/(W)* 1 IRQ1F 0 R/(W)* 8 IRQ8F 0 R/(W)* 0 IRQ0F 0 R/(W)*
1. Only 0 can be written, to clear the flag. The bit manipulation instructions or memory operation instructions should be used to clear the flag. 2.. Supported only by the H8SX/1658M Group.
Bit 15
Bit Name
Initial Value All 0
R/W R/(W)*
1
Description Reserved These bits are always read as 0. The write value should always be 0.
14
IRQ14F*2
0
R/(W)*1
[Setting condition] * * When the interrupt selected by ISCR occurs Writing 0 after reading IRQ14F = 1 [Clearing conditions] When IRQ14 interrupt exception handling is executed while falling edge sensing is selected.
13, 12
All 0
R/(W)*1
Reserved These bits are always read as 0. The write value should always be 0.
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Section 7 Interrupt Controller
Bit 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name IRQ11F IRQ10F IRQ9F IRQ8F IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)*
1 1 1 1 1 1 1 1 1 1 1 1
Description [Setting condition] * * * When the interrupt selected by ISCR occurs Writing 0 after reading IRQnF = 1 When interrupt exception handling is executed while low-level sensing is selected and IRQn input is high (n = 11 to 0). When IRQn interrupt exception handling is executed while falling-, rising-, or both-edge sensing is selected. When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0. [Clearing conditions]
*
*
Notes: 1. Only 0 can be written, to clear the flag. 2. Supported only by the H8SX/1658M Group.
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Section 7 Interrupt Controller
7.3.7
Software Standby Release IRQ Enable Register (SSIER)
SSIER selects the IRQ interrupt used to leave software standby mode. The IRQ interrupt used to leave software standby mode should not be set as the DTC activation source.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 0 R/W 7 SSI7 0 R/W 14 0 R/W 6 SSI6 0 R/W 13 0 R/W 5 SSI5 0 R/W 12 0 R/W 4 SSI4 0 R/W 11 SSI11 0 R/W 3 SSI3 0 R/W 10 SSI10 0 R/W 2 SSI2 0 R/W 9 SSI9 0 R/W 1 SSI1 0 R/W 8 SSI8 0 R/W 0 SSI0 0 R/W
Bit 15 to 12
Bit Name
Initial Value All 0
R/W R/W
Description Reserved These bits are always read as 0. The write value should always be 0.
11 10 9 8 7 6 5 4 3 2 1 0
SSI11 SSI10 SSI9 SSI8 SSI7 SSI6 SSI5 SSI4 SSI3 SSI2 SSI1 SSI0
0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Software Standby Release IRQ Setting These bits select the IRQn interrupt used to leave software standby mode (n = 11 to 0). 0: An IRQn request is not sampled in software standby mode 1: When an IRQn request occurs in software standby mode, this LSI leaves software standby mode after the oscillation settling time has elapsed
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Section 7 Interrupt Controller
7.4
7.4.1
Interrupt Sources
External Interrupts
There are thirteen external interrupts: NMI and IRQ11 to IRQ0. These interrupts can be used to leave software standby mode. (1) NMI Interrupts
Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is always accepted by the CPU regardless of the interrupt control mode or the settings of the CPU interrupt mask bits. The NMIEG bit in INTCR selects whether an interrupt is requested at the rising or falling edge on the NMI pin. When an NMI interrupt is generated, the interrupt controller determines that an error has occurred, and performs the following procedure. * * * * Sets the ERR bit of DTCCR in the DTC to 1. Sets the ERRF bit of DMDR_0 in DMAC to 1. Sets the ERRF bit of EDMDR_0 in the EXDMAC to 1 Clears the DTE bits of DMDRs for all channels in the DMAC to 0 to forcibly terminate transfer * Clears the DTE bits of EDMDRs for all channels in the EXDMAC to 0 to forcibly terminate transfer (2) IRQn Interrupts
An IRQn interrupt is requested by a signal input on pins IRQ11 to IRQ0. IRQn (n = 11 to 0) have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, on pins IRQn. * Enabling or disabling of interrupt requests IRQn can be selected by IER. * The interrupt priority can be set by IPR. * The status of interrupt requests IRQn is indicated in ISR. ISR flags can be cleared to 0 by software. The bit manipulation instructions and memory operation instructions should be used to clear the flag.
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Section 7 Interrupt Controller
Detection of IRQn interrupts is enabled through the P1ICR, P2ICR, and P5ICR register settings, and does not change regardless of the output setting. However, when a pin is used as an external interrupt input pin, the pin must not be used as an I/O pin for another function by clearing the corresponding DDR bit to 0. A block diagram of interrupts IRQn is shown in figure 7.2.
IRQnE
Corresponding bit in ICR
IRQnSF, IRQnSR IRQnF
Input buffer IRQn input
Edge/level detection circuit
IRQn interrupt request S R Q
[Legend] n = 11 to 0
Clear signal
Figure 7.2 Block Diagram of Interrupts IRQn When the IRQ sensing control in ISCR is set to a low level of signal IRQn, the level of IRQn should be held low until an interrupt handling starts. Then set the corresponding input signal IRQn to high in the interrupt handling routine and clear the IRQnF to 0. Interrupts may not be executed when the corresponding input signal IRQn is set to high before the interrupt handling begins. 7.4.2 Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features: * For each on-chip peripheral module there are flags that indicate the interrupt request status, and enable bits that enable or disable these interrupts. They can be controlled independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt controller. * The interrupt priority can be set by means of IPR. * The DTC and DMAC can be activated by a TPU, SCI, or other interrupt request. * The priority levels of DTC and DMAC activation can be controlled by the DTC and DMAC priority control functions.
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Section 7 Interrupt Controller
7.5
Interrupt Exception Handling Vector Table
Table 7.2 lists interrupt exception handling sources, vector address offsets, and interrupt priority. In the default priority order, a lower vector number corresponds to a higher priority. When interrupt control mode 2 is set, priority levels can be changed by setting the IPR contents. The priority for interrupt sources allocated to the same level in IPR follows the default priority, that is, they are fixed. Table 7.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority
Vector Address Offset*
1
Advanced Mode, Vector Classification External pin UBC Interrupt Source NMI UBC break interrupt External pin IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 Reserved for system use 64 65 66 67 68 69 70 71 72 73 74 75 76 77 H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 IPRD6 to IPRD4 Low IPRA14 to IPRA12 IPRA10 to IPRA8 IPRA6 to IPRA4 IPRA2 to IPRA0 IPRB14 to IPRB12 IPRB10 to IPRB8 IPRB6 to IPRB4 IPRB2 to IPRB0 IPRC14 to IPRC12 IPRC10 to IPRC8 IPRC6 to IPRC4 IPRC2 to IPRC0 O O O O O O O O O O O O Number 7 14 Middle Mode, Maximum Mode H'001C H'0038 IPR Priority High DTC Activation DMAC Activation
LVD*
2
Voltage78 monitoring interrupt (IRQ14)
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Section 7 Interrupt Controller
Vector Address Offset*
1
Advanced Mode, Vector Classification Interrupt Source Reserved for system use WDT WOVI Reserved for system use A/D_0 ADI0 Reserved for system use TPU_0 TGI0A TGI0B TGI0C TGI0D TCI0V TPU_1 TGI1A TGI1B TCI1V TCI1U TPU_2 TGI2A TGI2B TCI2V TCI2U TPU_3 TGI3A TGI3B TGI3C TGI3D TCI3V TPU_4 TGI4A TGI4B TCI4V TCI4U 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 H'0160 H'0164 H'0168 H'016C H'0170 H'0174 H'0178 H'017C H'0180 H'0184 H'0188 H'018C H'0190 H'0194 H'0198 H'019C H'01A0 H'01A4 H'01A8 H'01AC H'01B0 H'01B4 Low IPRG6 to IPRG4 IPRG10 to IPRG8 IPRG14 to IPRG12 IPRF2 to IPRF0 IPRF6 to IPRF4 O O O O O O O O O O O O O O O O O O O 86 87 H'0158 H'015C IPRF10 to IPRF8 O O Number 79 80 81 82 Middle Mode, Maximum Mode H'013C H'0140 H'0144 H'0148 IPRE10 to IPRE8 IPR Priority High DTC Activation DMAC Activation
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Section 7 Interrupt Controller
Vector Address Offset*
1
Advanced Mode, Vector Classification TPU_5 Interrupt Source TGI5A TGI5B TCI5V TCI5U Reserved for system use TMR_0 CMI0A CMI0B OV0I TMR_1 CMI1A CMI1B OV1I TMR_2 CMI2A CMI2B OV2I TMR_3 CMI3A CMI3B OV3I DMAC DMTEND0 DMTEND1 DMTEND2 DMTEND3 EXDMAC EXDMTEND0 EXDMTEND1 EXDMTEND2 EXDMTEND3 DMAC DMEEND0 DMEEND1 DMEEND2 DMEEND3 Number 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 Middle Mode, Maximum Mode H'01B8 H'01BC H'01C0 H'01C4 H'01C8 H'01CC H'01D0 H'01D4 H'01D8 H'01DC H'01E0 H'01E4 H'01E8 H'01EC H'01F0 H'01F4 H'01F8 H'01FC H'0200 H'0204 H'0208 H'020C H'0210 H'0214 H'0218 H'021C H'0220 H'0224 H'0228 H'022C Low IPRI14 to IPRI12 IPRI10 to IPRI8 IPRI6 to IPRI4 IPRI2 to IPRI0 IPRJ14 to IPRJ12 IPRJ10 to IPRJ8 IPRJ6 to IPRJ4 IPRJ2 to IPRJ0 IPRK14 to IPRK12 IPRH2 to IPRH0 IPRH6 to IPRH4 IPRH10 to IPRH8 IPRH14 to IPRH12 IPR IPRG2 to IPRG0 Priority High DTC Activation O O O O O O O O O O O O O O O O O O O O O O DMAC Activation O
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Section 7 Interrupt Controller
Vector Address Offset*
1
Advance Mode, Vector Classification EXDMAC Interrupt Source EXDMEEND0 EXDMEEND1 EXDMEEND2 EXDMEEND3 SCI_0 ERI0 RXI0 TXI0 TEI0 SCI_1 ERI1 RXI1 TXI1 TEI1 SCI_2 ERI2 RXI2 TXI2 TEI2 Reserved for system use Number 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 SCI_4 ERI4 RXI4 TXI4 TEI4 TPU_6 TGI6A TGI6B TGI6C TGI6D TGI6V 160 161 162 163 164 165 166 167 168 Middle Mode, Maximum Mode H'0230 H'0234 H'0238 H'023C H'0240 H'0244 H'0248 H'024C H'0250 H'0254 H'0258 H'025C H'0260 H'0264 H'0268 H'026C H'0270 H'0274 H'0278 H'027C H'0280 H'0284 H'0288 H'028C H'0290 H'0294 H'0298 H'029C H'02A0 IPRM14 to IPRM12 Low IPRL2 to IPRL0 IPRL6 to IPRL4 IPRL14 to IPRL12 IPRK2 to IPRK0 IPRK6 to IPRK4 IPR IPRK10 to IPRK8 Priority High DTC Activation O O O O O O O O O O O O O O O O DMAC Activation O O O O O O O O O
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Section 7 Interrupt Controller
Vector Address Offset*
1
Advance Mode, Vector Classification TPU_7 Interrupt Source TGI7A TGI7B TGI7V TCI7U TPU_8 TGI8A TGI8B TCI8V TCI8U TPU_9 TGI9A TGI9B TGI9C TGI9D TCI9V TPU_10 TGI10A TGI10B Reserved for system use Reserved for system use TCI10V TCI10U TPU_11 TGI11A TGI11B TCI11V TCI11U Reserved for system use 186 187 188 189 190 191 192 | 215 H'02E8 H'02EC H'02F0 H'02F4 H'02F8 H'02FC H'0300 | H'035C Low IPRO6 to IPRO4 IPRO10 to IPRO8 IPRO14 to IPRO12 O O O | O | 185 H'02E4 Number 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 Middle Mode, Maximum Mode H'02A4 H'02A8 H'02AC H'02B0 H'02B4 H'02B8 H'02BC H'02C0 H'02C4 H'02C8 H'02CC H'02D0 H'02D4 H'02D8 H'02DC H'02E0 IPRN6 to IPRN4 IPRN2 to IPRN0 IPRN10 to IPRN8 IPRN14 to IPRN12 IRPM2 to IRPM0 IRPM6 to IRPM4 IPR IRPM10 to IRPM8 Priority High DTC Activation O O O O O O O O O O DMAC Activation O O O O
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Section 7 Interrupt Controller
Vector Address Offset*
1
Advanced Mode, Vector Classification IIC2_0 Interrupt Source IICI0 Reserved for system use IIC2_1 IICI1 Reserved for system use SCI_5 RXI5 TXI5 ERI5 TEI5 SCI_6 RXI6 TXI6 ERI6 TEI6 TMR_4 TMR_5 TMR_6 TMR_7 USB CMIA4 or CMIB4 CMIA5 or CMIB5 CMIA6 or CMIB6 CMIA7 or CMIB7 USBINTN0 USBINTN1 USBINTN2 USBINTN3 -- Reserved for system use A/D_1 USB -- ADI1 resume Reserved for system use 237 238 239 | 255 H'03B4 H'03B8 H'03BC | H'03FC Low -- -- -- -- | -- O -- -- | -- 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 H'0370 H'0374 H'0378 H'037C H'0380 H'0384 H'0388 H'038C H'0390 H'0394 H'0398 H'039C H'03A0 H'03A4 H'03A8 H'03AC H'03B0 IPRR2 to IPRR0 IPRR6 to IPRR4 IPRR10 to IPRR8 IPRR14 to IPRR12 IPRQ2 to IPRQ0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- O O -- -- O O -- -- -- -- -- -- O O -- -- -- 218 219 H'0368 H'036C -- -- -- -- Number 216 217 Middle Mode, Maximum Mode H'0360 H'0364 IPR IPRQ6 to IPRQ4 Priority High DTC Activation -- -- DMAC Activation -- --
Notes: 1. Lower 16 bits of the start address in advanced, middle, and maximum modes. 2. Supported only by the H8SX/1658M Group.
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Section 7 Interrupt Controller
7.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two interrupt control modes: interrupt control mode 0 and interrupt control mode 2. Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is selected by INTCR. Table 7.3 shows the differences between interrupt control mode 0 and interrupt control mode 2. Table 7.3
Interrupt Control Mode 0
Interrupt Control Modes
Priority Setting Register Default Interrupt Mask Bit I
Description The priority levels of the interrupt sources are fixed default settings. The interrupts except for NMI is masked by the I bit. Eight priority levels can be set for interrupt sources except for NMI with IPR. 8-level interrupt mask control is performed by bits I2 to I0.
2
IPR
I2 to I0
7.6.1
Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests except for NMI are masked by the I bit in CCR of the CPU. Figure 7.3 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, the interrupt request is sent to the interrupt controller. 2. If the I bit in CCR is set to 1, NMI is accepted, and other interrupt requests are held pending. If the I bit is cleared to 0, an interrupt request is accepted. 3. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority, sends the request to the CPU, and holds other interrupt requests pending. 4. When the CPU accepts the interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC and CCR contents are saved to the stack area during the interrupt exception handling. The PC contents saved on the stack is the address of the first instruction to be executed after returning from the interrupt handling routine. 6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
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Section 7 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
Program execution state
Interrupt generated? Yes Yes
No
NMI No I=0 Yes No Pending
No IRQ0 Yes No IRQ1 Yes
TEI4 Yes
Save PC and CCR
I1
Read vector address
Branch to interrupt handling routine
Figure 7.3 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0
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Section 7 Interrupt Controller
7.6.2
Interrupt Control Mode 2
In interrupt control mode 2, interrupt requests except for NMI are masked by comparing the interrupt mask level (I2 to I0 bits) in EXR of the CPU and the IPR setting. There are eight levels in mask control. Figure 7.4 shows a flowchart of the interrupt acceptance operation in this case. 1. If an interrupt request occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. 2. For multiple interrupt requests, the interrupt controller selects the interrupt request with the highest priority according to the IPR setting, and holds other interrupt requests pending. If multiple interrupt requests have the same priority, an interrupt request is selected according to the default setting shown in Table 7.2. 3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. When the interrupt request does not have priority over the mask level set, it is held pending, and only an interrupt request with a priority over the interrupt mask level is accepted. 4. When the CPU accepts an interrupt request, it starts interrupt exception handling after execution of the current instruction has been completed. 5. The PC, CCR, and EXR contents are saved to the stack area during interrupt exception handling. The PC saved on the stack is the address of the first instruction to be executed after returning from the interrupt handling routine. 6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. 7. The CPU generates a vector address for the accepted interrupt and starts execution of the interrupt handling routine at the address indicated by the contents of the vector address in the vector table.
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Section 7 Interrupt Controller
Program execution state
Interrupt generated? Yes Yes NMI No No
No
Level 7 interrupt? Yes Mask level 6 or below? Yes
No Level 6 interrupt? No Yes Level 1 interrupt? Mask level 5 or below? Yes Mask level 0? Yes No Yes No No
Save PC, CCR, and EXR
Pending
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Figure 7.4 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2
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7.6.3
Interrupt acceptance Instruction prefetch Internal operation Stack Vector fetch Internal operation
Interrupt level determination Wait for end of instruction
Instruction prefetch in interrupt handling routine
I
Interrupt request signal
Internal address bus (1) (3) (5) (7) (9)
(11)
Interrupt Exception Handling Sequence
Internal read signal
Internal write signal
Figure 7.5 shows the interrupt exception handling sequence. The example is for the case where interrupt control mode 0 is set in maximum mode, and the program area and stack area are in onchip memory.
Figure 7.5 Interrupt Exception Handling
(2) (4) (6) (8) (10) (6) (8) (9) (10) (11) (12) Saved PC and saved CCR Vector address Start address of interrupt handling routine (vector address contents) Start address of Interrupt handling routine ((11) = (10)) First instruction of interrupt handling routine
Internal data bus
(12)
Section 7 Interrupt Controller
(1)
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Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP - 2 (7) SP - 4
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Section 7 Interrupt Controller
7.6.4
Interrupt Response Times
Table 7.4 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The symbols for execution states used in Table 7.4 are explained in Table 7.5. This LSI is capable of fast word transfer to on-chip memory, so allocating the program area in onchip ROM and the stack area in on-chip RAM enables high-speed processing. Table 7.4 Interrupt Response Times
Normal Mode* Interrupt Control Mode 0
1 5
Advanced Mode Interrupt Control Mode 0 3 1 to 19 + 2*SI Interrupt Control Mode 2
Maximum Mode* Interrupt Control Mode 0
5
Execution State Interrupt priority determination*
Interrupt Control Mode 2
Interrupt Control Mode 2
Number of states until executing 2 instruction ends* PC, CCR, EXR stacking Vector fetch Instruction fetch*
3
SK to 2*SK*
6
2*SK
SK to 2*SK*
6
2*SK
2*SK
2*SK
Sh 2*SI
4
Internal processing*
2 10 to 31 11 to 31 10 to 31 11 to 31 11 to 31 11 to 31
Total (using on-chip memory)
Notes: 1. 2. 3. 4. 5. 6.
Two states for an internal interrupt. In the case of the MULXS or DIVXS instruction Prefetch after interrupt acceptance or for an instruction in the interrupt handling routine. Internal operation after interrupt acceptance or after vector fetch Not available in this LSI. When setting the SP value to 4n, the interrupt response time is SK; when setting to 4n + 2, the interrupt response time is 2*SK.
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Section 7 Interrupt Controller
Table 7.5
Number of Execution States in Interrupt Handling Routine
Object of Access External Device 8-Bit Bus 16-Bit Bus 2-State Access 4 2 4 3-State Access 6 + 2m 3+m 6 + 2m
Symbol Vector fetch Sh Instruction fetch SI Stack manipulation SK
On-Chip Memory 1 1 1
2-State Access 8 4 8
3-State Access 12 + 4m 6 + 2m 12 + 4m
[Legend] m: Number of wait cycles in an external device access.
7.6.5
DTC and DMAC Activation by Interrupt
The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: * * * * Interrupt request to the CPU Activation request to the DTC Activation request to the DMAC Combination of the above
For details on interrupt requests that can be used to activate the DTC and DMAC, see Table 7.2, section 10, DMA Controller (DMAC), and section 12, Data Transfer Controller (DTC). Figure 7.6 shows a block diagram of the DTC, DMAC, and interrupt controller.
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Section 7 Interrupt Controller
Select signal DMRSR_0 to DMRSR_3 Control signal Interrupt request On-chip peripheral module Interrupt request clear signal DMAC select circuit DMAC activation request signal Clear signal DTCER Clear signal DMAC
Select signal Interrupt request Clear signal DTC/CPU Interrupt request IRQ interrupt Interrupt request clear signal select circuit Priority determination Interrupt controller I, I2 to I0 DTC control circuit Clear signal CPU interrupt request vector number CPU DTC activation request vector number DTC
Figure 7.6 Block Diagram of DTC, DMAC, and Interrupt Controller (1) Selection of Interrupt Sources
The activation source for each DMAC channel is selected by DMRSR. The selected activation source is input to the DMAC through the select circuit. When transfer by an on-chip module interrupt is enabled (DTF1 = 1, DTF0 = 0, and DTE = 1 in DMDR) and the DTA bit in DMDR is set to 1, the interrupt source selected for the DMAC activation source is controlled by the DMAC and cannot be used as a DTC activation source or CPU interrupt source. Interrupt sources that are not controlled by the DMAC are set for DTC activation sources or CPU interrupt sources by the DTCE bit in DTCERA to DTCERH of the DTC. Specifying the DISEL bit in MRB of the DTC generates an interrupt request to the CPU by clearing the DTCE bit to 0 after the individual DTC data transfer. Note that when the DTC performs a predetermined number of data transfers and the transfer counter indicates 0, an interrupt request is made to the CPU by clearing the DTCE bit to 0 after the DTC data transfer. When the same interrupt source is set as both the DTC and DMAC activation source and CPU interrupt source, the DTC and DMAC must be given priority over the CPU. If the IPSETE bit in CPUPCR is set to 1, the priority is determined according to the IPR setting. Therefore, the CPUP setting or the IPR setting corresponding to the interrupt source must be set to lower than or equal to the DTCP and DMAP setting. If the CPU is given priority over the DTC or DMAC, the DTC or DMAC may not be activated, and the data transfer may not be performed.
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Section 7 Interrupt Controller
(2)
Priority Determination
The DTC activation source is selected according to the default priority, and the selection is not affected by its mask level or priority level. For respective priority levels, see table 12.1, Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs. (3) Operation Order
If the same interrupt is selected as both the DTC activation source and CPU interrupt source, the CPU interrupt exception handling is performed after the DTC data transfer. If the same interrupt is selected as the DTC or DMAC activation source or CPU interrupt source, respective operations are performed independently. Table 7.6 lists the selection of interrupt sources and interrupt source clear control by setting the DTA bit in DMDR of the DMAC, the DTCE bit in DTCERA to DTCERH of the DTC, and the DISEL bit in MRB of the DTC. Table 7.6 Interrupt Source Selection and Clear Control
DTC Setting DTCE 0 1 DISEL * 0 1 1 * * Interrupt Source Selection/Clear Control DMAC O O O DTC X O X CPU X X
DMAC Setting DTA 0
[Legend] : The corresponding interrupt is used. The interrupt source is cleared. (The interrupt source flag must be cleared in the CPU interrupt handling routine.) O: The corresponding interrupt is used. The interrupt source is not cleared. X: The corresponding interrupt is not available. *: Don't care.
(4)
Usage Note
The interrupt sources of the SCI, and A/D converter are cleared according to the setting shown in Table 7.6, when the DTC or DMAC reads/writes the prescribed register. To initiate multiple channels for the DTC with the same interrupt, the same priority (DTCP = DMAP) should be assigned.
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Section 7 Interrupt Controller
7.7
CPU Priority Control Function Over DTC, DMAC, and EXDMAC
The interrupt controller has a function to control the priority among the DTC, DMAC, EXDMAC, and the CPU by assigning different priority levels to the DTC, DMAC, EXDMAC, and the CPU. Since the priority level can automatically be assigned to the CPU on an interrupt occurrence, it is possible to execute the CPU interrupt exception handling prior to the DTC, DMAC, or EXDMAC transfer. The priority level of the CPU is assigned by bits CPUP2 to CPUP0 in CPUPCR. The priority level of the DTC is assigned by bits DTCP2 to DTCP0 in CPUPCR. The priority level of the DMAC is assigned by bits DMAP2 to DMAP0 in DMDR for each channel. The priority level of the EXDMAC is assigned by bits EDMAP2 to EDMAP0 in the EXDMA mode control register (EDMDR_0 to EDMDE_3) for each channel. The priority control function over the DTC and DMAC is enabled by setting the CPUPCE bit in CPUPCR to 1. When the CPUPCE bit is 1, the DTC, DMAC , and EXDMAC activation sources are controlled according to the respective priority levels. The DTC activation source is controlled according to the priority level of the CPU indicated by bits CPUP2 to CPUP0 and the priority level of the DTC indicated by bits DTCP2 to DTCP0. If the CPU has priority, the DTC activation source is held. The DTC is activated when the condition by which the activation source is held is cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DTCP2 to DTCP0). The priority level of the DTC is assigned by the DTCP2 to DTCP0 bits regardless of the activation source. For the DMAC, the priority level can be specified for each channel. The DMAC activation source is controlled according to the priority level of each DMAC channel indicated by bits DMAP2 to DMAP0 and the priority level of the CPU. If the CPU has priority, the DMAC activation source is held. The DMAC is activated when the condition by which the activation source is held is cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2 to DMAP0). If different priority levels are specified for channels, the channels of the higher priority levels continue transfer and the activation sources for the channels of lower priority levels than that of the CPU are held. For the EXDMAC, the priority level can be specified for each channel. The EXDMAC activation source is controlled according to the priority level of each EXDMAC channel indicated by bits EDMAP2 to EDMAP0 and the priority level of the CPU. If the CPU has priority, the EXDMAC activation source is held. The EXDMAC is activated when the condition by which the activation source is held is cancelled (CPUPCE = 1 and value of bits CPUP2 to CPUP0 is greater than that of bits DMAP2 to EDMAP0). If different priority levels are specified for channels, the channels of
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Section 7 Interrupt Controller
the higher priority levels continue transfer and the activation sources for the channels of lower priority levels than that of the CPU are held. There are two methods for assigning the priority level to the CPU by the IPSETE bit in CPUPCR. Setting the IPSETE bit to 1 enables a function to automatically assign the value of the interrupt mask bit of the CPU to the CPU priority level. Clearing the IPSETE bit to 0 disables the function to automatically assign the priority level. Therefore, the priority level is assigned directly by software rewriting bits CPUP2 to CPUP0. Even if the IPSETE bit is 1, the priority level of the CPU is software assignable by rewriting the interrupt mask bit of the CPU (I bit in CCR or I2 to I0 bits in EXR). The priority level that is automatically assigned when the IPSETE bit is 1 differs according to the interrupt control mode. In interrupt control mode 0, the I bit in CCR of the CPU is reflected in bit CPUP2. Bits CPUP1 and CPUP0 are fixed 0. In interrupt control mode 2, the values of bits I2 to I0 in EXR of the CPU are reflected in bits CPUP2 to CPUP0. Table 7.7 shows the CPU priority control. Table 7.7 CPU Priority Control
Control Status Interrupt Mask Bit I = any I=0 I=1 2 IPR setting I2 to I0 0 1 IPSETE in CPUPCR CPUP2 to CPUP0 0 1 B'111 to B'000 B'000 B'100 B'111 to B'000 I2 to I0 Enabled Disabled Updating of CPUP2 to CPUP0 Enabled Disabled
Interrupt Control Interrupt Mode Priority 0 Default
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Section 7 Interrupt Controller
Table 7.8 shows a setting example of the priority control function over the DTC and DMAC and the transfer request control state. A priority level can be independently set to each DMAC channel, but the table only shows one channel for example. Transfers through the DMAC channels can be separately controlled by assigning different priority levels for channels. Table 7.8
Interrupt Control Mode
Example of Priority Control Function Setting and Control State
CPUPCE CPUP2 in to CPUPCE CPUP0 DTCP2 to DTCP0 DMAP2 to DMAP0 EDMAP2 to EDMAP0 Transfer Request Control State DTC DMAC EXDMAC
0
0 1
Any B'000 B'100 B'100 B'100 B'000
Any B'000 B'000 B'000 B'111 B'111 Any B'000 B'011 B'011 B'011 B'011 B'011 B'011 B'011 B'110
Any B'000 B'000 B'011 B'101 B'101 Any B'000 B'101 B'101 B'101 B'101 B'101 B'101 B'101 B'101
Any B'000 B'000 B'100 B'000 B'000 Any B'000 B'110 B'110 B'110 B'110 B'110 B'110 B'011 B'011
Enabled Enabled Masked Masked Enabled Enabled Enabled Enabled Enabled Enabled Masked Masked Masked Masked Masked Enabled
Enabled Enabled Masked Masked Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Masked Masked Enabled Enabled
Enabled Enabled Masked Enabled Masked Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Masked Masked Masked
2
0 1
Any B'000 B'000 B'011 B'100 B'101 B'110 B'111 B'101 B'101
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Section 7 Interrupt Controller
7.8
7.8.1
Usage Notes
Conflict between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to mask the interrupt, the masking becomes effective after execution of the instruction. When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request with priority over that interrupt, interrupt exception handling will be executed for the interrupt with priority, and another interrupt will be ignored. The same also applies when an interrupt source flag is cleared to 0. Figure 7.7 shows an example in which the TCIEV bit in TIER of the TPU is cleared to 0. The above conflict will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked.
TIER_0 write cycle by CPU TCIV exception handling
P Internal address bus
TIER_0 address
Internal write signal
TCIEV
TCFV
TCIV interrupt signal
Figure 7.7 Conflict between Interrupt Generation and Disabling Similarly, when an interrupt is requested immediately before the DTC enable bit is changed to activate the DTC, DTC activation and the interrupt exception handling by the CPU are both executed. When changing the DTC enable bit, make sure that an interrupt is not requested.
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Section 7 Interrupt Controller
7.8.2
Instructions that Disable Interrupts
Instructions that disable interrupts immediately after execution are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 7.8.3 Times when Interrupts are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction, and for a period of writing to the registers of the interrupt controller. 7.8.4 Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B and the EEPMOV.W instructions. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the transfer is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used.
L1: EEPMOV.W MOV.W BNE R4,R4 L1
7.8.5
Interrupts during Execution of MOVMD and MOVSD Instructions
With the MOVMD or MOVSD instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at the end of the individual transfer cycle. The PC value saved on the stack in this case is the address of the MOVMD or MOVSD instruction. The transfer of the remaining data is resumed after returning from the interrupt handling routine.
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Section 7 Interrupt Controller
7.8.6
Interrupts of Peripheral Modules
To clear an interrupt source flag by the CPU using an interrupt function of a peripheral module, the flag must be read from after clearing within the interrupt processing routine. This makes the request signal synchronized with the peripheral module clock. For details, refer to section 26.5.1, Notes on Clock Pulse Generator.
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Section 7 Interrupt Controller
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Section 8 User Break Controller (UBC)
Section 8 User Break Controller (UBC)
The user break controller (UBC) generates a UBC break interrupt request each time the state of the program counter matches a specified break condition. The UBC break interrupt is a nonmaskable interrupt and is always accepted, regardless of the interrupt control mode and the state of the interrupt mask bit of the CPU. For each channel, the break control register (BRCR) and break address register (BAR) are used to specify the break condition as a combination of address bits and type of bus cycle. Four break conditions are independently specifiable on four channels, A to D.
8.1
Features
* Number of break channels: four (channels A, B, C, and D) * Break comparison conditions (each channel) Address Bus master (CPU cycle) Bus cycle (instruction execution (PC break)) * UBC break interrupt exception handling is executed immediately before execution of the instruction fetched from the specified address (PC break). * Module stop state can be set
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Section 8 User Break Controller (UBC)
8.2
Block Diagram
Instruction execution pointer Instruction execution pointer Break control PC break control
BARAH BARAL
Mode control
Internal bus (output side)
Internal bus (input side)
Break address Break control
Sequential control Flag set control
A ch
Condition Address match comparator determination
UBC break interrupt request
BARBH
BARBL
B ch BARCH BARCL
Condition Address match comparator determination
A ch PC Condition match B ch PC Condition match C ch PC Condition match D ch PC Condition match
BARDH
BARDL
C ch
Condition Address match comparator determination
BRCRA
BRCRB D ch
Condition Address match comparator determination
BRCRC
BRCRD
CPU status
Figure 8.1 Block Diagram of UBC
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Section 8 User Break Controller (UBC)
8.3
Register Descriptions
Table 8.1 lists the register configuration of the UBC. Table 8.1 Register Configuration
Abbreviation BARAH BARAL Break address mask register A BAMRAH BAMRAL Break address register B BARBH BARBL Break address mask register B BAMRBH BAMRBL Break address register C BARCH BARCL Break address mask register C BAMRCH BAMRCL Break address register D BARDH BARDL Break address mask register D BAMRDH BAMRDL Break control register A Break control register B Break control register C Break control register D BRCRA BRCRB BRCRC BRCRD R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 H'0000 Address H'FFA00 H'FFA02 H'FFA04 H'FFA06 H'FFA08 H'FFA0A H'FFA0C H'FFA0E H'FFA10 H'FFA12 H'FFA14 H'FFA16 H'FFA18 H'FFA1A H'FFA1C H'FFA1E H'FFA28 H'FFA2C H'FFA30 H'FFA34 Access Size 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8/16 8/16 8/16 8/16
Register Name Break address register A
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Section 8 User Break Controller (UBC)
8.3.1
Break Address Register n (BARA, BARB, BARC, BARD)
Each break address register n (BARn) consists of break address register nH (BARnH) and break address register nL (BARnL). Together, BARnH and BARnL specify the address used as a break condition on channel n of the UBC.
BARnH
Bit:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BARn31 BARn30 BARn29 BARn28 BARn27 BARn26 BARn25 BARn24 BARn23 BARn22 BARn21 BARn20 BARn19 BARn18 BARn17 BARn16
Initial Value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
BARnL
Bit:
15 14 13 12 11 10 9 BARn9 0 R/W 8 BARn8 0 R/W 7 BARn7 0 R/W 6 BARn6 0 R/W 5 BARn5 0 R/W 4 BARn4 0 R/W 3 BARn3 0 R/W 2 BARn2 0 R/W 1 BARn1 0 R/W 0 BARn0 0 R/W BARn15 BARn14 BARn13 BARn12 BARn11 BARn10
Initial Value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
* BARnH
Bit 31 to 16 Bit Name BARn31 to BARn16 Initial Value All 0 R/W R/W Description Break Address n31 to 16 These bits hold the upper bit values (bits 31 to 16) for the address break-condition on channel n.
[Legend] n = Channels A to D
* BARnL
Bit 15 to 0 Bit Name BARn15 to BARn0 Initial Value All 0 R/W R/W Description Break Address n15 to 0 These bits hold the lower bit values (bits 15 to 0) for the address break-condition on channel n.
[Legend] n = Channels A to D
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Section 8 User Break Controller (UBC)
8.3.2
Break Address Mask Register n (BAMRA, BAMRB, BAMRC, BAMRD)
Be sure to write H'FF00 0000 to break address mask register n (BAMRn). Operation is not guaranteed if another value is written here.
BAMRnH
Bit:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BAMRn31 BAMRn30 BAMRn29 BAMRn28 BAMRn27 BAMRn26 BAMRn25 BAMRn24 BAMRn23 BAMRn22 BAMRn21 BAMRn20 BAMRn19 BAMRn18 BAMRn17 BAMRn16
Initial Value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
BAMRnL
Bit:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BAMRn15 BAMRn14 BAMRn13 BAMRn12 BAMRn11 BAMRn10 BAMRn9 BAMRn8 BAMRn7 BAMRn6 BAMRn5 BAMRn4 BAMRn3 BAMRn2 BAMRn1 BAMRn0
Initial Value: R/W:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
* BAMRnH
Bit 31 to 16 Bit Name Initial Value R/W R/W Description Break Address Mask n31 to 16 Be sure to write H'FF00 here before setting a break condition in the break control register.
BAMRn31 to All 0 BAMRn16
[Legend] n = Channels A to D
* BAMRnL
Bit 15 to 0 Bit Name Initial Value R/W R/W Description Break Address Mask n15 to 0 Be sure to write H'0000 here before setting a break condition in the break control register.
BAMRn15 to All 0 BAMRn0
[Legend] n = Channels A to D
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Section 8 User Break Controller (UBC)
8.3.3
Break Control Register n (BRCRA, BRCRB, BRCRC, BRCRD)
BRCRA, BRCRB, BRCRC, and BRCRD are used to specify and control conditions for channels A, B, C, and D of the UBC.
Bit:
15 14 13 CMFCPn 0 R/W 12 11 CPn2 0 R/W 10 CPn1 0 R/W 9 CPn0 0 R/W 8 7 6 5 IDn1 0 R/W 4 IDn0 0 R/W 3 RWn1 0 R/W 2 RWn0 0 R/W 1 0
-
Initial Value: R/W:
0 R/W
-
0 R/W
-
0 R/W
-
0 R/W
-
0 R/W
-
0 R/W
-
0 R/W
-
0 R/W
[Legend] n = Channels A to D
Bit 15 14 13
Bit Name CMFCPn
Initial Value 0 0 0
R/W R/W R/W R/W
Description Reserved These bits are always read as 0. The write value should always be 0. Condition Match CPU Flag UBC break source flag that indicates satisfaction of a specified CPU bus cycle condition. 0: The CPU cycle condition for channel n break requests has not been satisfied. 1: The CPU cycle condition for channel n break requests has been satisfied.
12
0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
11 10 9
CPn2 CPn1 CPn0
0 0 0
R/W R/W R/W
CPU Cycle Select These bits select CPU cycles as the bus cycle break condition for the given channel. 000: Break requests will not be generated. 001: The bus cycle break condition is CPU cycles. 01x: Setting prohibited 1xx: Setting prohibited
8 7 6

0 0 0
R/W R/W R/W
Reserved These bits are always read as 0. The write value should always be 0.
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Section 8 User Break Controller (UBC)
Bit 5 4
Bit Name IDn1 IDn0
Initial Value 0 0
R/W R/W R/W
Description Break Condition Select These bits select the PC break as the source of UBC break interrupt requests for the given channel. 00: Break requests will not be generated. 01: UBC break condition is the PC break. 1x: Setting prohibited
3 2
RWn1 RWn0
0 0
R/W R/W
Read Select These bits select read cycles as the bus cycle break condition for the given channel. 00: Break requests will not be generated. 01: The bus cycle break condition is read cycles. 1x: Setting prohibited
1 0

0 0
R/W R/W
Reserved These bits are always read as 0. The write value should always be 0.
[Legend] n = Channels A to D
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Section 8 User Break Controller (UBC)
8.4
Operation
The UBC does not detect condition matches in standby states (sleep mode, all module clock stop mode, software standby mode, deep software standby, and hardware standby mode). 8.4.1 Setting of Break Control Conditions
1. The address condition for the break is set in break address register n (BARn). A mask for the address is set in break address mask register n (BAMRn). 2. The bus and break conditions are set in break control register n (BRCRn). Bus conditions consist of CPU cycle, PC break, and reading. Condition comparison is not performed when the CPU cycle setting is CPn = B'000, the PC break setting is IDn = B'00, or the read setting is RWn = B'00. 3. The condition match CPU flag (CMFCPn) is set in the event of a break condition match on the corresponding channel. These flags are set when the break condition matches but are not cleared when it no longer does. To confirm setting of the same flag again, read the flag once from the break interrupt handling routine, and then write 0 to it (the flag is cleared by writing 0 to it after reading it as 1). [Legend] n = Channels A to D 8.4.2 PC Break
1. When specifying a PC break, specify the address as the first address of the required instruction. If the address for a PC break condition is not the first address of an instruction, a break will never be generated. 2. The break occurs after fetching and execution of the target instruction have been confirmed. In cases of contention between a break before instruction execution and a user maskable interrupt, priority is given to the break before instruction execution. 3. A break will not be generated even if a break before instruction execution is set in a delay slot. 4. The PC break condition is generated by specifying CPU cycles as the bus condition in break control register n (BRCRn.CPn0 = 1), PC break as the break condition (IDn0 = 1), and read cycles as the bus-cycle condition (RWn0 = 1). [Legend] n = Channels A to D
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Section 8 User Break Controller (UBC)
8.4.3
Condition Match Flag
Condition match flags are set when the break conditions match. The condition match flags of the UBC are listed in Table 8.2. Table 8.2
Register BRCRA BRCRB BRCRC BRCRD
List of Condition Match Flags
Flag Bit CMFCPA (bit 13) CMFCPB (bit 13) CMFCPC (bit 13) CMFCPD (bit 13) Source Indicates that the condition matches in the CPU cycle for channel A Indicates that the condition matches in the CPU cycle for channel B Indicates that the condition matches in the CPU cycle for channel C Indicates that the condition matches in the CPU cycle for channel D
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Section 8 User Break Controller (UBC)
8.5
Usage Notes
1. PC break usage note Contention between a SLEEP instruction (to place the chip in the sleep state or on software standby) and PC break If a break before a PC break instruction is set for the instruction after a SLEEP instruction and the SLEEP instruction is executed with the SSBY bit cleared to 0, break interrupt exception handling is executed without sleep mode being entered. In this case, the instruction after the SLEEP instruction is executed after the RTE instruction. When the SSBY bit is set to 1, break interrupt exception handling is executed after the oscillation settling time has elapsed subsequent to the transition to software standby mode. When an interrupt is the canceling source, interrupt exception handling is executed after the RTE instruction, and the instruction following the SLEEP instruction is then executed.
CLK SLEEP
Cancelling source Software standby Break interrupt exception handling (PC break source) Interrupt exception handling (Cancelling source)
Figure 8.2 Contention between SLEEP Instruction (Software Standby) and PC Break 2. Prohibition on Setting of PC Break Setting of a UBC break interrupt for program within the UBC break interrupt handling routine is prohibited. 3. The procedure for clearing a UBC flag bit (condition match flag) is shown below. A flag bit is cleared by writing 0 to it after reading it as 1. As the register that contains the flag bits is accessible in byte units, bit manipulation instructions can be used.
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Section 8 User Break Controller (UBC)
CKS
Register read The value read as 1 is retained Register write Flag bit Flag bit is set to 1 Flag bit is cleared to 0
Figure 7.3 Flag Bit Clearing Sequence (Condition Match Flag) 4. After setting break conditions for the UBC, an unexpected UBC break interrupt may occur after the execution of an illegal instruction. This depends on the value of the program counter and the internal bus cycle.
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Section 8 User Break Controller (UBC)
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Section 9 Bus Controller (BSC)
Section 9 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters; CPU, DMAC, EXDMAC, and DTC.
9.1
Features
* Manages external address space in area units Manages the external address space divided into eight areas Chip select signals (CS0 to CS7) can be output for each area Bus specifications can be set independently for each area 8-bit access or 16-bit access can be selected for each area Burst ROM, byte control SRAM, or address/data multiplexed I/O interface can be set An endian conversion function is provided to connect a device of little endian * Basic bus interface This interface can be connected to the SRAM and ROM 2-state access or 3-state access can be selected for each area Program wait cycles can be inserted for each area Wait cycles can be inserted by the WAIT pin. Extension cycles can be inserted while CSn is asserted for each area (n = 0 to 7) The negation timing of the read strobe signal (RD) can be modified * Byte control SRAM interface Byte control SRAM interface can be set for areas 0 to 7 The SRAM that has a byte control pin can be directly connected * Burst ROM interface Burst ROM interface can be set for areas 0 and 1 Burst ROM interface parameters can be set independently for areas 0 and 1 * Address/data multiplexed I/O interface Address/data multiplexed I/O interface can be set for areas 3 to 7
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Section 9 Bus Controller (BSC)
* Idle cycle insertion Idle cycles can be inserted between external read accesses to different areas Idle cycles can be inserted before the external write access after an external read access Idle cycles can be inserted before the external read access after an external write access Idle cycles can be inserted before the external access after a DMAC/EXDMAC single address transfer (write access) * Write buffer function External write cycles and internal accesses can be executed in parallel Write accesses to the on-chip peripheral module and on-chip memory accesses can be executed in parallel DMAC single address transfers and internal accesses can be executed in parallel * External bus release function * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, EXDMAC, DTC, and external bus master * EXDMAC transfers to the external buses and internal accesses can be executed in parallel * Multi-clock function The internal peripheral functions can be operated in synchronization with the peripheral module clock (P). Accesses to the external address space can be operated in synchronization with the external bus clock (B). * The bus start (BS) and read/write (RD/WR) signals can be output.
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Section 9 Bus Controller (BSC)
A block diagram of the bus controller is shown in Figure 9.1.
CPU address bus
DMAC address bus DTC address bus EXDMAC address bus
Address selector
Area decoder
CS7 to CS0
Internal bus control signals
CPU bus mastership acknowledge signal DTC bus mastership acknowledge signal DMAC bus mastership acknowledge signal CPU bus mastership request signal DTC bus mastership request signal DMAC bus mastership request signal
EXDMAC bus mastership acknowledge signal EXDMAC bus mastership request signal
Internal bus control unit External bus control unit
Internal bus arbiter
External bus control signals
WAIT
External bus arbiter
BREQ BACK BREQO
Control register
Internal data bus
ABWCR ASTCR WTCRA WTCRB RDNCR CSACR
IDLCR BCR1 BCR2 ENDIANCR
SRAMCR BROMCR MPXCR
[Legend] ABWCR: Bus width control register ASTCR: Access state control register WTCRA: Wait control register A WTCRB: Wait control register B RDNCR: Read strobe timing control register CSACR: CS assertion period control register IDLCD: Idle control register
BCR1: Bus control register 1 BCR2: Bus control register 2 ENDIANCR: Endian control register SRAMCR: SRAM mode control register BROMCR: Burst ROM interface control register MPXCR: Address/data multiplexed I/O control register
Figure 9.1 Block Diagram of Bus Controller
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Section 9 Bus Controller (BSC)
9.2
Register Descriptions
The bus controller has the following registers. * * * * * * * * * * * * * Bus width control register (ABWCR) Access state control register (ASTCR) Wait control register A (WTCRA) Wait control register B (WTCRB) Read strobe timing control register (RDNCR) CS assertion period control register (CSACR) Idle control register (IDLCR) Bus control register 1 (BCR1) Bus control register 2 (BCR2) Endian control register (ENDIANCR) SRAM mode control register (SRAMCR) Burst ROM interface control register (BROMCR) Address/data multiplexed I/O control register (MPXCR)
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Section 9 Bus Controller (BSC)
9.2.1
Bus Width Control Register (ABWCR)
ABWCR specifies the data bus width for each area in the external address space.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 ABWH7 1 R/W 7 ABWL7 1 R/W 14 ABWH6 1 R/W 6 ABWL6 1 R/W 13 ABWH5 1 R/W 5 ABWL5 1 R/W 12 ABWH4 1 R/W 4 ABWL4 1 R/W 11 ABWH3 1 R/W 3 ABWL3 1 R/W 10 ABWH2 1 R/W 2 ABWL2 1 R/W 9 ABWH1 1 R/W 1 ABWL1 1 R/W 8 ABWH0 1/0 R/W 0 ABWL0 1 R/W
Note: * Initial value at 16-bit bus initiation is H'FEFF, and that at 8-bit bus initiation is H'FFFF.
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name ABWH7 ABWH6 ABWH5 ABWH4 ABWH3 ABWH2 ABWH1 ABWL0 ABWL7 ABWL6 ABWL5 ABWL4 ABWL3 ABWL2 ABWL1 ABWL0
Initial Value*1 1 1 1 1 1 1 1 1/0 1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Area 7 to 0 Bus Width Control These bits select whether the corresponding area is to be designated as 8-bit access space or 16-bit access space. ABWHn ABWLn (n = 7 to 0) x 0: Setting prohibited 0 1: Area n is designated as 16-bit access space 1 1: Area n is designated as 8-bit access 2 space*
[Legend] x: Don't care Notes: 1. Initial value at 16-bit bus initiation is H'FEFF, and that at 8-bit bus initiation is H'FFFF. 2. An address space specified as byte control SRAM interface must not be specified as 8bit access space.
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Section 9 Bus Controller (BSC)
9.2.2
Access State Control Register (ASTCR)
ASTCR designates each area in the external address space as either 2-state access space or 3-state access space and enables/disables wait cycle insertion.
Bit Bit Name Initial Value R/W
Bit Bit Name Initial Value R/W
15 AST7 1 R/W
7 0 R
14 AST6 1 R/W
6 0 R
13 AST5 1 R/W
5 0 R
12 AST4 1 R/W
4 0 R
11 AST3 1 R/W
3 0 R
10 AST2 1 R/W
2 0 R
9 AST1 1 R/W
1 0 R
8 AST0 1 R/W
0 0 R
Bit 15 14 13 12 11 10 9 8
Bit Name AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0
Initial Value 1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Area 7 to 0 Access State Control These bits select whether the corresponding area is to be designated as 2-state access space or 3-state access space. Wait cycle insertion is enabled or disabled at the same time. 0: Area n is designated as 2-state access space Wait cycle insertion in area n access is disabled 1: Area n is designated as 3-state access space Wait cycle insertion in area n access is enabled (n = 7 to 0) Reserved These are read-only bits and cannot be modified.
7 to 0
All 0
R
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Section 9 Bus Controller (BSC)
9.2.3
Wait Control Registers A and B (WTCRA, WTCRB)
WTCRA and WTCRB select the number of program wait cycles for each area in the external address space.
* WTCRA Bit Bit Name Initial Value R/W
Bit Bit Name Initial Value R/W
15 0 R
7 0 R
14 W72 1 R/W
6 W52 1 R/W
13 W71 1 R/W
5 W51 1 R/W
12 W70 1 R/W
4 W50 1 R/W
11 0 R
3 0 R
10 W62 1 R/W
2 W42 1 R/W
9 W61 1 R/W
1 W41 1 R/W
8 W60 1 R/W
0 W40 1 R/W
* WTCRB
Bit Bit Name Initial Value R/W
Bit Bit Name Initial Value R/W
15 0 R
7 0 R
14 W32 1 R/W
6 W12 1 R/W
13 W31 1 R/W
5 W11 1 R/W
12 W30 1 R/W
4 W10 1 R/W
11 0 R
3 0 R
10 W22 1 R/W
2 W02 1 R/W
9 W21 1 R/W
1 W01 1 R/W
8 W20 1 R/W
0 W00 1 R/W
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Section 9 Bus Controller (BSC)
* WTCRA
Bit 15 14 13 12 Bit Name W72 W71 W70 Initial Value 0 1 1 1 R/W R R/W R/W R/W Description Reserved This is a read-only bit and cannot be modified. Area 7 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 7 while bit AST7 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 11 10 9 8 W62 W61 W60 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Area 6 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 6 while bit AST6 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 7 0 R Reserved This is a read-only bit and cannot be modified.
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Section 9 Bus Controller (BSC)
Bit 6 5 4
Bit Name W52 W51 W50
Initial Value 1 1 1
R/W R/W R/W R/W
Description Area 5 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 5 while bit AST5 in ASTCR is 1. 000: Program cycle wait not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted
3 2 1 0
W42 W41 W40
0 1 1 1
R R/W R/W R/W
Reserved This is a read-only bit and cannot be modified. Area 4 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 4 while bit AST4 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted
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Section 9 Bus Controller (BSC)
* WTCRB
Bit 15 14 13 12 Bit Name W32 W31 W30 Initial Value 0 1 1 1 R/W R R/W R/W R/W Description Reserved This is a read-only bit and cannot be modified. Area 3 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 3 while bit AST3 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 11 10 9 8 W22 W21 W20 0 1 1 1 R R/W R/W R/W Reserved This is a read-only bit and cannot be modified. Area 2 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 2 while bit AST2 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted 7 0 R Reserved This is a read-only bit and cannot be modified.
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Section 9 Bus Controller (BSC)
Bit 6 5 4
Bit Name W12 W11 W10
Initial Value 1 1 1
R/W R/W R/W R/W
Description Area 1 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 1 while bit AST1 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted
3 2 1 0
W02 W01 W00
0 1 1 1
R R/W R/W R/W
Reserved This is a read-only bit and cannot be modified. Area 0 Wait Control 2 to 0 These bits select the number of program wait cycles when accessing area 0 while bit AST0 in ASTCR is 1. 000: Program wait cycle not inserted 001: 1 program wait cycle inserted 010: 2 program wait cycles inserted 011: 3 program wait cycles inserted 100: 4 program wait cycles inserted 101: 5 program wait cycles inserted 110: 6 program wait cycles inserted 111: 7 program wait cycles inserted
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Section 9 Bus Controller (BSC)
9.2.4
Read Strobe Timing Control Register (RDNCR)
RDNCR selects the negation timing of the read strobe signal (RD) when reading the external address spaces specified as a basic bus interface or the address/data multiplexed I/O interface.
Bit Bit Name Initial Value R/W
Bit Bit Name Initial Value R/W
15 RDN7 0 R/W
7 0 R
14 RDN6 0 R/W
6 0 R
13 RDN5 0 R/W
5 0 R
12 RDN4 0 R/W
4 0 R
11 RDN3 0 R/W
3 0 R
10 RDN2 0 R/W
2 0 R
9 RDN1 0 R/W
1 0 R
8 RDN0 0 R/W
0 0 R
Bit 15 14 13 12 11 10 9 8
Bit Name RDN7 RDN6 RDN5 RDN4 RDN3 RDN2 RDN1 RDN0
Initial Value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Read Strobe Timing Control RDN7 to RDN0 set the negation timing of the read strobe in a corresponding area read access. As shown in Figure 9.2, the read strobe for an area for which the RDNn bit is set to 1 is negated one halfcycle earlier than that for an area for which the RDNn bit is cleared to 0. The read data setup and hold time are also given one half-cycle earlier. 0: In an area n read access, the RD signal is negated at the end of the read cycle 1: In an area n read access, the RD signal is negated one half-cycle before the end of the read cycle (n = 7 to 0)
7 to 0
All 0
R
Reserved These are read-only bits and cannot be modified.
Notes: 1. In an external address space which is specified as byte control SRAM interface, the RDNCR setting is ignored and the same operation when RDNn = 1 is performed. 2. In an external address space which is specified as burst ROM interface, the RDNCR setting is ignored during read accesses by the CPU and EXDMAC cluster transfer, and the same operation when RDNn = 0 is performed.
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Section 9 Bus Controller (BSC)
Bus cycle T1
B
T2
T3
RD
RDNn = 0
Data RD
RDNn = 1
Data
(n = 7 to 0)
Figure 9.2 Read Strobe Negation Timing (Example of 3-State Access Space) 9.2.5 CS Assertion Period Control Registers (CSACR)
CSACR selects whether or not the assertion periods of the chip select signals (CSn) and address signals for the basic bus, byte-control SRAM, burst ROM, and address/data multiplexed I/O interface are to be extended. Extending the assertion period of the CSn and address signals allows the setup time and hold time of read strobe (RD) and write strobe (LHWR/LLWR) to be assured and to make the write data setup time and hold time for the write strobe become flexible.
Bit Bit Name Initial Value R/W
Bit Bit Name Initial Value R/W
15 CSXH7 0 R/W
7 CSXT7 0 R/W
14 CSXH6 0 R/W
6 CSXT6 0 R/W
13 CSXH5 0 R/W
5 CSXT5 0 R/W
12 CSXH4 0 R/W
4 CSXT4 0 R/W
11 CSXH3 0 R/W
3 CSXT3 0 R/W
10 CSXH2 0 R/W
2 CSXT2 0 R/W
9 CSXH1 0 R/W
1 CSXT1 0 R/W
8 CSXH0 0 R/W
0 CSXT0 0 R/W
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Section 9 Bus Controller (BSC)
Bit 15 14 13 12 11 10 9 8
Bit Name CSXH7 CSXH6 CSXH5 CSXH4 CSXH3 CSXH2 CSXH1 CSXH0
Initial Value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description CS and Address Signal Assertion Period Control 1 These bits specify whether or not the Th cycle is to be inserted (see Figure 9.3). When an area for which bit CSXHn is set to 1 is accessed, one Th cycle, in which the CSn and address signals are asserted, is inserted before the normal access cycle. 0: In access to area n, the CSn and address assertion period (Th) is not extended 1: In access to area n, the CSn and address assertion period (Th) is extended (n = 7 to 0) CS and Address Signal Assertion Period Control 2 These bits specify whether or not the Tt cycle is to be inserted (see Figure 9.3). When an area for which bit CSXTn is set to 1 is accessed, one Tt cycle, in which the CSn and address signals are retained, is inserted after the normal access cycle. 0: In access to area n, the CSn and address assertion period (Tt) is not extended 1: In access to area n, the CSn and address assertion period (Tt) is extended (n = 7 to 0)
7 6 5 4 3 2 1 0
CSXT7 CSXT6 CSXT5 CSXT4 CSXT3 CSXT2 CSXT1 CSXT0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Note:
*
In burst ROM interface, the CSXTn settings are ignored during read accesses by the CPU and EXDMAC cluster transfer
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Section 9 Bus Controller (BSC)
Bus cycle Th B T1 T2 T3 Tt
Address CSn AS BS
RD/WR
RD Read Data bus Read data
LHWR, LLWR Write Data bus Write data
Figure 9.3 CS and Address Assertion Period Extension (Example of Basic Bus Interface, 3-State Access Space, and RDNn = 0)
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Section 9 Bus Controller (BSC)
9.2.6
Idle Control Register (IDLCR)
IDLCR specifies the idle cycle insertion conditions and the number of idle cycles.
Bit Bit Name Initial Value R/W
Bit Bit Name Initial Value R/W
15 IDLS3 1 R/W
7 IDLSEL7 0 R/W
14 IDLS2 1 R/W
6 IDLSEL6 0 R/W
13 IDLS1 1 R/W
5 IDLSEL5 0 R/W
12 IDLS0 1 R/W
4 IDLSEL4 0 R/W
11 IDLCB1 1 R/W
3 IDLSEL3 0 R/W
10 IDLCB0 1 R/W
2 IDLSEL2 0 R/W
9 IDLCA1 1 R/W
1 IDLSEL1 0 R/W
8 IDLCA0 1 R/W
0 IDLSEL0 0 R/W
Bit 15
Bit Name IDLS3
Initial Value 1
R/W R/W
Description Idle Cycle Insertion 3 Inserts an idle cycle between the bus cycles when the DMAC/EXDMAC single address transfer (write cycle) is followed by external access. 0: No idle cycle is inserted 1: An idle cycle is inserted
14
IDLS2
1
R/W
Idle Cycle Insertion 2 Inserts an idle cycle between the bus cycles when the external write cycle is followed by external read cycle. 0: No idle cycle is inserted 1: An idle cycle is inserted
13
IDLS1
1
R/W
Idle Cycle Insertion 1 Inserts an idle cycle between the bus cycles when the external read cycles of different areas continue. 0: No idle cycle is inserted 1: An idle cycle is inserted
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Section 9 Bus Controller (BSC)
Bit 12
Bit Name IDLS0
Initial Value 1
R/W R/W
Description Idle Cycle Insertion 0 Inserts an idle cycle between the bus cycles when the external read cycle is followed by external write cycle. 0: No idle cycle is inserted 1: An idle cycle is inserted
11 10
IDLCB1 IDLCB0
1 1
R/W R/W
Idle Cycle State Number Select B Specifies the number of idle cycles to be inserted for the idle condition specified by IDLS1 and IDLS0. 00: No idle cycle is inserted 01: 2 idle cycles are inserted 00: 3 idle cycles are inserted 01: 4 idle cycles are inserted
9 8
IDLCA1 IDLCA0
1 1
R/W R/W
Idle Cycle State Number Select A Specifies the number of idle cycles to be inserted for the idle condition specified by IDLS3 to IDLS0. 00: 1 idle cycle is inserted 01: 2 idle cycles are inserted 10: 3 idle cycles are inserted 11: 4 idle cycles are inserted
7 6 5 4 3 2 1 0
IDLSEL7 IDLSEL6 IDLSEL5 IDLSEL4 IDLSEL3 IDLSEL2 IDLSEL1 IDLSEL0
0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Idle Cycle Number Select Specifies the number of idle cycles to be inserted for each area for the idle insertion condition specified by IDLS1 and IDLS0. 0: Number of idle cycles to be inserted for area n is specified by IDLCA1 and IDLCA0. 1: Number of idle cycles to be inserted for area n is specified by IDLCB1 and IDLCB0. (n = 7 to 0)
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Section 9 Bus Controller (BSC)
9.2.7
Bus Control Register 1 (BCR1)
BCR1 is used for selection of the external bus released state protocol, enabling/disabling of the write data buffer function, and enabling/disabling of the WAIT pin input.
Bit Bit Name Initial Value R/W
Bit Bit Name Initial Value R/W
15 BRLE 0 R/W
7 DKC 0 R/W
14 BREQOE 0 R/W
6 EDKC 0 R/W
13 0 R
5 0 R
12 0 R
4 0 R
11 0 R/W
3 0 R
10 0 R/W
2 0 R
9 WDBE 0 R/W
1 0 R
8 WAITE 0 R/W
0 0 R
Bit 15
Bit Name BRLE
Initial Value 0
R/W R/W
Description External Bus Release Enable Enables/disables external bus release. 0: External bus release disabled BREQ, BACK, and BREQO pins can be used as I/O ports 1: External bus release enabled* For details, see section 13, I/O Ports. BREQO Pin Enable Controls outputting the bus request signal (BREQO) to the external bus master in the external bus released state when an internal bus master performs an external address space access. 0: BREQO output disabled BREQO pin can be used as I/O port 1: BREQO output enabled
14
BREQOE
0
R/W
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Section 9 Bus Controller (BSC)
Bit 13, 12 11, 10
Bit Name
Initial Value All 0 All 0
R/W R R/W
Description Reserved These are read-only bits and cannot be modified. Reserved These bits are always read as 0. The write value should always be 0.
9
WDBE
0
R/W
Write Data Buffer Enable The write data buffer function can be used for an external write cycle and a DMAC single address transfer cycle. The changed setting may not affect an external access immediately after the change. 0: Write data buffer function not used 1: Write data buffer function used
8
WAITE
0
R/W
WAIT Pin Enable Selects enabling/disabling of wait input by the WAIT pin. 0: Wait input by WAIT pin disabled WAIT pin can be used as I/O port 1: Wait input by WAIT pin enabled For details, see section 13, I/O Ports.
7
DKC
0
R/W
DACK Control Selects the timing of DMAC transfer acknowledge signal assertion. 0: DACK signal is asserted at the B falling edge 1: DACK signal is asserted at the B rising edge
6
EDKC
0
R/W
EDACK Control Selects the timing of EXDMAC transfer acknowledge signal assertion. 0: EDACK signal is asserted at the B falling edge 1: EDACK signal is asserted at the B rising edge
5 to 0
All 0
R
Reserved These are read-only bits and cannot be modified.
Note: When external bus release is enabled or input by the WAIT pin is enabled, make sure to set the ICR bit to 1. For details, see section 13, I/O Ports.
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Section 9 Bus Controller (BSC)
9.2.8
Bus Control Register 2 (BCR2)
BCR2 is used for bus arbitration control of the CPU, DMAC, EXDMAC, and DTC, and enabling/disabling of the write data buffer function to the peripheral modules.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 EBCCS 0 R/W 4 IBCCS 0 R/W 3 0 R 2 0 R 1 1 R/W
0 PWDBE 0 R/W
Bit 7, 6 5
Bit Name EBCCS
Initial Value All 0 0
R/W R R/W
Description Reserved These are read-only bits and cannot be modified. External Bus Cycle Control Select Selects the external bus arbiter function. 0: Releases the bus mastership according to the priority 1: Executes the bus cycles alternatively when an EXDMAC or external bus master conflict with a CPU, DMAC, or DTC external space access request
4
IBCCS
0
R/W
Internal Bus Cycle Control Select Selects the internal bus arbiter function. 0: Releases the bus mastership according to the priority 1: Executes the bus cycles alternatively when a CPU bus mastership request conflicts with a DMAC or DTC bus mastership request
3, 2 1

All 0 1
R R/W
Reserved These are read-only bits and cannot be modified. Reserved This bit is always read as 1. The write value should always be 1.
0
PWDBE
0
R/W
Peripheral Module Write Data Buffer Enable Specifies whether or not to use the write data buffer function for the peripheral module write cycles. 0: Write data buffer function not used 1: Write data buffer function used
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Section 9 Bus Controller (BSC)
9.2.9
Endian Control Register (ENDIANCR)
ENDIANCR selects the endian format for each area of the external address space. Though the data format of this LSI is big endian, data can be transferred in the little endian format during external address space access. Note that the data format for the areas used as a program area or a stack area should be big endian.
Bit Bit Name Initial Value R/W 7 LE7 0 R/W 6 LE6 0 R/W 5 LE5 0 R/W 4 LE4 0 R/W 3 LE3 0 R/W 2 LE2 0 R/W 1 0 R
0 0 R
Bit 7 6 5 4 3 2 1, 0
Bit Name LE7 LE6 LE5 LE4 LE3 LE2
Initial Value 0 0 0 0 0 0 All 0
R/W R/W R/W R/W R/W R/W R/W R
Description Little Endian Select Selects the endian for the corresponding area. 0: Data format of area n is specified as big endian 1: Data format of area n is specified as little endian (n = 7 to 2) Reserved These are read-only bits and cannot be modified.
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Section 9 Bus Controller (BSC)
9.2.10
SRAM Mode Control Register (SRAMCR)
SRAMCR specifies the bus interface of each area in the external address space as a basic bus interface or a byte control SRAM interface. In areas specified as 8-bit access space by ABWCR, the SRAMCR setting is ignored and the byte control SRAM interface cannot be specified.
Bit Bit Name Initial Value R/W
Bit Bit Name Initial Value R/W
15 BCSEL7 0 R/W
7 0 R
14 BCSEL6 0 R/W
6 0 R
13 BCSEL5 0 R/W
5 0 R
12 BCSEL4 0 R/W
4 0 R
11 BCSEL3 0 R/W
3 0 R
10 BCSEL2 0 R/W
2 0 R
9 BCSEL1 0 R/W
1 0 R
8 BCSEL0 0 R/W
0 0 R
Bit 15 14 13 12 11 10 9 8 7 to 0
Bit Name BCSEL7 BCSEL6 BCSEL5 BCSEL4 BCSEL3 BCSEL2 BCSEL1 BCSEL0
Initial Value 0 0 0 0 0 0 0 0 All 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R
Description Byte Control SRAM Interface Select Selects the bus interface for the corresponding area. When setting a bit to 1, the bus interface select bits in BROMCR and MPXCR must be cleared to 0. 0: Area n is basic bus interface 1: Area n is byte control SRAM interface (n = 7 to 0)
Reserved These are read-only bits and cannot be modified.
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Section 9 Bus Controller (BSC)
9.2.11
Burst ROM Interface Control Register (BROMCR)
BROMCR specifies the burst ROM interface.
Bit Bit Name Initial Value R/W
Bit Bit Name Initial Value R/W
15 BSRM0 0 R/W
7 BSRM1 0 R/W
14 BSTS02 0 R/W
6 BSTS12 0 R/W
13 BSTS01 0 R/W
5 BSTS11 0 R/W
12 BSTS00 0 R/W
4 BSTS10 0 R/W
11 0 R
3 0 R
10 0 R
2 0 R
9 BSWD01 0 R/W
1 BSWD11 0 R/W
8 BSWD00 0 R/W
0 BSWD10 0 R/W
Bit 15
Bit Name BSRM0
Initial Value 0
R/W R/W
Description Area 0 Burst ROM Interface Select Specifies the area 0 bus interface. To set this bit to 1, clear bit BCSEL0 in SRAMCR to 0. 0: Basic bus interface or byte-control SRAM interface 1: Burst ROM interface
14 13 12
BSTS02 BSTS01 BSTS00
0 0 0
R/W R/W R/W
Area 0 Burst Cycle Select Specifies the number of burst cycles of area 0 000: 1 cycle 001: 2 cycles 010: 3 cycles 011: 4 cycles 100: 5 cycles 101: 6 cycles 110: 7 cycles 111: 8 cycles
11, 10
All 0
R
Reserved These are read-only bits and cannot be modified.
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Section 9 Bus Controller (BSC)
Bit 9 8
Bit Name BSWD01 BSWD00
Initial Value 0 0
R/W R/W R/W
Description Area 0 Burst Word Number Select Selects the number of words in burst access to the area 0 burst ROM interface 00: Up to 4 words (8 bytes) 01: Up to 8 words (16 bytes) 10: Up to 16 words (32 bytes) 11: Up to 32 words (64 bytes)
7
BSRM1
0
R/W
Area 1 Burst ROM Interface Select Specifies the area 1 bus interface as a basic interface or a burst ROM interface. To set this bit to 1, clear bit BCSEL1 in SRAMCR to 0. 0: Basic bus interface or byte-control SRAM interface 1: Burst ROM interface
6 5 4
BSTS12 BSTS11 BSTS10
0 0 0
R/W R/W R/W
Area 1 Burst Cycle Select Specifies the number of cycles of area 1 burst cycle 000: 1 cycle 001: 2 cycles 010: 3 cycles 011: 4 cycles 100: 5 cycles 101: 6 cycles 110: 7 cycles 111: 8 cycles
3 2 1 0
BSWD11 BSWD10
All 0 0 0
R R/W R/W
Reserved These are read-only bits and cannot be modified. Area 1 Burst Word Number Select Selects the number of words in burst access to the area 1 burst ROM interface 00: Up to 4 words (8 bytes) 01: Up to 8 words (16 bytes) 10: Up to 16 words (32 bytes) 11: Up to 32 words (64 bytes)
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Section 9 Bus Controller (BSC)
9.2.12
Address/Data Multiplexed I/O Control Register (MPXCR)
MPXCR specifies the address/data multiplexed I/O interface.
Bit Bit Name Initial Value R/W
Bit Bit Name Initial Value R/W
15 MPXE7 0 R/W
7 0 R
14 MPXE6 0 R/W
6 0 R
13 MPXE5 0 R/W
5 0 R
12 MPXE4 0 R/W
4 0 R
11 MPXE3 0 R/W
3 0 R
10 0 R
2 0 R
9 0 R
1 0 R
8 0 R
0 ADDEX 0 R/W
Bit 15 14 13 12 11
Bit Name MPXE7 MPXE6 MPXE5 MPXE4 MPXE3
Initial Value 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
Description Address/Data Multiplexed I/O Interface Select Specifies the bus interface for the corresponding area. To set this bit to 1, clear the BCSELn bit in SRAMCR to 0. 0: Area n is specified as a basic interface or a byte control SRAM interface. 1: Area n is specified as an address/data multiplexed I/O interface (n = 7 to 3)
10 to 1 0 ADDEX
All 0 0
R R/W
Reserved These are read-only bits and cannot be modified. Address Output Cycle Extension Specifies whether a wait cycle is inserted for the address output cycle of address/data multiplexed I/O interface. 0: No wait cycle is inserted for the address output cycle 1: One wait cycle is inserted for the address output cycle
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Section 9 Bus Controller (BSC)
9.3
Bus Configuration
Figure 9.4 shows the internal bus configuration of this LSI. The internal bus of this LSI consists of the following three types. * Internal system bus 1 A bus that connects the CPU, DTC, DMAC, on-chip RAM, on-chip ROM, internal peripheral bus, and external access bus. * Internal system bus 2 A bus that connects the EXDMAC and external access bus. * Internal peripheral bus A bus that accesses registers in the bus controller, interrupt controller, DMAC, and EXDMAC, and registers of peripheral modules such as SCI and timer. * External access bus A bus that accesses external devices via the external bus interface.
I synchronization
CPU
DTC
On-chip RAM
On-chip ROM
Internal system bus 1
Internal system bus 2
Write data buffer
Bus controller, interrupt controller, power-down controller
DMAC
EXDMAC
Write data buffer
Internal peripheral bus
External access bus
P synchronization
Peripheral functions
B synchronization
External bus interface
Figure 9.4 Internal Bus Configuration
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Section 9 Bus Controller (BSC)
9.4
Multi-Clock Function and Number of Access Cycles
The internal functions of this LSI operate synchronously with the system clock (I), the peripheral module clock (P), or the external bus clock (B). Table 9.1 shows the synchronization clock and their corresponding functions. Table 9.1 Synchronization Clocks and Their Corresponding Functions
Function Name MCU operating mode Interrupt controller Bus controller CPU DTC DMAC EXDMAC Internal memory Clock pulse generator Power down control I/O ports TPU PPG TMR WDT SCI A/D D/A IIC2 USB External bus interface
Synchronization Clock I
P
B
The frequency of each synchronization clock (I, P, and B) is specified by the system clock control register (SCKCR) independently. For further details, see section 26, Clock Pulse Generator. There will be cases when P and B are equal to I and when P and B are different from I according to the SCKCR specifications. In any case, access cycles for internal peripheral functions and external space is performed synchronously with P and B, respectively.
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Section 9 Bus Controller (BSC)
For example, in an external address space access where the frequency rate of I and B is n : 1, the operation is performed in synchronization with B. In this case, external 2-state access space is 2n cycles and external 3-state access space is 3n cycles (no wait cycles is inserted) if the number of access cycles is counted based on I. If the frequencies of I, P and B are different, the start of bus cycle may not synchronize with P or B according to the bus cycle initiation timing. In this case, clock synchronization cycle (Tsy) is inserted at the beginning of each bus cycle. For example, if an external address space access occurs when the frequency rate of I and B is n : 1, 0 to n-1 cycles of Tsy may be inserted. If an internal peripheral module access occurs when the frequency rate of I and P is m : 1, 0 to m-1 cycles of Tsy may be inserted. Figure 9.5 shows the external 2-state access timing when the frequency rate of I and B is 4 : 1. Figure 9.6 shows the external 3-state access timing when the frequency rate of I and B is 2 : 1.
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Section 9 Bus Controller (BSC)
Divided clock synchronization cycle
Tsy
T1
T2
I
B
Address CSn AS RD
Read
D15 to D8 D7 to D0
LHWR LLWR
Write
D15 to D8
D7 to D0 BS RD/WR
Figure 9.5 System Clock: External Bus Clock = 4:1, External 2-State Access
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Section 9 Bus Controller (BSC)
Divided clock synchronization cycle Tsy I
T1
T2
T3
B
Address
CSn
AS
RD
Read
D15 to D8 D7 to D0
LHWR LLWR
Write
D15 to D8
D7 to D0
BS
RD/WR
Figure 9.6 System Clock: External Bus Clock = 2:1, External 3-State Access
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Section 9 Bus Controller (BSC)
9.5
9.5.1
External Bus
Input/Output Pins
Table 9.2 shows the pin configuration of the bus controller and Table 9.3 shows the pin functions on each interface. Table 9.2
Name Bus cycle start Address strobe/ address hold
Pin Configuration
Symbol BS AS/AH I/O Output Output Function Signal indicating that the bus cycle has started * Strobe signal indicating that the basic bus, byte control SRAM, or burst ROM space is accessed and address output on address bus is enabled Signal to hold the address during access to the address/data multiplexed I/O interface
* Read strobe RD Output
Strobe signal indicating that the basic bus, byte control SRAM, burst ROM, or address/data multiplexed I/O space is being read * * Signal indicating the input or output direction Write enable signal of the SRAM during access to the byte control SRAM space Strobe signal indicating that the basic bus, burst ROM, or address/data multiplexed I/O space is written to, and the upper byte (D15 to D8) of data bus is enabled Strobe signal indicating that the byte control SRAM space is accessed, and the upper byte (D15 to D8) of data bus is enabled Strobe signal indicating that the basic bus, burst ROM, or address/data multiplexed I/O space is written to, and the lower byte (D7 to D0) of data bus is enabled Strobe signal indicating that the byte control SRAM space is accessed, and the lower byte (D7 to D0) of data bus is enabled
Read/write
RD/WR
Output
Low-high write/ lower-upper byte select
LHWR/LUB Output
*
*
Low-low write/ lower-lower byte select
LLWR/LLB
Output
*
*
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Section 9 Bus Controller (BSC)
Name Chip select 0 Chip select 1 Chip select 2 Chip select 3 Chip select 4 Chip select 5 Chip select 6 Chip select 7 Wait Bus request Bus request acknowledge Bus request output
Symbol CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 WAIT BREQ BACK BREQO
I/O Output Output Output Output Output Output Output Output Input Input Output Output
Function Strobe signal indicating that area 0 is selected Strobe signal indicating that area 1 is selected Strobe signal indicating that area 2 is selected Strobe signal indicating that area 3 is selected Strobe signal indicating that area 4 is selected Strobe signal indicating that area 5 is selected Strobe signal indicating that area 6 is selected Strobe signal indicating that area 7 is selected Wait request signal when accessing external address space. Request signal for release of bus to external bus master Acknowledge signal indicating that bus has been released to external bus master External bus request signal used when internal bus master accesses external address space in the external-bus released state Data transfer acknowledge signal for DMAC_3 single address transfer Data transfer acknowledge signal for DMAC_2 single address transfer Data transfer acknowledge signal for DMAC_1 single address transfer Data transfer acknowledge signal for DMAC_0 single address transfer Data transfer acknowledge signal for EXDMAC_1 single address transfer Data transfer acknowledge signal for EXDMAC_0 single address transfer External bus clock
Data transfer acknowledge 3 (DMAC_3) Data transfer acknowledge 2 (DMAC_2) Data transfer acknowledge 1 (DMAC_1) Data transfer acknowledge 0 (DMAC_0) Data transfer acknowledge 1 (EXDMAC_1) Data transfer acknowledge 0 (EXDMAC_0) External bus clock
DACK3
Output
DACK2
Output
DACK1
Output
DACK0
Output
EDACK1
Output
EDACK0
Output
B
Output
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Section 9 Bus Controller (BSC)
Table 9.3
Pin Functions in Each Interface
Byte Control SRAM 16 O O O O O O O O O O O O O O O O
Address/Data
Initial State
Single-
Basic Bus 16 O O O O O O O O O O O O O O O O 8 O O O O O O O O O O O O O O O
Burst ROM 16 O O O O O O O O O O 8 O O O O O O O O O
Multiplexed I/O
Pin Name B CS0 CS1 CS2 CS3 CS4 CS5 CS6 CS7 BS RD/WR AS AH RD LHWR/LUB LLWR/LLB WAIT
16
8
Chip
16 O O O O O O O O O O O O O
8 O O O O O O O O O O O O
Remarks
Output Output Output Output
Output Output
Output Output Output Output Output Output
Controlled by WAITE
[Legend] O: Used as a bus control signal : Not used as a bus control signal (used as a port input when initialized)
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Section 9 Bus Controller (BSC)
9.5.2
Area Division
The bus controller divides the 16-Mbyte address space into eight areas, and performs bus control for the external address space in area units. Chip select signals (CS0 to CS7) can be output for each area. Figure 9.7 shows an area division of the 16-Mbyte address space. For details on address map, see section 3, MCU Operating Modes.
H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (8 Mbytes) H'BFFFFF H'C00000 Area 3 (2 Mbytes) H'DFFFFF H'E00000 Area 4 (1 Mbyte) H'EFFFFF H'F00000 Area 5 (1 Mbyte - 8 kbytes) H'FFDFFF H'FFE000 Area 6 H'FFFEFF (8 kbytes - 256 bytes) H'FFFF00 Area 7 (256 bytes) H'FFFFFF 16-Mbyte space
Figure 9.7 Address Space Area Division
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Section 9 Bus Controller (BSC)
9.5.3
Chip Select Signals
This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when the corresponding external address space area is accessed. Figure 9.8 shows an example of CSn (n = 0 to 7) signal output timing. Enabling or disabling of CSn signal output is set by the port function control register (PFCR). For details, see section 13.3, Port Function Controller. In on-chip ROM disabled extended mode, pin CS0 is placed in the output state after a reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding PFCR bits should be set to 1 when outputting signals CS1 to CS7. In on-chip ROM enabled extended mode, pins CS0 to CS7 are all placed in the input state after a reset and so the corresponding PFCR bits should be set to 1 when outputting signals CS0 to CS7. The PFCR can specify multiple CS outputs for a pin. If multiple CSn outputs are specified for a single pin by the PFCR, CS to be output are generated by mixing all the CS signals. In this case, the settings for the external bus interface areas in which the CSn signals are output to a single pin should be the same. Figure 9.9 shows the signal output timing when the CS signals to be output to areas 5 and 6 are output to the same pin.
Bus cycle T1 B Address bus CSn External address of area n T2 T3
Figure 9.8 CSn Signal Output Timing (n = 0 to 7)
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Section 9 Bus Controller (BSC)
Area 5 access B
Area 6 access
CS5 CS6 Output waveform
Address bus
Area 5 access
Area 6 access
Figure 9.9 Timing When CS Signal is Output to the Same Pin 9.5.4 External Bus Interface
The type of the external bus interfaces, bus width, endian format, number of access cycles, and strobe assert/negate timings can be set for each area in the external address space. The bus width and the number of access cycles for both on-chip memory and internal I/O registers are fixed, and are not affected by the external bus settings. (1) Type of External Bus Interface
Four types of external bus interfaces are provided and can be selected in area units. Table 9.4 shows each interface name, description, area name to be set for each interface. Table 9.5 shows the areas that can be specified for each interface. The initial state of each area is a basic bus interface. Table 9.4
Interface Basic interface Byte control SRAM interface Burst ROM interface Address/data multiplexed I/O interface
Interface Names and Area Names
Description Directly connected to ROM and RAM Directly connected to byte SRAM with byte control pin Directly connected to the ROM that allows page access Directly connected to the peripheral LSI that requires address and data multiplexing Area Name Basic bus space Byte control SRAM space Burst ROM space Address/data multiplexed I/O space
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Section 9 Bus Controller (BSC)
Table 9.5
Areas Specifiable for Each Interface
Related Registers SRAMCR Areas 0 O O BROMCR MPXCR O 1 O O O 2 O O 3 O O O 4 O O O 5 O O O 6 O O O 7 O O O
Interface Basic interface Byte control SRAM interface Burst ROM interface Address/data multiplexed I/O interface
(2)
Bus Width
A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space and an area for which a 16-bit bus is selected functions as a 16-bit access space. In addition, the bus width of address/data multiplexed I/O space is 8 bits or 16 bits, and the bus width for the byte control SRAM space is 16 bits. The initial state of the bus width is specified by the operating mode. If all areas are designated as 8-bit access space, 8-bit bus mode is set; if any area is designated as 16-bit access space, 16-bit bus mode is set. (3) Endian Format
Though the endian format of this LSI is big endian, data can be converted into little endian format when reading or writing to the external address space. Areas 7 to 2 can be specified as either big endian or little endian format by the LE7 to LE2 bits in ENDIANCR. The initial state of each area is the big endian format. Note that the data format for the areas used as a program area or a stack area should be big endian.
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Section 9 Bus Controller (BSC)
(4) (a)
Number of Access Cycles Basic Bus Interface
The number of access cycles in the basic bus interface can be specified as two or three cycles by the ASTCR. An area specified as 2-state access is specified as 2-state access space; an area specified as 3-state access is specified as 3-state access space. For the 2-state access space, a wait cycle insertion is disabled. For the 3-state access space, a program wait (0 to 7 cycles) specified by WTCRA and WTCRB or an external wait by WAIT can be inserted. Assertion period of the chip select signal can be extended by CSACR.
Number of access cycles in the basic bus interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of CS extension cycles (0, 1, 2) [+ number of external wait cycles by the WAIT pin]
(b)
Byte Control SRAM Interface
The number of access cycles in the byte control SRAM interface is the same as that in the basic bus interface.
Number of access cycles in byte control SRAM interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of CS extension cycles (0, 1, 2) [+ number of external wait cycles by the WAIT pin]
(c)
Burst ROM Interface
The number of access cycles at full access in the burst ROM interface is the same as that in the basic bus interface. The number of access cycles in the burst access can be specified as one to eight cycles by the BSTS bit in BROMCR.
Number of access cycles in the burst ROM interface = number of basic cycles (2, 3) + number of program wait cycles (0 to 7) + number of CS extension cycles (0, 1) [+number of external wait cycles by the WAIT pin] + number of burst access cycles (1 to 8) x number of burst accesses (0 to 63)
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Section 9 Bus Controller (BSC)
(d)
Address/data multiplexed I/O interface
The number of access cycles in data cycle of the address/data multiplexed I/O interface is the same as that in the basic bus interface. The number of access cycles in address cycle can be specified as two or three cycles by the ADDEX bit in MPXCR.
Number of access cycles in the address/data multiplexed I/O interface = number of address output cycles (2, 3) + number of data output cycles (2, 3) + number of program wait cycles (0 to 7) + number of CS extension cycles (0, 1, 2) [+number of external wait cycles by the WAIT pin]
Table 9.6 lists the number of access cycles for each interface. Table 9.6
Basic bus interface
Number of Access Cycles
= = Th [0,1] Th [0,1] Th [0,1] Th [0,1] Th [0,1] Th [0,1] +Th [0,1] +Th [0,1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T1 [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +T2 [1] +Tt [0,1] +Tt [0,1] +Tt [0,1] +Tt [0,1] +Tb [(1 to 8) x m] +Tb [(1 to 8) x m] +Tt [0,1] +Tt [0,1]
[2 to 4] [3 to 12 + n] [2 to 4] [3 to 12 + n] [(2 to 3) + (1 to 8) x m] [(2 to 11 + n) + (1 to 8) x m] [4 to 7] [5 to 15 + n]
+Tpw +Ttw [0 to 7] [n]
+T3 [1]
Byte control SRAM interface
= =
+Tpw +Ttw [0 to 7] [n]
+T3 [1]
Burst ROM interface
= =
+Tpw +Ttw [0 to 7] [n]
+T3 [1]
Address/data multiplexed I/O interface
= Tma [2,3] = Tma [2,3]
+Tpw +Ttw [0 to 7] [n]
+T3 [1]
[Legend] Numbers: Number of access cycles n: Pin wait (0 to ) m: Number of burst accesses (0 to 63)
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Section 9 Bus Controller (BSC)
(5)
Strobe Assert/Negate Timings
The assert and negate timings of the strobe signals can be modified as well as number of access cycles. * * * * Read strobe (RD) in the basic bus interface Chip select assertion period extension cycles in the basic bus interface Data transfer acknowledge (DACK3 to DACK0) output for DMAC single address transfers Data transfer acknowledge (EDACK1 and EDACK0) output for EXDMAC single address transfers Area and External Bus Interface Area 0
9.5.5 (1)
Area 0 includes on-chip ROM. All of area 0 is used as external address space in on-chip ROM disabled extended mode, and the space excluding on-chip ROM is external address space in onchip ROM enabled extended mode. When area 0 external address space is accessed, the CS0 signal can be output. Either of the basic bus interface, byte control SRAM interface, or burst ROM interface can be selected for area 0 by bit BSRM0 in BROMCR and bit BCSEL0 in SRAMCR. Table 9.7 shows the external interface of area 0. Table 9.7 Area 0 External Interface
Register Setting Interface Basic bus interface Byte control SRAM interface Burst ROM interface Setting prohibited BSRM0 of BROMCR 0 0 1 1 BCSEL0 of SRAMCR 0 1 0 1
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Section 9 Bus Controller (BSC)
(2)
Area 1
In externally extended mode, all of area 1 is external address space. In on-chip ROM enabled extended mode, the space excluding on-chip ROM is external address space. When area 1 external address space is accessed, the CS1 signal can be output. Either of the basic bus interface, byte control SRAM, or burst ROM interface can be selected for area 1 by bit BSRM1 in BROMCR and bit BCSEL1 in SRAMCR. Table 9.8 shows the external interface of area 1. Table 9.8 Area 1 External Interface
Register Setting Interface Basic bus interface Byte control SRAM interface Burst ROM interface Setting prohibited BSRM1 of BROMCR 0 0 1 1 BCSEL1 of SRAMCR 0 1 0 1
(3)
Area 2
In externally extended mode, all of area 2 is external address space. When area 2 external address space is accessed, the CS2 signal can be output. Either the basic bus interface or byte control SRAM interface can be selected for area 2 by bit BCSEL2 in SRAMCR. Table 9.9 shows the external interface of area 2. Table 9.9 Area 2 External Interface
Register Setting Interface Basic bus interface Byte control SRAM interface BCSEL2 of SRAMCR 0 1
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Section 9 Bus Controller (BSC)
(4)
Area 3
In externally extended mode, all of area 3 is external address space. When area 3 external address space is accessed, the CS3 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 3 by bit MPXE3 in MPXCR and bit BCSEL3 in SRAMCR. Table 9.10 shows the external interface of area 3. Table 9.10 Area 3 External Interface
Register Setting Interface Basic bus interface Byte control SRAM interface Address/data multiplexed I/O interface Setting prohibited MPXE3 of MPXCR 0 0 1 1 BCSEL3 of SRAMCR 0 1 0 1
(5)
Area 4
In externally extended mode, all of area 4 is external address space. When area 4 external address space is accessed, the CS4 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 4 by bit MPXE4 in MPXCR and bit BCSEL4 in SRAMCR. Table 9.11 shows the external interface of area 4. Table 9.11 Area 4 External Interface
Register Setting Interface Basic bus interface Byte control SRAM interface Address/data multiplexed I/O interface Setting prohibited MPXE4 of MPXCR 0 0 1 1 BCSEL4 of SRAMCR 0 1 0 1
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Section 9 Bus Controller (BSC)
(6)
Area 5
Area 5 includes the on-chip RAM and access prohibited spaces. In external extended mode, area 5, other than the on-chip RAM and access prohibited spaces, is external address space. Note that the on-chip RAM is enabled when the RAME bit in SYSCR are set to 1. If the RAME bit in SYSCR is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are an external address space. For details, see section 3, MCU Operating Modes. When area 5 external address space is accessed, the CS5 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 5 by the MPXE5 bit in MPXCR and the BCSEL5 bit in SRAMCR. Table 9.12 shows the external interface of area 5. Table 9.12 Area 5 External Interface
Register Setting Interface Basic bus interface Byte control SRAM interface Address/data multiplexed I/O interface Setting prohibited MPXE5 of MPXCR 0 0 1 1 BCSEL5 of SRAMCR 0 1 0 1
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Section 9 Bus Controller (BSC)
(7)
Area 6
Area 6 includes internal I/O registers. In external extended mode, area 6 other than on-chip I/O register area is external address space. When area 6 external address space is accessed, the CS6 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 6 by the MPXE6 bit in MPXCR and the BCSEL6 bit in SRAMCR. Table 9.13 shows the external interface of area 6. Table 9.13 Area 6 External Interface
Register Setting Interface Basic bus interface Byte control SRAM interface Address/data multiplexed I/O interface Setting prohibited MPXE6 of MPXCR 0 0 1 1 BCSEL6 of SRAMCR 0 1 0 1
(8)
Area 7
Area 7 includes internal I/O registers. In external extended mode, area 7 other than internal I/O register area is external address space. When area 7 external address space is accessed, the CS7 signal can be output. Either of the basic bus interface, byte control SRAM interface, or address/data multiplexed I/O interface can be selected for area 7 by the MPXE7 bit in MPXCR and the BCSEL7 bit in SRAMCR. Table 9.14 shows the external interface of area 7. Table 9.14 Area 7 External Interface
Register Setting Interface Basic bus interface Byte control SRAM interface Address/data multiplexed I/O interface Setting prohibited MPXE7 of MPXCR 0 0 1 1 BCSEL7 of SRAMCR 0 1 0 1
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Section 9 Bus Controller (BSC)
9.5.6
Endian and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space), the data size, and endian format when accessing external address space. (1) 8-Bit Access Space
With the 8-bit access space, the lower byte data bus (D7 to D0) is always used for access. The amount of data that can be accessed at one time is one byte: a word access is performed as two byte accesses, and a longword access, as four byte accesses. Figures 8.10 and 8.11 illustrate data alignment control for the 8-bit access space. Figure 9.10 shows the data alignment when the data endian format is specified as big endian. Figure 9.11 shows the data alignment when the data endian format is specified as little endian.
Strobe signal LHWR/LUB RD LLWR/LLB
Data Size Byte Word
Access Address
n
Access Count 1
Bus Cycle 1st 1st
Data Size Byte Byte Byte Byte Byte Byte Byte
D15
Data bus D8 D7
7 15
D0
0
8 0 24 16
n
n
2 2nd
7
31
Longword
4
1st 2nd 3rd 4th
23 15 7
8 0
Figure 9.10 Access Sizes and Data Alignment Control for 8-Bit Access Space (Big Endian)
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Section 9 Bus Controller (BSC)
Strobe signal LHWR/LUB RD LLWR/LLB
Data Size Byte Word
Access Address
n n n
Access Count 1 2
Bus Cycle 1st 1st 2nd
Data Size Byte Byte Byte Byte Byte Byte Byte
D15
Data bus D8 D7
7 7
D0
0 0 8 0 8
15
7
Longword
4
1st 2nd 3rd 4th
15 23 31
16 24
Figure 9.11 Access Sizes and Data Alignment Control for 8-Bit Access Space (Little Endian) (2) 16-Bit Access Space
With the 16-bit access space, the upper byte data bus (D15 to D8) and lower byte data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word. Figures 8.12 and 8.13 illustrate data alignment control for the 16-bit access space. Figure 9.12 shows the data alignment when the data endian format is specified as big endian. Figure 9.13 shows the data alignment when the data endian format is specified as little endian. In big endian, byte access for an even address is performed by using the upper byte data bus and byte access for an odd address is performed by using the lower byte data bus. In little endian, byte access for an even address is performed by using the lower byte data bus, and byte access for an odd address is performed by using the third byte data bus.
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Section 9 Bus Controller (BSC)
Strobe signal LHWR/LUB LLWR/LLB
RD
Access Size Byte
Word
Access Address Even (2n) Odd (2n+1) Even (2n) Odd (2n+1)
Access Count 1 1 1 2
Bus Cycle 1st 1st 1st 1st 2nd
Data Size Byte Byte Word Byte Byte Word Word Byte Word Byte
D15
7
Data bus D8 D7
0
D0
7
15
87
0
0
15
7
0
8
Longword
Even (2n) Odd (2n+1)
2
1st 2nd
31
24 23
16
15
87
0 24
8
3
1st 2nd 3rd
31
23 16 15 0
7
Figure 9.12 Access Sizes and Data Alignment Control for 16-Bit Access Space (Big Endian)
Strobe signal LHWR/LUB LLWR/LLB
RD
Access Size Byte
Word
Access Address Even (2n) Odd (2n+1) Even (2n)
Odd (2n+1)
Access Count 1 1 1 2
Bus Cycle 1st 1st 1st 1st 2nd
Data Size Byte Byte Word Byte Byte Word Word Byte Word Byte
D15
Data bus D8 D7
7
D0
0
7
15
0
87
0
7
0
15
15
31 87
24 23
8
Longword
Even (2n) Odd (2n+1)
2
1st 2nd
0
16
3
1st 2nd 3rd
7
23
0 16 15
8 24
31
Figure 9.13 Access Sizes and Data Alignment Control for 16-Bit Access Space (Little Endian)
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Section 9 Bus Controller (BSC)
9.6
Basic Bus Interface
The basic bus interface can be connected directly to the ROM and SRAM. The bus specifications can be specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, CSACR, and ENDIANCR. 9.6.1 Data Bus
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and controls whether the upper byte data bus (D15 to D8) or lower byte data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space), the data size, and endian format when accessing external address space,. For details, see section 9.5.6, Endian and Data Alignment. 9.6.2 I/O Pins Used for Basic Bus Interface
Table 9.15 shows the pins used for basic bus interface. Table 9.15 I/O Pins for Basic Bus Interface
Name Bus cycle start Address strobe Read strobe Read/write Low-high write Low-low write Chip select 0 to 7 Wait Note: * Symbol BS AS* RD RD/WR LHWR LLWR I/O Output Output Output Output Output Output Function Signal indicating that the bus cycle has started Strobe signal indicating that an address output on the address bus is valid during access Strobe signal indicating the read access Signal indicating the data bus input or output direction Strobe signal indicating that the upper byte (D15 to D8) is valid during write access Strobe signal indicating that the lower byte (D7 to D0) is valid during write access Strobe signal indicating that the area is selected Wait request signal used when an external address space is accessed
CS0 to CS7 Output WAIT Input
When the address/data multiplexed I/O is selected, this pin only functions as the AH output and does not function as the AS output.
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Section 9 Bus Controller (BSC)
9.6.3
Basic Timing
This section describes the basic timing when the data is specified as big endian. (1) 16-Bit 2-State Access Space
Figures 8.14 to 8.16 show the bus timing of 16-bit 2-state access space. When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even addresses access, and the lower byte data bus (D7 to D0) is used for odd addresses. No wait cycles can be inserted.
Bus cycle
T1
B
T2
Address
CSn AS RD
Read
D15 to D8 D7 to D0 LHWR LLWR
Valid Invalid
High level Valid
Write
D15 to D8
D7 to D0
BS RD/WR
DACK or EDACK
High-Z
Notes: 1. n = 0 to 7 2. When RDNn = 0 3. When DKC, EDKC = 0
Figure 9.14 16-Bit 2-State Access Space Bus Timing (Byte Access for Even Address)
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Section 9 Bus Controller (BSC)
Bus cycle T1 B Address CSn AS RD Read D15 to D8 D7 to D0 Invalid T2
Valid
LHWR LLWR D15 to D8 D7 to D0
High level
Write
High-Z Valid
BS RD/WR DACK or EDACK
Notes: 1. n = 0 to 7 2. When RDNn = 0 3. When DKC, EDKC = 0
Figure 9.15 16-Bit 2-State Access Space Bus Timing (Byte Access for Odd Address)
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Section 9 Bus Controller (BSC)
Bus cycle
T1
B
T2
Address CSn AS RD Read D15 to D8 D7 to D0
Valid
Valid
LHWR LLWR Write D15 to D8 D7 to D0
Valid
Valid
BS
RD/WR
DACK or EDACK
Notes: 1. n = 0 to 7 2. When RDNn = 0 3. When DKC, EDKC= 0
Figure 9.16 16-Bit 2-State Access Space Bus Timing (Word Access for Even Address)
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Section 9 Bus Controller (BSC)
(2)
16-Bit 3-State Access Space
Figures 8.17 to 8.19 show the bus timing of 16-bit 3-state access space. When accessing 16-bit access space, the upper byte data bus (D15 to D8) is used for even addresses, and the lower byte data bus (D7 to D0) is used for odd addresses. Wait cycles can be inserted.
Bus cycle
T1
B
T2
T3
Address CSn AS RD
Read
D15 to D8 D7 to D0 LHWR LLWR High level D15 to D8 D7 to D0 High-Z
BS RD/WR Valid
Valid
Invalid
Write
DACK or EDACK
Notes: 1. n = 0 to 7 2. When RDNn = 0 3. When DKC, EDKC= 0
Figure 9.17 16-Bit 3-State Access Space Bus Timing (Byte Access for Even Address)
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Section 9 Bus Controller (BSC)
Bus cycle T1 B T2 T3
Address CSn AS RD Read D15 to D8 D7 to D0 LHWR High level Write LLWR Invalid Valid
D15 to D8 D7 to D0
High-Z Valid
BS RD/WR
DACK or EDACK
Notes: 1. n = 0 to 7 2. When RDNn = 0 3. When DKC, EDKC= 0
Figure 9.18 16-Bit 3-State Access Space Bus Timing (Word Access for Odd Address)
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Section 9 Bus Controller (BSC)
Bus cycle T1 B T2 T3
Address CSn AS RD Read D15 to D8 D7 to D0 LHWR LLWR Write D15 to D8 D7 to D0 Valid Valid Valid Valid
BS
RD/WR DACK or EDACK
Notes: 1. n = 0 to 7 2. When RDNn = 0 3. When DKC, EDKC= 0
Figure 9.19 16-Bit 3-State Access Space Bus Timing (Word Access for Even Address)
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Section 9 Bus Controller (BSC)
9.6.4
Wait Control
This LSI can extend the bus cycle by inserting wait cycles (Tw) when the external address space is accessed. There are two ways of inserting wait cycles: program wait (Tpw) insertion and pin wait (Ttw) insertion using the WAIT pin. (1) Program Wait Insertion
From 0 to 7 wait cycles can be inserted automatically between the T2 state and T3 state for 3-state access space, according to the settings in WTCRA and WTCRB. (2) Pin Wait Insertion
For 3-state access space, when the WAITE bit in BCR1 is set to 1 and the corresponding ICR bit is set to 1, wait input by means of the WAIT pin is enabled. When the external address space is accessed in this state, a program wait (Tpw) is first inserted according to the WTCRA and WTCRB settings. If the WAIT pin is low at the falling edge of B in the last T2 or Tpw cycle, another Ttw cycle is inserted until the WAIT pin is brought high. The pin wait insertion is effective when the Tw cycles are inserted to seven cycles or more, or when the number of Tw cycles to be inserted is changed according to the external devices. The WAITE bit is common to all areas. For details on ICR, see section 13, I/O Ports.
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Section 9 Bus Controller (BSC)
Figure 9.20 shows an example of wait cycle insertion timing. After a reset, the 3-state access is specified, the program wait is inserted for seven cycles, and the WAIT input is disabled.
Wait by program Wait by WAIT pin wait Tpw Ttw Ttw
T1 B
T2
T3
WAIT
Address
CSn
AS
RD
Read
Data bus
Read data
LHWR, LLWR
Write Data bus Write data
BS
RD/WR
Notes: 1. Upward arrows indicate the timing of WAIT pin sampling. 2. n = 0 to 7 3. When RDNn = 0
Figure 9.20 Example of Wait Cycle Insertion Timing
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Section 9 Bus Controller (BSC)
9.6.5
Read Strobe (RD) Timing
The read strobe timing can be modified in area units by setting bits RDN7 to RDN0 in RDNCR to 1. Note that the RD timing with respect to the DACK or EDACK rising edge will change if the read strobe timing is modified by setting RDNn to 1 when the DMAC or EXDMAC is used in the single address mode. Figure 9.21 shows an example of timing when the read strobe timing is changed in the basic bus 3state access space.
Bus cycle T1 T2 T3
B Address bus
CSn AS RD RDNn = 0 Data bus RD RDNn = 1 Data bus BS RD/WR
DACK or EDACK Notes: 1. n = 0 to 7 2. When DKC, EDKC = 0
Figure 9.21 Example of Read Strobe Timing
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Section 9 Bus Controller (BSC)
9.6.6
Extension of Chip Select (CS) Assertion Period
Some external I/O devices require a setup time and hold time between address and CS signals and strobe signals such as RD, LHWR, and LLWR. Settings can be made in CSACR to insert cycles in which only the CS, AS, and address signals are asserted before and after a basic bus space access cycle. Extension of the CS assertion period can be set in area units. With the CS assertion extension period in write access, the data setup and hold times are less stringent since the write data is output to the data bus. Figure 9.22 shows an example of the timing when the CS assertion period is extended in basic bus 3-state access space. Both extension cycle Th inserted before the basic bus cycle and extension cycle Tt inserted after the basic bus cycle, or only one of these, can be specified for individual areas. Insertion or noninsertion can be specified for the Th cycle with the upper eight bits (CSXH7 to CSXH0) in CSACR, and for the Tt cycle with the lower eight bits (CSXT7 to CSXT0).
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Section 9 Bus Controller (BSC)
Bus cycle Th
B
T1
T2
T3
Tt
Address
CSn
AS RD
Read
Data bus
LHWR, LLWR
Write Data bus Write data
Read data
BS RD/WR
DACK or EDACK Notes: 1. n = 0 to 7 2. When DKC, EDKC = 0
Figure 9.22 Example of Timing when Chip Select Assertion Period is Extended
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Section 9 Bus Controller (BSC)
9.6.7
DACK and EDACK Signal Output Timings
For DMAC or EXDMAC single address transfers, the DACK or EDACK signal assert timing can be modified by using the DKC or EDKC bit in BCR1. Figure 9.23 shows the DACK and EDACK signal output timings. Setting the DKC or EDKC bit to 1 asserts the DACK or EDACK signal a half cycle earlier.
Bus cycle T1 T2
B Address bus
CSn AS RD Read Data bus Read data
LHWR, LLWR Write Data bus BS RD/WR Write data
DKC, EDCK = 0 DACK or EDACK DKC, EDCK = 1
Notes: 1. n = 7 to 0 2. RDNn = 0
Figure 9.23 DACK and EDACK Signal Output Timings
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Section 9 Bus Controller (BSC)
9.7
Byte Control SRAM Interface
The byte control SRAM interface is a memory interface for outputting a byte select strobe during a read or a write bus cycle. This interface has 16-bit data input/output pins and can be connected to the SRAM that has the upper byte select and the lower byte select strobes such as UB and LB. The operation of the byte control SRAM interface is the same as the basic bus interface except that: the byte select strobes (LUB and LLB) are output from the write strobe output pins (LHWR and LLWR), respectively; the read strobe (RD) negation timing is a half cycle earlier than that in the case where RDNn = 0 in the basic bus interface regardless of the RDNCR settings; and the RD/WR signal is used as write enable. 9.7.1 Byte Control SRAM Space Setting
Byte control SRAM interface can be specified for areas 0 to 7. Each area can be specified as byte control SRAM interface by setting bits BCSELn (n = 0 to 7) in SRAMCR. For the area specified as burst ROM interface or address/data multiplexed I/O interface, the SRAMCR setting is invalid and byte control SRAM interface cannot be used. 9.7.2 Data Bus
The bus width of the byte control SRAM space can be specified as 16-bit byte control SRAM space according to bits ABWHn and ABWLn (n = 0 to 7) in ABWCR. The area specified as 8-bit access space cannot be specified as the byte control SRAM space. For the 16-bit byte control SRAM space, data bus (D15 to D0) is valid. Access size and data alignment are the same as the basic bus interface. For details, see section 9.5.6, Endian and Data Alignment.
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Section 9 Bus Controller (BSC)
9.7.3
I/O Pins Used for Byte Control SRAM Interface
Table 9.16 shows the pins used for the byte control SRAM interface. In the byte control SRAM interface, write strobe signals (LHWR and LLWR) are output from the byte select strobes. The RD/WR signal is used as a write enable signal. Table 9.16 I/O Pins for Byte Control SRAM Interface
Pin AS/AH When Byte Control SRAM is Specified AS Name Address strobe I/O Output Function Strobe signal indicating that the address output on the address bus is valid when a basic bus interface space or byte control SRAM space is accessed Strobe signal indicating that area n is selected Output enable for the SRAM when the byte control SRAM space is accessed Write enable signal for the SRAM when the byte control SRAM space is accessed Upper byte select when the 16-bit byte control SRAM space is accessed Lower byte select when the 16-bit byte control SRAM space is accessed Wait request signal used when an external address space is accessed Address output pin Data input/output pin
CSn RD RD/WR LHWR/LUB LLWR/LLB WAIT A20 to A0 D15 to D0
CSn RD RD/WR LUB LLB WAIT A20 to A0 D15 to D0
Chip select Read strobe Read/write Lower-upper byte select Lower-lower byte select Wait Address pin Data pin
Output Output Output Output Output Input Output Input/ output
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Section 9 Bus Controller (BSC)
9.7.4 (1)
Basic Timing 2-State Access Space
Figure 9.24 shows the bus timing when the byte control SRAM space is specified as a 2-state access space. Data buses used for 16-bit access space is the same as those in basic bus interface. No wait cycles can be inserted.
Bus cycle
T1 B Address
T2
CSn AS LUB LLB RD/WR RD D15 to D8 D7 to D0 Valid Valid
Read
RD/WR Write RD D15 to D8 D7 to D0 BS DACK or EDACK Note: n = 0 to 7 High level Valid Valid
Figure 9.24 16-Bit 2-State Access Space Bus Timing
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Section 9 Bus Controller (BSC)
(2)
3-State Access Space
Figure 9.25 shows the bus timing when the byte control SRAM space is specified as a 3-state access space. Data buses used for 16-bit access space is the same as those in the basic bus interface. Wait cycles can be inserted.
Bus cycle T2
T1 B Address CSn AS LUB LLB RD/WR RD Read D15 to D8 D7 to D0
T3
Valid Valid
RD/WR RD D15 to D8 D7 to D0 High level Valid Valid
Write
BS DACK or EDACK Note: n = 0 to 7
Figure 9.25 16-Bit 3-State Access Space Bus Timing
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Section 9 Bus Controller (BSC)
9.7.5
Wait Control
The bus cycle can be extended for the byte control SRAM interface by inserting wait cycles (Tw) in the same way as the basic bus interface. (1) Program Wait Insertion
From 0 to 7 wait cycles can be inserted automatically between T2 cycle and T3 cycle for the 3state access space in area units, according to the settings in WTCRA and WTCRB. (2) Pin Wait Insertion
For 3-state access space, when the WAITE bit in BCR1 is set to 1, the corresponding DDR bit is cleared to 0, and the ICR bit is set to 1, wait input by means of the WAIT pin is enabled. For details on DDR and ICR, see section 13, I/O Ports. Figure 9.26 shows an example of wait cycle insertion timing.
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Section 9 Bus Controller (BSC)
Wait by program wait T1 B T2 Tpw
Wait by WAIT pin Ttw Ttw T3
WAIT
Address
CSn
AS
LUB, LLB RD/WR
Read
RD
Data bus RD/WR RD Data bus
Read data
Write
High level Write data
BS
DACK or EDACK
Notes: 1. Upward arrows indicate the timing of WAIT pin sampling. 2. n = 0 to 7
Figure 9.26 Example of Wait Cycle Insertion Timing
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Section 9 Bus Controller (BSC)
9.7.6
Read Strobe (RD)
When the byte control SRAM space is specified, the RDNCR setting for the corresponding space is invalid. The read strobe negation timing is the same timing as when RDNn = 1 in the basic bus interface. Note that the RD timing with respect to the DACK or EDACK rising edge becomes different. 9.7.7 Extension of Chip Select (CS) Assertion Period
In the byte control SRAM interface, the extension cycles can be inserted before and after the bus cycle in the same way as the basic bus interface. For details, see section 9.6.6, Extension of Chip Select (CS) Assertion Period. 9.7.8 DACK and EDACK Signal Output Timings
For DMAC or EXDMAC single address transfers, the DACK or EDACK signal assert timing can be modified by using the DKC or EDKC bit in BCR1. Figure 9.27 shows the DACK and EDACK signal output timings. Setting the DKC or EDKC bit to 1 asserts the DACK or EDACK signal a half cycle earlier.
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Section 9 Bus Controller (BSC)
Bus cycle
T1 T2
B Address
CSn AS LUB LLB
RD/WR RD Read Valid Valid
D15 to D8 D7 to D0
RD/WR RD Write
High level
Valid
Valid
D15 to D8 D7 to D0
BS
DKC, EDKC = 0
DACK or EDACK
DKC, EDKC = 1
Figure 9.27 DACK and EDACK Signal Output Timings
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Section 9 Bus Controller (BSC)
9.8
Burst ROM Interface
In this LSI, external address space areas 0 and 1 can be designated as burst ROM space, and burst ROM interfacing performed. The burst ROM interface enables ROM with page access capability to be accessed at high speed. Areas 1 and 0 can be designated as burst ROM space by means of bits BSRM1 and BSRM0 in BROMCR. Consecutive burst accesses of up to 32 words can be performed, according to the setting of bits BSWDn1 and BSWDn0 (n = 0, 1) in BROMCR. From one to eight cycles can be selected for burst access. Settings can be made independently for area 0 and area 1. In the burst ROM interface, the burst access covers only CPU read accesses and cluster transfer read accesses of EXDMAC. Other accesses are performed with the similar method to the basic bus interface. 9.8.1 Burst ROM Space Setting
Burst ROM interface can be specified for areas 0 and 1. Areas 0 and 1 can be specified as burst ROM space by setting bits BSRMn (n = 0, 1) in BROMCR. 9.8.2 Data Bus
The bus width of the burst ROM space can be specified as 8-bit or 16-bit burst ROM interface space according to the ABWHn and ABWLn bits (n = 0, 1) in ABWCR. For the 8-bit bus width, data bus (D7 to D0) is valid. For the 16-bit bus width, data bus (D15 to D0) is valid. Access size and data alignment are the same as the basic bus interface. For details, see section 9.5.6, Endian and Data Alignment.
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Section 9 Bus Controller (BSC)
9.8.3
I/O Pins Used for Burst ROM Interface
Table 9.17 shows the pins used for the burst ROM interface. Table 9.17 I/O Pins Used for Burst ROM Interface
Name Bus cycle start Address strobe Read strobe Read/write Low-high write Low-low write Chip select 0 to 7 Wait Symbol BS AS RD RD/WR LHWR LLWR I/O Output Output Output Output Output Output Function Signal indicating that the bus cycle has started. Strobe signal indicating that an address output on the address bus is valid during access Strobe signal indicating the read access Signal indicating the data bus input or output direction Strobe signal indicating that the upper byte (D15 to D8) is valid during write access Strobe signal indicating that the lower byte (D7 to D0) is valid during write access Strobe signal indicating that the area is selected Wait request signal used when an external address space is accessed
CS0 to CS7 Output WAIT Input
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Section 9 Bus Controller (BSC)
9.8.4
Basic Timing
The number of access cycles in the initial cycle (full access) on the burst ROM interface is determined by the basic bus interface settings in ABWCR, ASTCR, WTCRA, WTCRB, and bits CSXHn in CSACR (n = 0 to 7). When area 0 or area 1 designated as burst ROM space, the settings in RDNCR and bits CSXTn in CSACR (n = 0 to 7) are ignored during read accesses by the CPU and EXDMAC cluster transfer. From one to eight cycles can be selected for the burst cycle, according to the settings of bits BSTS02 to BSTS00 and BSTS12 to BSTS10 in BROMCR. Wait cycles cannot be inserted. In addition, 4-word, 8-word, 16-word, or 32-word consecutive burst access can be performed according to the settings of BSTS01, BSTS00, BSTS11, and BSTS10 bits in BROMCR. The basic access timing for burst ROM space is shown in figures 8.28 and 8.29.
Full access Burst access T3
T1
B Upper address bus Lower address bus
CSn
T2
T1
T2
T1
T2
AS
RD
Data bus
BS
RD/WR
Note: n = 1, 0
Figure 9.28 Example of Burst ROM Access Timing (ASTn = 1, Two Burst Cycles)
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Section 9 Bus Controller (BSC)
Full access
Burst access
T1
T2
T1
T1
B Upper address bus
Lower address bus
CSn
AS
RD
Data bus
BS
RD/WR
Note: n = 1, 0
Figure 9.29 Example of Burst ROM Access Timing (ASTn = 0, One Burst Cycle)
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Section 9 Bus Controller (BSC)
9.8.5
Wait Control
As with the basic bus interface, either program wait insertion or pin wait insertion by the WAIT pin can be used in the initial cycle (full access) on the burst ROM interface. See section 9.6.4, Wait Control. Wait cycles cannot be inserted in a burst cycle. 9.8.6 Read Strobe (RD) Timing
In the burst ROM space, the RDNCR setting for the corresponding space is invalid during read accesses by the CPU or EXDMAC cluster transfer. The read strobe negation timing is the same timing as when RDNn = 0 in the basic bus interface. 9.8.7 Extension of Chip Select (CS) Assertion Period
In the burst ROM interface, the extension cycles can be inserted in the same way as the basic bus interface. For the burst ROM space, the burst access can be enabled only during read accesses by the CPU or EXDMAC cluster transfer. In this case, the setting of the corresponding CSXTn bit in CSACR is ignored and an extension cycle can be inserted only before the full access cycle. Note that no extension cycle can be inserted before or after the burst access cycles. For accesses except read accesses by the CPU or EXDMAC cluster transfer, the burst ROM space is equivalent to the basic bus interface space. Accordingly, extension cycles can be inserted before and after the burst access cycles.
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Section 9 Bus Controller (BSC)
9.9
Address/Data Multiplexed I/O Interface
If areas 3 to 7 of external address space are specified as address/data multiplexed I/O space in this LSI, the address/data multiplexed I/O interface can be performed. In the address/data multiplexed I/O interface, peripheral LSIs that require the multiplexed address/data can be connected directly to this LSI. 9.9.1 Address/Data Multiplexed I/O Space Setting
Address/data multiplexed I/O interface can be specified for areas 3 to 7. Each area can be specified as the address/data multiplexed I/O space by setting bits MPXEn (n = 3 to 7) in MPXCR. 9.9.2 Address/Data Multiplex
In the address/data multiplexed I/O space, data bus is multiplexed with address bus. Table 9.18 shows the relationship between the bus width and address output. Table 9.18 Address/Data Multiplex
Data Pins Bus Width 8 bits Cycle Address Data 16 bits Address Data PI7 A15 PI6 A14 PI5 A13 PI4 A12 PI3 A11 PI2 A10 PI1 A9 D9 PI0 A8 D8 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 A7 D7 A7 D7 A6 D6 A6 D6 A5 D5 A5 D5 A4 D4 A4 D4 A3 D3 A3 D3
A2 D2 A2 D2
A1 D1 A1 D1
A0 D0 A0 D0
D15 D14 D13 D12 D11 D10
9.9.3
Data Bus
The bus width of the address/data multiplexed I/O space can be specified for either 8-bit access space or 16-bit access space by the ABWHn and ABWLn bits (n = 3 to 7) in ABWCR. For the 8-bit access space, D7 to D0 are valid for both address and data. For 16-bit access space, D15 to D0 are valid for both address and data. If the address/data multiplexed I/O space is accessed, the corresponding address will be output to the address bus. For details on access size and data alignment, see section 9.5.6, Endian and Data Alignment.
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Section 9 Bus Controller (BSC)
9.9.4
I/O Pins Used for Address/Data Multiplexed I/O Interface
Table 9.19 shows the pins used for the address/data multiplexed I/O Interface. Table 9.19 I/O Pins for Address/Data Multiplexed I/O Interface
When Byte Control SRAM is Specified CSn AH* RD LHWR
Pin CSn AS/AH RD LHWR/LUB
Name Chip select Address hold Read strobe
I/O Output Output Output
Function Chip select (n = 3 to 7) when area n is specified as the address/data multiplexed I/O space Signal to hold an address when the address/data multiplexed I/O space is specified Signal indicating that the address/data multiplexed I/O space is being read Strobe signal indicating that the upper byte (D15 to D8) is valid when the address/data multiplexed I/O space is written Strobe signal indicating that the lower byte (D7 to D0) is valid when the address/data multiplexed I/O space is written Address and data multiplexed pins for the address/data multiplexed I/O space. Only D7 to D0 are valid when the 8-bit space is specified. D15 to D0 are valid when the 16-bit space is specified.
Low-high write Output
LLWR/LLB
LLWR
Low-low write
Output
D15 to D0
D15 to D0
Address/data
Input/ output
A20 to A0 WAIT BS RD/WR
A20 to A0 WAIT BS RD/WR
Address Wait
Output Input
Address output pin Wait request signal used when the external address space is accessed Signal to indicate the bus cycle start Signal indicating the data bus input or output direction
Bus cycle start Output Read/write Output
Note:
*
The AH output is multiplexed with the AS output. At the timing that an area is specified as address/data multiplexed I/O, this pin starts to function as the AH output meaning that this pin cannot be used as the AS output. At this time, when other areas set to the basic bus interface is accessed, this pin does not function as the AS output. Until an area is specified as address/data multiplexed I/O, be aware that this pin functions as the AS output.
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Section 9 Bus Controller (BSC)
9.9.5
Basic Timing
The bus cycle in the address/data multiplexed I/O interface consists of an address cycle and a data cycle. The data cycle is based on the basic bus interface timing specified by the ABWCR, ASTCR, WTCRA, WTCRB, RDNCR, and CSACR. Figures 8.30 and 8.31 show the basic access timings.
Address cycle Tma1 Tma2 T1 Data cycle T2
B Address bus
CSn
AH
RD Read D7 to D0 Address Read data
LLWR Write D7 to D0 Address Write data
BS
RD/WR
DACK or EDACK
Note: n = 3 to 7
Figure 9.30 8-Bit Access Space Access Timing (ABWHn = 1, ABWLn = 1)
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Section 9 Bus Controller (BSC)
Bus cycle Address cycle Tma1 Tma2 T1 Data cycle T2
B Address bus
CSn
AH
RD Read D15 to D0 Address Read data
LHWR
LLWR Write
D15 to D0
Address
Write data
BS
RD/WR
DACK or EDACK
Note: n = 3 to 7
Figure 9.31 16-Bit Access Space Access Timing (ABWHn = 0, ABWLn = 1)
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Section 9 Bus Controller (BSC)
9.9.6
Address Cycle Control
An extension cycle (Tmaw) can be inserted between Tma1 and Tma2 cycles to extend the AH signal output period by setting the ADDEX bit in MPXCR. By inserting the Tmaw cycle, the address setup for AH and the AH minimum pulse width can be assured. Figure 9.32 shows the access timing when the address cycle is three cycles.
Address cycle Tma1 B Tmaw Tma2 T1 Data cycle T2
Address bus
CSn
AH RD Read D15 to D0 LHWR Address Read data
Write
LLWR
D15 to D0
Address
Write data
BS
RD/WR DACK or EDACK
Note: n = 3 to 7
Figure 9.32 Access Timing of 3 Address Cycles (ADDEX = 1)
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Section 9 Bus Controller (BSC)
9.9.7
Wait Control
In the data cycle of the address/data multiplexed I/O interface, program wait insertion and pin wait insertion by the WAIT pin are enabled in the same way as in the basic bus interface. For details, see section 9.6.4, Wait Control. Wait control settings do not affect the address cycles. 9.9.8 Read Strobe (RD) Timing
In the address/data multiplexed I/O interface, the read strobe timing of data cycles can be modified in the same way as in basic bus interface. For details, see section 9.6.5, Read Strobe (RD) Timing. Figure 9.33 shows an example when the read strobe timing is modified.
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Section 9 Bus Controller (BSC)
Address cycle Tma1 Tma2 T1
Data cycle T2
B Address bus
CSn
AH
RD RDNn = 0 D15 to D0 Address Read data
RD RDNn = 1 D15 to D0 Address Read data
BS
RD/WR
DACK or EDACK Note: n = 3 to 7
Figure 9.33 Read Strobe Timing
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Section 9 Bus Controller (BSC)
9.9.9
Extension of Chip Select (CS) Assertion Period
In the address/data multiplexed interface, the extension cycles can be inserted before and after the bus cycle. For details, see section 9.6.6, Extension of Chip Select (CS) Assertion Period. Figure 9.34 shows an example of the chip select (CS) assertion period extension timing.
Bus cycle Address cycle Data cycle Th T1
Tma1
B
Tma2
T2
Tt
Address bus
CSn AH
RD
Read
D15 to D0
Address
Read data
LHWR LLWR
Write
D15 to D0
Address
Write data
BS
RD/WR
DACK or EDACK
Note: n = 3 to 7
Figure 9.34 Chip Select (CS) Assertion Period Extension Timing in Data Cycle
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Section 9 Bus Controller (BSC)
When consecutively reading from the same area connected to a peripheral LSI whose data hold time is long, data outputs from the peripheral LSI and this LSI may conflict. Inserting the chip select assertion period extension cycle after the access cycle can avoid the data conflict. Figure 9.35 shows an example of the operation. In the figure, both bus cycles A and B are read access cycles to the address/data multiplexed I/O space. An example of the data conflict is shown in (a), and an example of avoiding the data conflict by the CS assertion period extension cycle in (b).
Bus cycle A Bus cycle B
B Address bus CS AH RD Data bus Data conflict
Data hold time is long.
(a) Without CS assertion period extension cycle (CSXTn = 0) Bus cycle A Bus cycle B
B Address bus CS AH RD Data bus (b) With CS assertion period extension cycle (CSXTn = 1)
Figure 9.35 Consecutive Read Accesses to Same Area (Address/Data Multiplexed I/O Space)
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Section 9 Bus Controller (BSC)
9.9.10
DACK and EDACK Signal Output Timings
For DMAC or EXDMAC single address transfers, the DACK and EDACK signals assert timing can be modified by using the DKC and EDKC bits in BCR1. Figure 9.36 shows the DACK and EDACK signal output timings. Setting the DKC or EDKC bit to 1 asserts the DACK or EDACK signal a half cycle earlier.
Address cycle
Data cycle
Tma1
B
Tma2
T1
T2
Address bus
CSn AH RD
RDNn = 0
D15 to D0 RD
RDNn = 1
Address
Read data
D15 to D0
Address
Read data
BS RD/WR
DKC, EDKC = 0
DACK or EDACK
DKC, EDKC = 1 Note: n = 3 to 7
Figure 9.36 DACK and EDACK Signal Output Timings
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Section 9 Bus Controller (BSC)
9.10
Idle Cycle
In this LSI, idle cycles can be inserted between the consecutive external accesses. By inserting the idle cycle, data conflicts between ROM read cycle whose output floating time is long and an access cycle from/to high-speed memory or I/O interface can be prevented. 9.10.1 Operation
When this LSI consecutively accesses external address space, it can insert an idle cycle between bus cycles in the following four cases. These conditions are determined by the sequence of read and write and previously accessed area. 1. 2. 3. 4. When read cycles of different areas in the external address space occur consecutively When an external write cycle occurs immediately after an external read cycle When an external read cycle occurs immediately after an external write cycle When an external access occurs immediately after a DMAC or EXDMAC single address transfer (write cycle)
Up to four idle cycles can be inserted under the conditions shown above. The number of idle cycles to be inserted should be specified to prevent data conflicts between the output data from a previously accessed device and data from a subsequently accessed device. Under conditions 1 and 2, which are the conditions to insert idle cycles after read, the number of idle cycles can be selected from setting A specified by bits IDLCA1 and IDLCA0 in IDLCR or setting B specified by bits IDLCB1 and IDLCB0 in IDLCR: Setting A can be selected from one to four cycles, and setting B can be selected from one or two to four cycles. Setting A or B can be specified for each area by setting bits IDLSEL7 to IDLSEL0 in IDLCR. Note that bits IDLSEL7 to IDLSEL0 correspond to the previously accessed area of the consecutive accesses. The number of idle cycles to be inserted under conditions 3 and 4, which are conditions to insert idle cycles after write, can be determined by setting A as described above. After the reset release, IDLCR is initialized to four idle cycle insertion under all conditions 1 to 4 shown above. Table 9.20 shows the correspondence between conditions 1 to 4 and number of idle cycles to be inserted for each area. Table 9.21 shows the correspondence between the number of idle cycles to be inserted specified by settings A and B, and number of cycles to be inserted.
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Section 9 Bus Controller (BSC)
Table 9.20 Number of Idle Cycle Insertion Selection in Each Area
Bit Settings IDLSn Insertion Condition Consecutive reads in different areas n 1 IDLSELn 0 0 1 Write after read 0 0 1 0 1 Read after write 2 0 1 External access after single address transfer 3 0 1 A B A B A B A B A B A B Area for Previous Access 1 2 3 4 5 6 7
Setting n = 0 to 7 0 1
Invalid A B A B A B A B A B
Invalid A B A B A B A B A B
Invalid A Invalid A
[Legend] A: Number of idle cycle insertion A is selected. B: Number of idle cycle insertion B is selected. Invalid: No idle cycle is inserted for the corresponding condition.
Table 9.21 Number of Idle Cycle Insertions
Bit Settings A IDLCA1 0 0 1 1 IDLCA0 0 1 0 1 IDLCB1 0 0 1 1 B IDLCB0 0 1 0 1 Number of Cycles 0 1 2 3 4
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Section 9 Bus Controller (BSC)
(1)
Consecutive Reads in Different Areas
If consecutive reads in different areas occur while bit IDLS1 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 when bit IDLSELn in IDLCR is cleared to 0, or bits IDLCB1 and IDLCB0 when bit IDLSELn is set to 1 are inserted at the start of the second read cycle (n = 0 to 7). Figure 9.37 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data conflict is prevented.
Bus cycle A T1 B Address bus CS (area A) CS (area B) RD T2 T3 Bus cycle B T1
T2
Bus cycle A T1 T2 T3 Bus cycle B Ti T1
T2
Data bus Data conflict
Data hold time is long.
(a) No idle cycle inserted (IDLS1 = 0)
(b) Idle cycle inserted (IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Figure 9.37 Example of Idle Cycle Operation (Consecutive Reads in Different Areas)
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Section 9 Bus Controller (BSC)
(2)
Write after Read
If an external write occurs after an external read while bit IDLS0 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 when bit IDLSELn in IDLCR is cleared to 0 when IDLSELn = 0, or bits IDLCB1 and IDLCB0 when IDLSELn is set to 1 are inserted at the start of the write cycle (n = 0 to 7). Figure 9.38 shows an example of the operation in this case. In this example, bus cycle A is a read cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data conflict is prevented.
Bus cycle A T1 B Address bus CS (area A) CS (area B) RD LLWR T2 T3 Bus cycle B T1 T2
Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2
Data bus
Data hold time is long.
Data conflict
(a) No idle cycle inserted (IDLS0 = 0)
(b) Idle cycle inserted (IDLS0 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Figure 9.38 Example of Idle Cycle Operation (Write after Read)
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Section 9 Bus Controller (BSC)
(3)
Read after Write
If an external read occurs after an external write while bit IDLS2 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 are inserted at the start of the read cycle (n = 0 to 7). Figure 9.39 shows an example of the operation in this case. In this example, bus cycle A is a CPU write cycle and bus cycle B is a read cycle from the SRAM. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the CPU write data and read data from an SRAM device. In (b), an idle cycle is inserted, and a data conflict is prevented.
Bus cycle A T1 B Address bus CS (area A) CS (area B) RD LLWR Data bus T2 T3 Bus cycle B T1 T2
Bus cycle A T1 T2 T3 Bus cycle B Ti T1 T2
Data conflict
Output floating time is long.
(a) No idle cycle inserted (IDLS2 = 0) (b) Idle cycle inserted (IDLS2 = 1, IDLCA1 = 0, IDLCA0 = 0)
Figure 9.39 Example of Idle Cycle Operation (Read after Write)
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Section 9 Bus Controller (BSC)
(4)
External Access after Single Address Transfer Write
If an external access occurs after a single address transfer write while bit IDLS3 in IDLCR is set to 1, idle cycles specified by bits IDLCA1 and IDLCA0 are inserted at the start of the external access (n = 0 to 7). Figure 9.40 shows an example of the operation in this case. In this example, bus cycle A is a single address transfer (write cycle) and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a conflict occurs in bus cycle B between the external device write data and this LSI write data. In (b), an idle cycle is inserted, and a data conflict is prevented.
Bus cycle A
T1 T2 T3
Bus cycle B
T1 T2
Bus cycle A T1 T2 T3
Bus cycle B Ti T1 T2
B Address bus CS (area A) CS (area B)
LLWR DACK or EDACK Data bus
Data conflict
Output floating time is long.
(a) No idle cycle inserted (IDLS3 = 0)
(b) Idle cycle inserted (IDLS3 = 1, IDLCA1 = 0, IDLCA0 = 0)
Figure 9.40 Example of Idle Cycle Operation (Write after Single Address Transfer Write)
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Section 9 Bus Controller (BSC)
(5)
External NOP Cycles and Idle Cycles
A cycle in which an external space is not accessed due to internal operations is called an external NOP cycle. Even when an external NOP cycle occurs between consecutive external bus cycles, an idle cycle can be inserted. In this case, the number of external NOP cycles is included in the number of idle cycles to be inserted. Figure 9.41 shows an example of external NOP and idle cycle insertion.
No external access Idle cycle (NOP) (remaining) Ti Ti T1
Preceding bus cycle T1 B T2 Tpw T3
Following bus cycle T2 Tpw T3
Address bus CS (area A) CS (area B)
RD
Data bus
Specified number of idle cycles or more including no external access cycles (NOP) (Condition: Number of idle cycles to be inserted when different reads continue: 4 cycles)
Figure 9.41 Idle Cycle Insertion Example
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Section 9 Bus Controller (BSC)
(6)
Relationship between Chip Select (CS) Signal and Read (RD) Signal
Depending on the system's load conditions, the RD signal may lag behind the CS signal. An example is shown in Figure 9.42. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the RD signal in bus cycle A and the CS signal in bus cycle B. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle indicated in (b) is set.
Bus cycle A T1 B Address bus CS (area A) CS (area B) RD T2 T3 Bus cycle B T1
T2 Bus cycle A T1 T2 T3 Bus cycle B Ti T1
T2
Overlap time may occur between the CS (area B) and RD (a) No idle cycle inserted (IDLS1 = 0) (b) Idle cycle inserted (IDLS1 = 1, IDLSELn = 0, IDLCA1 = 0, IDLCA0 = 0)
Figure 9.42 Relationship between Chip Select (CS) and Read (RD)
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Section 9 Bus Controller (BSC)
Table 9.22 Idle Cycles in Mixed Accesses to Normal Space
Previous Access Next Access IDLS 3 2 1 0 1 0 IDLSEL 7 to 0 0 1 0 0 1 1 1 IDLCA 0 0 1 0 1 0 0 1 1 Normal space Normal read space write 0 1 0 0 0 1 1 1 0 1 0 1 0 0 1 1 Normal space Normal write space read 0 1 0 0 1 1 Single Normal address space read transfer write 0 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 IDLCB 0 Idle Cycle Disabled 1 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted 0 cycle inserted 2 cycle inserted 3 cycles inserted 4 cycles inserted Disabled 1 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted 0 cycle inserted 2 cycle inserted 3 cycles inserted 4 cycles inserted Disabled 1 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted Disabled 1 cycle inserted 2 cycles inserted 3 cycles inserted 4 cycles inserted
Normal space Normal read space read
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Section 9 Bus Controller (BSC)
9.10.2
Pin States in Idle Cycle
Table 9.23 shows the pin states in an idle cycle. Table 9.23 Pin States in Idle Cycle
Pins A20 to A0 D15 to D0 CSn (n = 7 to 0) AS RD BS RD/WR AH LHWR, LLWR DACKn (n = 3 to 0) EDACKn (n = 1 to 0) Pin State Contents of following bus cycle High impedance High High High High High low High High High
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Section 9 Bus Controller (BSC)
9.11
Bus Release
This LSI can release the external bus in response to a bus request from an external device. In the external bus released state, internal bus masters except the EXDMAC continue to operate as long as there is no external access. In addition, in the external bus released state, the BREQO signal can be driven low to output a bus request externally. 9.11.1 Operation
In external extended mode, when the BRLE bit in BCR1 is set to 1 and the ICR bits for the corresponding pin are set to 1, the bus can be released to the external. Driving the BREQ pin low issues an external bus request to this LSI. When the BREQ pin is sampled, at the prescribed timing, the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus released state. For details on DDR and ICR, see section 13, I/O Ports. In the external bus released state, the CPU, DTC, and DMAC can access the internal space using the internal bus. When the CPU, DTC, DMAC, or EXDMAC attempts to access the external address space, it temporarily defers initiation of the bus cycle, and waits for the bus request from the external bus master to be canceled. If the BREQOE bit in BCR1 is set to 1, the BREQO pin can be driven low when any of the following requests are issued, to request cancellation of the bus request externally. * When the CPU, DTC, DMAC, or EXDMAC attempts to access the external address space * When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clock-stop mode * When SCKCR is written to for setting the clock frequency If an external bus release request and external access occur simultaneously, the priority is as follows: (High) EXDMAC > External bus release > External access by CPU, DTC, or DMAC (Low)
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Section 9 Bus Controller (BSC)
9.11.2
Pin States in External Bus Released State
Table 9.24 shows pin states in the external bus released state. Table 9.24 Pin States in Bus Released State
Pins A20 to A0 D15 to D0 BS CSn (n = 7 to 0) AS AH RD/WR RD LUB, LLB LHWR, LLWR DACKn (n = 3 to 0) EDACKn (n = 1 to 0) Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High level High level
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Section 9 Bus Controller (BSC)
9.11.3
Transition Timing
Figure 9.43 shows the timing for transition to the bus released state.
External space access cycle T1 T2
External bus released state
CPU cycle
B
Address bus
Data bus
Hi-Z
Hi-Z Hi-Z
CSn
AS
RD
Hi-Z Hi-Z
LHWR, LLWR
BREQ
Hi-Z
BACK
BREQO
[1]
[2]
[3]
[4]
[7]
[5]
[8]
[6]
[1] A low level of the BREQ signal is sampled at the rising edge of the B signal. [2] The bus control signals are driven high at the end of the external space access cycle. It takes two cycles or more after the low level of the BREQ signal is sampled. [3] The BACK signal is driven low, releasing bus to the external bus master. [4] The BREQ signal state sampling is continued in the external bus released state. [5] A high level of the BREQ signal is sampled. [6] The external bus released cycles are ended one cycle after the BREQ signal is driven high. [7] When the external space is accessed by an internal bus master during external bus released while the BREQOE bit is set to 1, the BREQO signal goes low. [8] Normally the BREQO signal goes high at the rising edge of the BACK signal.
Figure 9.43 Bus Released State Transition Timing
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Section 9 Bus Controller (BSC)
9.12
9.12.1
Internal Bus
Access to Internal Address Space
The internal address spaces of this LSI are the on-chip ROM space, on-chip RAM space, and register space for the on-chip peripheral modules. The number of cycles necessary for access differs according the space. Table 9.25 shows the number of access cycles for each on-chip memory space. Table 9.25 Number of Access Cycles for On-Chip Memory Spaces
Access Space On-chip ROM space On-chip RAM space Access Read Write Read Write Number of Access Cycles One I cycle Three I cycles One I cycle One I cycle
In access to the registers for on-chip peripheral modules, the number of access cycles differs according to the register to be accessed. When the dividing ratio of the operating clock of a bus master and that of a peripheral module is 1 : n, synchronization cycles using a clock divided by 0 to n-1 are inserted for register access in the same way as for external bus clock division. Table 9.26 lists the number of access cycles for registers of on-chip peripheral modules. Table 9.26 Number of Access Cycles for Registers of On-Chip Peripheral Modules
Number of Cycles Module to be Accessed
DMAC and EXDMAC registers
Read Two I
Write Two I Three I
Write Data Buffer Function Disabled Disabled
MCU operating mode, clock pulse generator, Two I power-down control registers, interrupt controller, bus controller, and DTC registers I/O port registers of PFCR and WDT I/O port registers other than PFCR and PORTM, PPG0, TPU, TMR0, TMR1, SCI0 to SCI2, SCI4, IIC2, D/A, and A/D_0 registers
Two P Two P
Three P Disabled Two P Enabled
I/O port registers of PORTM, TMR2, TMR3, USB, Three P SCI5, SCI6, A/D_1, and PPG1 registers
Three P Enabled
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Section 9 Bus Controller (BSC)
9.13
9.13.1
Write Data Buffer Function
Write Data Buffer Function for External Data Bus
This LSI has a write data buffer function for the external data bus. Using the write data buffer function enables internal accesses in parallel with external writes or DMAC single address transfers. The write data buffer function is made available by setting the WDBE bit to 1 in BCR1. Figure 9.44 shows an example of the timing when the write data buffer function is used. When this function is used, if an external address space write or a DMAC single address transfer continues for two cycles or longer, and there is an internal access next, an external write only is executed in the first two cycles. However, from the next cycle onward, internal accesses (on-chip memory or internal I/O register read/write) and the external address space write rather than waiting until it ends are executed in parallel.
On-chip memory read
Peripheral module read
External write cycle
I
Internal address bus
On-chip memory 1
On-chip memory 2
Peripheral module address
T1
T2
T3
B
Address bus
External address
External space write
CSn LHWR, LLWR
D15 to D0
Figure 9.44 Example of Timing when Write Data Buffer Function is Used
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Section 9 Bus Controller (BSC)
9.13.2
Write Data Buffer Function for Peripheral Modules
This LSI has a write data buffer function for the peripheral module access. Using the write data buffer function enables peripheral module writes and on-chip memory or external access to be executed in parallel. The write data buffer function is made available by setting the PWDBE bit in BCR2 to 1. For details on the on-chip peripheral module registers, see Table 9.26, Number of Access Cycles for Registers of On-Chip Peripheral Modules in section 9.12, Internal Bus. Figure 9.45 shows an example of the timing when the write data buffer function is used. When this function is used, if an internal I/O register write continues for two cycles or longer and then there is an on-chip RAM, an on-chip ROM, or an external access, internal I/O register write only is performed in the first two cycles. However, from the next cycle onward an internal memory or an external access and internal I/O register write are executed in parallel rather than waiting until it ends.
On-chip memory read
Peripheral module write I
Internal address bus
P
Internal I/O address bus Internal I/O data bus
Peripheral module address
Figure 9.45 Example of Timing when Peripheral Module Write Data Buffer Function is Used
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Section 9 Bus Controller (BSC)
9.14
Bus Arbitration
This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). This LSI incorporates internal access and external access bus arbiters that can be used and controlled independently. The internal bus arbiter handles the CPU, DTC, and DMAC accesses. The external bus arbiter handles the external access by the CPU, DTC, and DMAC, external access by the EXDMAC, and external bus release request (external bus master). The bus arbiters determine priorities at the prescribed timing, and permit use of the bus by means of the bus request acknowledge signal. 9.14.1 Operation
The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The priority of the internal bus arbitration:
(High) DMAC > DTC > CPU (Low)
The priority of the external bus arbitration:
(High) EXDMAC > External bus release request > External access by the CPU, DTC, and DMAC (Low)
If the DMAC or DTC accesses continue, the CPU can be given priority over the DMAC or DTC to execute the bus cycles alternatively between them by setting the IBCCS bit in BCR2. In this case, the priority between the DMAC and DTC does not change. If the external bus release request or EXDMAC accesses continue, the external access by the CPU, DTC, and DMAC can be given priority over the EXDMAC or external bus release request to execute the bus cycles alternatively between them by setting the EBCCS bit in BCR2. In this case, the priority between the EXDMAC and external bus release request does not change. An internal bus access by the CPU, DTC, or DMAC, an external bus access by an external bus release request, and an external bus access by the EXDMAC can be executed in parallel.
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Section 9 Bus Controller (BSC)
9.14.2
Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority over that of the bus master that has taken control of the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific timings at which each bus master can release the bus. (1) CPU
The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or DMAC, the internal bus arbiter transfers the bus to the bus master that issued the request. If an external bus cycle is executed by the CPU, the external bus arbiter transfers the bus to the EXDMAC that issued the request. The timing for transfer of the bus is at the end of the bus cycle. In sleep mode, the bus is transferred synchronously with the clock. Note, however, that the bus cannot be transferred in the following cases. * The word or longword access is performed in some divisions. * Stack handling is performed in multiple bus cycles. * Transfer data read or write by memory transfer instructions, block transfer instructions, or TAS instruction. (In the block transfer instructions, the bus can be transferred in the write cycle and the following transfer data read cycle.) * From the target read to write in the bit manipulation instructions or memory operation instructions. (In an instruction that performs no write operation according to the instruction condition, up to a cycle corresponding the write cycle) (2) DTC
The DTC sends the internal bus arbiter a request for the bus when an activation request is generated. When the DTC accesses an external bus space, the DTC first takes control of the bus from the internal bus arbiter and then requests a bus to the external bus arbiter. Once the DTC takes control of the bus, the DTC continues the transfer processing cycles. If a bus master whose priority is higher than the DTC requests the bus, the DTC transfers the bus to the higher priority bus master. If the IBCCS bit in BCR2 is set to 1, the DTC transfers the bus to the CPU. Note, however, that the bus cannot be transferred in the following cases.
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Section 9 Bus Controller (BSC)
* During transfer information read * During the first data transfer * During transfer information write back The DTC releases the bus when the consecutive transfer cycles completed. (3) DMAC
The DMAC sends the internal bus arbiter a request for the bus when an activation request is generated. When the DMAC accesses an external bus space, the DMAC first takes control of the bus from the internal bus arbiter and then requests a bus to the external bus arbiter. After the DMAC takes control of the bus, it may continue the transfer processing cycles or release the bus at the end of every bus cycle depending on the conditions. The DMAC continues transfers without releasing the bus in the following case: * Between the read cycle in the dual-address mode and the write cycle corresponding to the read cycle If no bus master of a higher priority than the DMAC requests the bus and the IBCCS bit in BCR2 is cleared to 0, the DMAC continues transfers without releasing the bus in the following cases: * During 1-block transfers in the block transfer mode * During transfers in the burst mode In other cases, the DMAC transfers the bus at the end of the bus cycle. (4) EXDMAC
The EXDMAC sends the external bus arbiter a request for the bus when an activation request is generated. During external access by the internal bus master, the bus is transferred to the EXDMAC at the timing the bus can be transferred. After the EXDMAC takes control of the bus, it may continue the transfer processing cycles or release the bus at the end of every bus cycle depending on the conditions. The EXDMAC continues transfers without releasing the bus in the following case: * Between the read cycle in the dual-address mode and the write cycle corresponding to the read cycle * During transfers in the cluster transfer mode
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Section 9 Bus Controller (BSC)
If no bus master of a higher priority than the EXDMAC requests the bus and the EBCCS bit in BCR2 is cleared to 0, the EXDMAC continues transfers without releasing the bus in the following cases: * During 1-block transfers in the block transfer mode * During transfers in the burst mode In other cases, the EXDMAC transfers the bus at the end of the bus cycle. If startup requests are issued to the multiple EXDMAC channels when other bus masters do not request the bus, the EXDMAC takes control of the bus and continues to transfer processing cycles. (5) External Bus Release
When the BREQ pin goes low and an external bus release request is issued while the BRLE bit in BCR1 is set to 1 with the corresponding ICR bit set to 1, a bus request is sent to the bus arbiter. External bus release can be performed on completion of an external bus cycle.
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Section 9 Bus Controller (BSC)
9.15
Bus Controller Operation in Reset
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any executing bus cycle is aborted.
9.16
(1)
Usage Notes
Setting Registers
The BSC registers must be specified before accessing the external address space. In on-chip ROM disabled mode, the BSC registers must be specified before accessing the external address space for other than an instruction fetch access. (2) External Bus Release Function and All-Module-Clock-Stop Mode
In this LSI, if the ACSE bit in MSTPCRA is set to 1, and then a SLEEP instruction is executed with the setting for all peripheral module clocks to be stopped (MSTPCRA and MSTPCRB = H'FFFFFFFF) or for operation of the 8-bit timer module alone (MSTPCRA and MSTPCRB = H'F[F to C]FFFFFF), and a transition is made to the sleep state, the all-module-clock-stop mode is entered in which the clock is also stopped for the bus controller and I/O ports. For details, see section 27, Power-Down Modes. In this state, the external bus release function is halted. To use the external bus release function in sleep mode, the ACSE bit in MSTPCRA must be cleared to 0. Conversely, if a SLEEP instruction to place the chip in all-module-clock-stop mode is executed in the external bus released state, the transition to all-module-clock-stop mode is deferred and performed until after the bus is recovered. (3) External Bus Release Function and Software Standby
In this LSI, internal bus master operation does not stop even while the bus is released, as long as the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP instruction to place the chip in software standby mode is executed while the external bus is released, the transition to software standby mode is deferred and performed after the bus is recovered. Also, since clock oscillation halts in software standby mode, if the BREQ signal goes low in this mode, indicating an external bus release request, the request cannot be answered until the chip has recovered from the software standby mode. Note that the BACK and BREQO pins are both in the high-impedance state in software standby mode.
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Section 9 Bus Controller (BSC)
(4)
BREQO Output Timing
When the BREQOE bit is set to 1 and the BREQO signal is output, both the BREQO and BACK signals may go low simultaneously. This will occur if the next external access request occurs while internal bus arbitration is in progress after the chip samples a low level of the BREQ signal.
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Section 9 Bus Controller (BSC)
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Section 10 DMA Controller (DMAC)
Section 10 DMA Controller (DMAC)
This LSI includes a 4-channel DMA controller (DMAC).
10.1
Features
* Maximum of 4-G byte address space can be accessed * Byte, word, or longword can be set as data transfer unit * Maximum of 4-G bytes (4,294,967,295 bytes) can be set as total transfer size Supports free-running mode in which total transfer size setting is not needed * DMAC activation methods are auto-request, on-chip module interrupt, and external request. Auto request: CPU activates (cycle stealing or burst access can be selected) On-chip module interrupt: Interrupt requests from on-chip peripheral modules can be selected as an activation source External request: Low level or falling edge detection of the DREQ signal can be selected. External request is available for all four channels. * Dual or single address mode can be selected as address mode Dual address mode: Both source and destination are specified by addresses Single address mode: Either source or destination is specified by the DACK signal and the other is specified by address * Normal, repeat, or block transfer can be selected as transfer mode Normal transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat size of data is transferred and then a transfer address returns to the transfer start address Up to 65536 transfers (65,536 bytes/words/longwords) can be set as repeat size Block transfer mode: One block data is transferred at a single transfer request Up to 65,536 bytes/words/longwords can be set as block size
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Section 10 DMA Controller (DMAC)
* Extended repeat area function which repeats the addressees within a specified area using the transfer address with the fixed upper bits (ring buffer transfer can be performed, as an example) is available One bit (two bytes) to 27 bits (128 Mbytes) for transfer source and destination can be set as extended repeat areas * Address update can be selected from fixed address, offset addition, and increment or decrement by 1, 2, or 4 Address update by offset addition enables to transfer data at addresses which are not placed continuously * Word or longword data can be transferred to an address which is not aligned with the respective boundary Data is divided according to its address (byte or word) when it is transferred * Two types of interrupts can be requested to the CPU A transfer end interrupt is generated after the number of data specified by the transfer counter is transferred. A transfer escape end interrupt is generated when the remaining total transfer size is less than the transfer data size at a single transfer request, when the repeat size of data transfer is completed, or when the extended repeat area overflows. * Module stop state can be set.
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Section 10 DMA Controller (DMAC)
A block diagram of the DMAC is shown in figure 10.1.
Internal address bus External pins DREQn DACKn TENDn Interrupt signals requested to the CPU by each channel Internal activation sources ... Controller Address buffer Operation unit Operation unit DOFR_n DSAR_n Internal activation source detector DMDR_n DMRSR_n DACR_n DDAR_n DTCR_n DBSR_n
Internal data bus
Data buffer
Module data bus [Legend] DSAR_n: DDAR_n: DOFR_n: DTCR_n: DBSR_n: DMDR_n: DACR_n: DMRSR_n: DMA source address register DMA destination address register DMA offset register DMA transfer count register DMA block size register DMA mode control register DMA address control register DMA module request select register DREQn: DMA transfer request DACKn: DMA transfer acknowledge TENDn: DMA transfer end n = 0 to 3
Figure 10.1 Block Diagram of DMAC
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Section 10 DMA Controller (DMAC)
10.2
Input/Output Pins
Table 10.1 shows the pin configuration of the DMAC. Table 10.1 Pin Configuration
Channel 0 Pin Name DMA transfer request 0 DMA transfer acknowledge 0 DMA transfer end 0 1 DMA transfer request 1 DMA transfer acknowledge 1 DMA transfer end 1 2 DMA transfer request 2 DMA transfer acknowledge 2 DMA transfer end 2 3 DMA transfer request 3 DMA transfer acknowledge 3 DMA transfer end 3 Abbr. DREQ0 DACK0 TEND0 DREQ1 DACK1 TEND1 DREQ2 DACK2 TEND2 DREQ3 DACK3 TEND3 I/O Input Output Output Input Output Output Input Output Output Input Output Output Function Channel 0 external request Channel 0 single address transfer acknowledge Channel 0 transfer end Channel 1 external request Channel 1 single address transfer acknowledge Channel 1 transfer end Channel 2 external request Channel 2 single address transfer acknowledge Channel 2 transfer end Channel 3 external request Channel 3 single address transfer acknowledge Channel 3 transfer end
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Section 10 DMA Controller (DMAC)
10.3
Register Descriptions
The DMAC has the following registers. Channel 0: * * * * * * * * DMA source address register_0 (DSAR_0) DMA destination address register_0 (DDAR_0) DMA offset register_0 (DOFR_0) DMA transfer count register_0 (DTCR_0) DMA block size register_0 (DBSR_0) DMA mode control register_0 (DMDR_0) DMA address control register_0 (DACR_0) DMA module request select register_0 (DMRSR_0)
Channel 1: * * * * * * * * DMA source address register_1 (DSAR_1) DMA destination address register_1 (DDAR_1) DMA offset register_1 (DOFR_1) DMA transfer count register_1 (DTCR_1) DMA block size register_1 (DBSR_1) DMA mode control register_1 (DMDR_1) DMA address control register_1 (DACR_1) DMA module request select register_1 (DMRSR_1)
Channel 2: * * * * * * * * DMA source address register_2 (DSAR_2) DMA destination address register_2 (DDAR_2) DMA offset register_2 (DOFR_2) DMA transfer count register_2 (DTCR_2) DMA block size register_2 (DBSR_2) DMA mode control register_2 (DMDR_2) DMA address control register_2 (DACR_2) DMA module request select register_2 (DMRSR_2)
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Section 10 DMA Controller (DMAC)
Channel 3: * * * * * * * * DMA source address register_3 (DSAR_3) DMA destination address register_3 (DDAR_3) DMA offset register_3 (DOFR_3) DMA transfer count register_3 (DTCR_3) DMA block size register_3 (DBSR_3) DMA mode control register_3 (DMDR_3) DMA address control register_3 (DACR_3) DMA module request select register_3 (DMRSR_3) DMA Source Address Register (DSAR)
10.3.1
DSAR is a 32-bit readable/writable register that specifies the transfer source address. DSAR updates the transfer source address every time data is transferred. When DDAR is specified as the destination address (the DIRS bit in DACR is 1) in single address mode, DSAR is ignored. Although DSAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24
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Section 10 DMA Controller (DMAC)
10.3.2
DMA Destination Address Register (DDAR)
DDAR is a 32-bit readable/writable register that specifies the transfer destination address. DDAR updates the transfer destination address every time data is transferred. When DSAR is specified as the source address (the DIRS bit in DACR is 0) in single address mode, DDAR is ignored. Although DDAR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24
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Section 10 DMA Controller (DMAC)
10.3.3
DMA Offset Register (DOFR)
DOFR is a 32-bit readable/writable register that specifies the offset to update the source and destination addresses. Although different values are specified for individual channels, the same values must be specified for the source and destination sides of a single channel.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24
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Section 10 DMA Controller (DMAC)
10.3.4
DMA Transfer Count Register (DTCR)
DTCR is a 32-bit readable/writable register that specifies the size of data to be transferred (total transfer size). To transfer 1-byte data in total, set H'00000001 in DTCR. When H'00000000 is set in this register, it means that the total transfer size is not specified and data is transferred with the transfer counter stopped (free running mode). When H'FFFFFFFF is set, the total transfer size is 4 Gbytes (4,294,967,295), which is the maximum size. While data is being transferred, this register indicates the remaining transfer size. The value corresponding to its data access size is subtracted every time data is transferred (byte: -1, word: -2, and longword: -4). Although DTCR can always be read from by the CPU, it must be read from in longwords and must not be written to while data for the channel is being transferred.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24
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Section 10 DMA Controller (DMAC)
10.3.5
DMA Block Size Register (DBSR)
DBSR specifies the repeat size or block size. DBSR is enabled in repeat transfer mode and block transfer mode and is disabled in normal transfer mode.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 31 BKSZH31 0 R/W 23 BKSZH23 0 R/W 15 BKSZ15 0 R/W 7 BKSZ7 0 R/W 30 BKSZH30 0 R/W 22 BKSZH22 0 R/W 14 BKSZ14 0 R/W 6 BKSZ6 0 R/W 29 BKSZH29 0 R/W 21 BKSZH21 0 R/W 13 BKSZ13 0 R/W 5 BKSZ5 0 R/W 28 BKSZH28 0 R/W 20 BKSZH20 0 R/W 12 BKSZ12 0 R/W 4 BKSZ4 0 R/W 27 BKSZH27 0 R/W 19 BKSZH19 0 R/W 11 BKSZ11 0 R/W 3 BKSZ3 0 R/W 26 BKSZH26 0 R/W 18 BKSZH18 0 R/W 10 BKSZ10 0 R/W 2 BKSZ2 0 R/W 25 BKSZH25 0 R/W 17 BKSZH17 0 R/W 9 BKSZ9 0 R/W 1 BKSZ1 0 R/W 24 BKSZH24 0 R/W 16 BKSZH16 0 R/W 8 BKSZ8 0 R/W 0 BKSZ0 0 R/W
Bit
Bit Name
Initial Value
R/W R/W
Description Specify the repeat size or block size. When H'0001 is set, the repeat or block size is one byte, one word, or one longword. When H'0000 is set, it means the maximum value (refer to table 10.1). While the DMA is in operation, the setting is fixed.
31 to 16 BKSZH31 to All 0 BKSZH16
15 to 0
BKSZ15 to BKSZ0
All 0
R/W
Indicate the remaining repeat or block size while the DMA is in operation. The value is decremented by 1 every time data is transferred. When the remaining size becomes 0, the value of the BKSZH bits is loaded. Set the same value as the BKSZH bits.
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Section 10 DMA Controller (DMAC)
Table 10.2 Data Access Size, Valid Bits, and Settable Size
Mode Data Access Size BKSZH Valid Bits BKSZ Valid Bits 31 to 16 15 to 0 Settable Size (Byte) 1 to 65,536 2 to 131,072 4 to 262,144
Byte Repeat transfer and block transfer Word Longword
10.3.6
DMA Mode Control Register (DMDR)
DMDR controls the DMAC operation. * DMDR_0
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 31 DTE 0 R/W 23 ACT 0 R 15 DTSZ1 0 R/W 7 DTF1 0 R/W 30 DACKE 0 R/W 22 0 R 14 DTSZ0 0 R/W 6 DTF0 0 R/W 29 TENDE 0 R/W 21 0 R 13 MDS1 0 R/W 5 DTA 0 R/W 28 0 R/W 20 0 R 12 MDS0 0 R/W 4 0 R 27 DREQS 0 R/W 19 ERRF 0 R/(W)* 11 TSEIE 0 R/W 3 0 R 26 NRD 0 R/W 18 0 R 10 0 R 2 DMAP2 0 R/W 25 0 R 17 ESIF 0 R/(W)* 9 ESIE 0 R/W 1 DMAP1 0 R/W 24 0 R 16 DTIF 0 R/(W)* 8 DTIE 0 R/W 0 DMAP0 0 R/W
Only 0 can be written to this bit after having been read as 1, to clear the flag.
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Section 10 DMA Controller (DMAC)
* DMDR_1 to DMDR_3
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 31 DTE 0 R/W 23 ACT 0 R 15 DTSZ1 0 R/W 7 DTF1 0 R/W 30 DACKE 0 R/W 22 0 R 14 DTSZ0 0 R/W 6 DTF0 0 R/W 29 TENDE 0 R/W 21 0 R 13 MDS1 0 R/W 5 DTA 0 R/W 28 0 R/W 20 0 R 12 MDS0 0 R/W 4 0 R 27 DREQS 0 R/W 19 0 R 11 TSEIE 0 R/W 3 0 R 26 NRD 0 R/W 18 0 R 10 0 R 2 DMAP2 0 R/W 25 0 R 17 ESIF 0 R/(W)* 9 ESIE 0 R/W 1 DMAP1 0 R/W 24 0 R 16 DTIF 0 R/(W)* 8 DTIE 0 R/W 0 DMAP0 0 R/W
Only 0 can be written to this bit after having been read as 1, to clear the flag.
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Section 10 DMA Controller (DMAC)
Bit 31
Bit Name DTE
Initial Value 0
R/W R/W
Description Data Transfer Enable Enables/disables a data transfer for the corresponding channel. When this bit is set to 1, it indicates that the DMAC is in operation. Setting this bit to 1 starts a transfer when the autorequest is selected. When the on-chip module interrupt or external request is selected, a transfer request after setting this bit to 1 starts the transfer. While data is being transferred, clearing this bit to 0 stops the transfer. In block transfer mode, if writing 0 to this bit while data is being transferred, this bit is cleared to 0 after the current 1-block size data transfer. If an event which stops (sustains) a transfer occurs externally, this bit is automatically cleared to 0 to stop the transfer. Operating modes and transfer methods must not be changed while this bit is set to 1. 0: Disables a data transfer 1: Enables a data transfer (DMA is in operation) [Clearing conditions] * * * * * When the specified total transfer size of transfers is completed When a transfer is stopped by an overflow interrupt by a repeat size end When a transfer is stopped by an overflow interrupt by an extended repeat size end When a transfer is stopped by a transfer size error interrupt When clearing this bit to 0 to stop a transfer
In block transfer mode, this bit changes after the current block transfer. * * When an address error or an NMI interrupt is requested In the reset state or hardware standby mode
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Section 10 DMA Controller (DMAC)
Bit 30
Bit Name DACKE
Initial Value 0
R/W R/W
Description DACK Signal Output Enable Enables/disables the DACK signal output in single address mode. This bit is ignored in dual address mode. 0: Disables DACK signal output 1: Enables DACK signal output
29
TENDE
0
R/W
TEND Signal Output Enable Enables/disables the TEND signal output. 0: Disables TEND signal output 1: Enables TEND signal output
28 27
DREQS
0 0
R/W R/W
Reserved Initial value should not be changed. DREQ Select Selects whether a low level or the falling edge of the DREQ signal used in external request mode is detected. 0: Low level detection 1: Falling edge detection (the first transfer after a transfer enabled is detected on a low level)
26
NRD
0
R/W
Next Request Delay Selects the accepting timing of the next transfer request. 0: Starts accepting the next transfer request after completion of the current transfer 1: Starts accepting the next transfer request one cycle of B after completion of the current transfer
25, 24
All 0
R
Reserved These bits are always read as 0 and cannot be modified.
23
ACT
0
R
Active State Indicates the operating state for the channel. 0: Waiting for a transfer request or a transfer disabled state by clearing the DTE bit to 0 1: Active state
22 to 20
All 0
R
Reserved These bits are always read as 0 and cannot be modified.
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Section 10 DMA Controller (DMAC)
Bit 19
Bit Name ERRF
Initial Value 0
R/W
Description
R/(W)* System Error Flag Indicates that an address error or an NMI interrupt has been generated. This bit is available only in DMDR_0. Setting this bit to 1 prohibits writing to the DTE bit for all the channels. This bit is reserved in DMDR_1 to DMDR_3. It is always read as 0 and cannot be modified. 0: An address error or an NMI interrupt has not been generated 1: An address error or an NMI interrupt has been generated [Clearing condition] * * When clearing to 0 after reading ERRF = 1 When an address error or an NMI interrupt has been generated [Setting condition]
However, when an address error or an NMI interrupt has been generated in DMAC module stop mode, this bit is not set to 1. 18 17 ESIF 0 0 R Reserved This bit is always read as 0 and cannot be modified. R/(W)* Transfer Escape Interrupt Flag Indicates that a transfer escape end interrupt has been requested. A transfer escape end means that a transfer is terminated before the transfer counter reaches 0. 0: A transfer escape end interrupt has not been requested 1: A transfer escape end interrupt has been requested [Clearing conditions] * * * * * When setting the DTE bit to 1 When clearing to 0 before reading ESIF = 1 When a transfer size error interrupt is requested When a repeat size end interrupt is requested When a transfer end interrupt by an extended repeat area overflow is requested
[Setting conditions]
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Section 10 DMA Controller (DMAC)
Bit 16
Bit Name DTIF
Initial Value 0
R/W
Description
R/(W)* Data Transfer Interrupt Flag Indicates that a transfer end interrupt by the transfer counter has been requested. 0: A transfer end interrupt by the transfer counter has not been requested 1: A transfer end interrupt by the transfer counter has been requested [Clearing conditions] * * * When setting the DTE bit to 1 When clearing to 0 after reading DTIF = 1 When DTCR reaches 0 and the transfer is completed
[Setting condition]
15 14
DTSZ1 DTSZ0
0 0
R/W R/W
Data Access Size 1 and 0 Select the data access size for a transfer. 00: Byte size (eight bits) 01: Word size (16 bits) 10: Longword size (32 bits) 11: Setting prohibited
13 12
MDS1 MDS0
0 0
R/W R/W
Transfer Mode Select 1 and 0 Select the transfer mode. 00: Normal transfer mode 01: Block transfer mode 10: Repeat transfer mode 11: Setting prohibited
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Section 10 DMA Controller (DMAC)
Bit 11
Bit Name TSEIE
Initial Value 0
R/W R/W
Description Transfer Size Error Interrupt Enable Enables/disables a transfer size error interrupt. When the next transfer is requested while this bit is set to 1 and the contents of the transfer counter is less than the size of data to be transferred at a single transfer request, the DTE bit is cleared to 0. At this time, the ESIF bit is set to 1 to indicate that a transfer size error interrupt has been requested. The sources of a transfer size error are as follows: * * In normal or repeat transfer mode, the total transfer size set in DTCR is less than the data access size In block transfer mode, the total transfer size set in DTCR is less than the block size
0: Disables a transfer size error interrupt request 1: Enables a transfer size error interrupt request 10 9 ESIE 0 0 R R/W Reserved This bit is always read as 0 and cannot be modified. Transfer Escape Interrupt Enable Enables/disables a transfer escape end interrupt request. When the ESIF bit is set to 1 with this bit set to 1, a transfer escape end interrupt is requested to the CPU or DTC. The transfer end interrupt request is cleared by clearing this bit or the ESIF bit to 0. 0: Disables a transfer escape end interrupt 1: Enables a transfer escape end interrupt 8 DTIE 0 R/W Data Transfer End Interrupt Enable Enables/disables a transfer end interrupt request by the transfer counter. When the DTIF bit is set to 1 with this bit set to 1, a transfer end interrupt is requested to the CPU or DTC. The transfer end interrupt request is cleared by clearing this bit or the DTIF bit to 0. 0: Disables a transfer end interrupt 1: Enables a transfer end interrupt
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Section 10 DMA Controller (DMAC)
Bit 7 6
Bit Name DTF1 DTF0
Initial Value 0 0
R/W R/W R/W
Description Data Transfer Factor 1 and 0 Select a DMAC activation source. When the on-chip peripheral module setting is selected, the interrupt source should be selected by DMRSR. When the external request setting is selected, the sampling method should be selected by the DREQS bit. 00: Auto request (cycle stealing) 01: Auto request (burst access) 10: On-chip module interrupt 11: External request
5
DTA
0
R/W
Data Transfer Acknowledge This bit is valid in DMA transfer by the on-chip module interrupt source. This bit enables or disables to clear the source flag selected by DMRSR. 0: To clear the source in DMA transfer is disabled. Since the on-chip module interrupt source is not cleared in DMA transfer, it should be cleared by the CPU or DTC transfer. 1: To clear the source in DMA transfer is enabled. Since the on-chip module interrupt source is cleared in DMA transfer, it does not require an interrupt by the CPU or DTC transfer.
4, 3
All 0
R
Reserved These bits are always read as 0 and cannot be modified.
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Section 10 DMA Controller (DMAC)
Bit 2 1 0
Bit Name DMAP2 DMAP1 DMAP0
Initial Value 0 0 0
R/W R/W R/W R/W
Description DMA Priority Level 2 to 0 Select the priority level of the DMAC when using the CPU priority control function over DTC and DMAC. When the CPU has priority over the DMAC, the DMAC masks a transfer request and waits for the timing when the CPU priority becomes lower than the DMAC priority. The priority levels can be set to the individual channels. This bit is valid when the CPUPCE bit in CPUPCR is set to 1. 000: Priority level 0 (low) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (high)
Note:
*
Only 0 can be written to, to clear the flag.
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Section 10 DMA Controller (DMAC)
10.3.7
DMA Address Control Register (DACR)
DACR specifies the operating mode and transfer method.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 31 AMS 0 R/W 23 0 R 15 SARIE 0 R/W 7 DARIE 0 R/W 30 DIRS 0 R/W 22 0 R 14 0 R 6 0 R 29 0 R 21 SAT1 0 R/W 13 0 R 5 0 R 28 0 R 20 SAT0 0 R/W 12 SARA4 0 R/W 4 DARA4 0 R/W 27 0 R 19 0 R 11 SARA3 0 R/W 3 DARA3 0 R/W 26 RPTIE 0 R/W 18 0 R 10 SARA2 0 R/W 2 DARA2 0 R/W 25 ARS1 0 R/W 17 DAT1 0 R/W 9 SARA1 0 R/W 1 DARA1 0 R/W 24 ARS0 0 R/W 16 DAT0 0 R/W 8 SARA0 0 R/W 0 DARA0 0 R/W
Bit 31
Bit Name AMS
Initial Value 0
R/W R/W
Description Address Mode Select Selects address mode from single or dual address mode. In single address mode, the DACK pin is enabled according to the DACKE bit. 0: Dual address mode 1: Single address mode
30
DIRS
0
R/W
Single Address Direction Select Specifies the data transfer direction in single address mode. This bit s ignored in dual address mode. 0: Specifies DSAR as source address 1: Specifies DDAR as destination address
29 to 27
0
R/W
Reserved These bits are always read as 0 and cannot be modified.
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Section 10 DMA Controller (DMAC)
Bit 26
Bit Name RPTIE
Initial Value 0
R/W R/W
Description Repeat Size End Interrupt Enable Enables/disables a repeat size end interrupt request. In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat-size data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. Even when the repeat area is not specified (ARS1 = 1 and ARS0 = 0), a repeat size end interrupt after a 1-block data transfer can be requested. In addition, in block transfer mode, when the next transfer is requested after 1-block data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. 0: Disables a repeat size end interrupt 1: Enables a repeat size end interrupt Area Select 1 and 0 Specify the block area or repeat area in block or repeat transfer mode. 00: Specify the block area or repeat area on the source address 01: Specify the block area or repeat area on the destination address 10: Do not specify the block area or repeat area 11: Setting prohibited Reserved These bits are always read as 0 and cannot be modified. Source Address Update Mode 1 and 0 Select the update method of the source address (DSAR). When DSAR is not specified as the transfer source in single address mode, this bit is ignored. 00: Source address is fixed 01: Source address is updated by adding the offset 10: Source address is updated by adding 1, 2, or 4 according to the data access size 11: Source address is updated by subtracting 1, 2, or 4 according to the data access size
25 24
ARS1 ARS0
0 0
R/W R/W
23, 22
All 0
R
21 20
SAT1 SAT0
0 0
R/W R/W
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Section 10 DMA Controller (DMAC)
Bit 19, 18
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0 and cannot be modified.
17 16
DAT1 DAT0
0 0
R/W R/W
Destination Address Update Mode 1 and 0 Select the update method of the destination address (DDAR). When DDAR is not specified as the transfer destination in single address mode, this bit is ignored. 00: Destination address is fixed 01: Destination address is updated by adding the offset 10: Destination address is updated by adding 1, 2, or 4 according to the data access size 11: Destination address is updated by subtracting 1, 2, or 4 according to the data access size
15
SARIE
0
R/W
Interrupt Enable for Source Address Extended Area Overflow Enables/disables an interrupt request for an extended area overflow on the source address. When an extended repeat area overflow on the source address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the source address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which a transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended area overflow on the source address 1: Enables an interrupt request for an extended area overflow on the source address
14, 13
All 0
R
Reserved These bits are always read as 0 and cannot be modified.
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Section 10 DMA Controller (DMAC)
Bit 12 11 10 9 8
Bit Name SARA4 SARA3 SARA2 SARA1 SARA0
Initial Value 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
Description Source Address Extended Repeat Area Specify the extended repeat area on the source address (DSAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the SARIE bit set to 1, an interrupt can be requested. Table 10.3 shows the settings and areas of the extended repeat area.
7
DARIE
0
R/W
Destination Address Extended Repeat Area Overflow Interrupt Enable Enables/disables an interrupt request for an extended area overflow on the destination address. When an extended repeat area overflow on the destination address occurs while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate an interrupt by an extended repeat area overflow on the destination address is requested. When block transfer mode is used with the extended repeat area function, an interrupt is requested after completion of a 1-block size transfer. When setting the DTE bit in DMDR of the channel for which the transfer has been stopped to 1, the transfer is resumed from the state when the transfer is stopped. When the extended repeat area is not specified, this bit is ignored. 0: Disables an interrupt request for an extended area overflow on the destination address 1: Enables an interrupt request for an extended area overflow on the destination address
6, 5
All 0
R
Reserved These bits are always read as 0 and cannot be modified.
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Section 10 DMA Controller (DMAC)
Bit 4 3 2 1 0
Bit Name DARA4 DARA3 DARA2 DARA1 DARA0
Initial Value 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
Description Destination Address Extended Repeat Area Specify the extended repeat area on the destination address (DDAR). With the extended repeat area, the specified lower address bits are updated and the remaining upper address bits are fixed. The extended repeat area size is specified from four bytes to 128 Mbytes in units of byte and a power of 2. When the lower address is overflowed from the extended repeat area by address update, the address becomes the start address and the end address of the area for address addition and subtraction, respectively. When an overflow in the extended repeat area occurs with the DARIE bit set to 1, an interrupt can be requested. Table 10.3 shows the settings and areas of the extended repeat area.
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Section 10 DMA Controller (DMAC)
Table 10.3 Settings and Areas of Extended Repeat Area
SARA4 to SARA0 or DARA4 to DARA0 Extended Repeat Area 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 111xx [Legend] x: Don't care Not specified 2 bytes specified as extended repeat area by the lower 1 bit of the address 4 bytes specified as extended repeat area by the lower 2 bits of the address 8 bytes specified as extended repeat area by the lower 3 bits of the address 16 bytes specified as extended repeat area by the lower 4 bits of the address 32 bytes specified as extended repeat area by the lower 5 bits of the address 64 bytes specified as extended repeat area by the lower 6 bits of the address 128 bytes specified as extended repeat area by the lower 7 bits of the address 256 bytes specified as extended repeat area by the lower 8 bits of the address 512 bytes specified as extended repeat area by the lower 9 bits of the address 1 Kbyte specified as extended repeat area by the lower 10 bits of the address 2 Kbytes specified as extended repeat area by the lower 11 bits of the address 4 Kbytes specified as extended repeat area by the lower 12 bits of the address 8 Kbytes specified as extended repeat area by the lower 13 bits of the address 16 Kbytes specified as extended repeat area by the lower 14 bits of the address 32 Kbytes specified as extended repeat area by the lower 15 bits of the address 64 Kbytes specified as extended repeat area by the lower 16 bits of the address 128 Kbytes specified as extended repeat area by the lower 17 bits of the address 256 Kbytes specified as extended repeat area by the lower 18 bits of the address 512 Kbytes specified as extended repeat area by the lower 19 bits of the address 1 Mbyte specified as extended repeat area by the lower 20 bits of the address 2 Mbytes specified as extended repeat area by the lower 21 bits of the address 4 Mbytes specified as extended repeat area by the lower 22 bits of the address 8 Mbytes specified as extended repeat area by the lower 23 bits of the address 16 Mbytes specified as extended repeat area by the lower 24 bits of the address 32 Mbytes specified as extended repeat area by the lower 25 bits of the address 64 Mbytes specified as extended repeat area by the lower 26 bits of the address 128 Mbytes specified as extended repeat area by the lower 27 bits of the address Setting prohibited
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Section 10 DMA Controller (DMAC)
10.3.8
DMA Module Request Select Register (DMRSR)
DMRSR is an 8-bit readable/writable register that specifies the on-chip module interrupt source. The vector number of the interrupt source is specified in eight bits. However, 0 is regarded as no interrupt source. For the vector numbers of the interrupt sources, refer to table 10.5.
Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0
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Section 10 DMA Controller (DMAC)
10.4
Transfer Modes
Table 10.4 shows the DMAC transfer modes. The transfer modes can be specified to the individual channels. Table 10.4 Transfer Modes
Address Register Address Mode Transfer mode Dual address * * * Normal transfer Repeat transfer Block transfer Activation Source * Auto request (activated by CPU) On-chip module interrupt External request Common Function * Total transfer size: 1 to 4 Gbytes or not specified Offset addition Extended repeat area function DSAR/ DACK DACK/ DDAR Source DSAR Destination DDAR
Repeat or block size * = 1 to 65,536 bytes, 1 to 65,536 words, or * 1 to 65,536 longwords Single address *
* *
Instead of specifying the source or destination address registers, data is directly transferred from/to the external device using the DACK pin The same settings as above are available other than address register setting (e.g., above transfer modes can be specified) One transfer can be performed in one bus cycle (the types of transfer modes are the same as those of dual address modes)
* *
When the auto request setting is selected as the activation source, the cycle stealing or burst access can be selected. When the total transfer size is not specified (DTCR = H'00000000), the transfer counter is stopped and the transfer is continued without the limitation of the transfer count.
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Section 10 DMA Controller (DMAC)
10.5
10.5.1 (1)
Operations
Address Modes
Dual Address Mode
In dual address mode, the transfer source address is specified in DSAR and the transfer destination address is specified in DDAR. A transfer at a time is performed in two bus cycles (when the data bus width is less than the data access size or the access address is not aligned with the boundary of the data access size, the number of bus cycles are needed more than two because one bus cycle is divided into multiple bus cycles). In the first bus cycle, data at the transfer source address is read and in the next cycle, the read data is written to the transfer destination address. The read and write cycles are not separated. Other bus cycles (bus cycle by other bus masters, refresh cycle, and external bus release cycle) are not generated between read and write cycles. The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is output in two bus cycles. When an idle cycle is inserted before the bus cycle, the TEND signal is also output in the idle cycle. The DACK signal is not output. Figure 10.2 shows an example of the signal timing in dual address mode and figure 10.3 shows the operation in dual address mode.
DMA read cycle B Address bus RD WR TEND DSAR
DMA write cycle
DDAR
Figure 10.2 Example of Signal Timing in Dual Address Mode
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Section 10 DMA Controller (DMAC)
Address TA
Transfer
Address TB
Address BA
Address update setting is as follows: Source address increment Fixed destination address
Figure 10.3 Operations in Dual Address Mode (2) Single Address Mode
In single address mode, data between an external device and an external memory is directly transferred using the DACK pin instead of DSAR or DDAR. A transfer at a time is performed in one bus cycle. In this mode, the data bus width must be the same as the data access size. For details on the data bus width, see section 9, Bus Controller (BSC). The DMAC accesses an external device as the transfer source or destination by outputting the strobe signal (DACK) to the external device with DACK and accesses the other transfer target by outputting the address. Accordingly, the DMA transfer is performed in one bus cycle. Figure 10.4 shows an example of a transfer between an external memory and an external device with the DACK pin. In this example, the external device outputs data on the data bus and the data is written to the external memory in the same bus cycle. The transfer direction is decided by the DIRS bit in DACR which specifies an external device with the DACK pin as the transfer source or destination. When DIRS = 0, data is transferred from an external memory (DSAR) to an external device with the DACK pin. When DIRS = 1, data is transferred from an external device with the DACK pin to an external memory (DDAR). The settings of registers which are not used as the transfer source or destination are ignored. The DACK signal output is enabled in single address mode by the DACKE bit in DMDR. The DACK signal is low active. The TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is output in one bus cycle. When an idle cycle is inserted before the bus cycle, the TEND signal is also output in the idle cycle.
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Section 10 DMA Controller (DMAC)
Figure 10.5 shows an example of timing charts in single address mode and figure 10.6 shows an example of operation in single address mode.
External address bus LSI External memory External data bus
DMAC
External device with DACK DACK DREQ
Data flow
Figure 10.4 Data Flow in Single Address Mode
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Section 10 DMA Controller (DMAC)
Transfer from external memory to external device with DACK DMA cycle B Address bus RD WR DACK Data bus TEND Data output by external memory DSAR Address for external memory space RD signal for external memory space
High
Transfer from external device with DACK to external memory DMA cycle B Address bus RD WR DACK Data bus TEND Data output by external device with DACK DDAR Address for external memory space
High
WR signal for external memory space
Figure 10.5 Example of Signal Timing in Single Address Mode
Address T
Transfer
DACK
Address B
Figure 10.6 Operations in Single Address Mode
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Section 10 DMA Controller (DMAC)
10.5.2 (1)
Transfer Modes
Normal Transfer Mode
In normal transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. DBSR is ignored in normal transfer mode. The TEND signal is output only in the last DMA transfer. Figure 10.7 shows an example of the signal timing in normal transfer mode and figure 10.8 shows the operation in normal transfer mode.
Auto request transfer in dual address mode: DMA transfer cycle Bus cycle TEND External request transfer in single address mode: DREQ Bus cycle DACK DMA DMA Read Write Last DMA transfer cycle Read Write
Figure 10.7 Example of Signal Timing in Normal Transfer Mode
Address TA
Transfer
Address TB
Total transfer size (DTCR)
Address BA
Address BB
Figure 10.8 Operations in Normal Transfer Mode
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Section 10 DMA Controller (DMAC)
(2)
Repeat Transfer Mode
In repeat transfer mode, one data access size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as a total transfer size by DTCR. The repeat size can be specified in DBSR up to 65536 x data access size. The repeat area can be specified for the source or destination address side by bits ARS1 and ARS0 in DACR. The address specified as the repeat area returns to the transfer start address when the repeat size of transfers is completed. This operation is repeated until the total transfer size specified in DTCR is completed. When H'00000000 is specified in DTCR, it is regarded as the free running mode and repeat transfer is continued until the DTE bit in DMDR is cleared to 0. In addition, a DMA transfer can be stopped and a repeat size end interrupt can be requested to the CPU or DTC when the repeat size of transfers is completed. When the next transfer is requested after completion of a 1-repeat size data transfer while the RPTIE bit is set to 1, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1 to complete the transfer. At this time, an interrupt is requested to the CPU or DTC when the ESIE bit in DMDR is set to 1. The timing of the TEND signal is the same as in normal transfer mode. Figure 10.9 shows the operation in repeat transfer mode while dual address mode is set. When the repeat area is specified as neither source nor destination address side, the operation is the same as the normal transfer mode operation shown in figure 10.8. In this case, a repeat size end interrupt can also be requested to the CPU when the repeat size of transfers is completed.
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Section 10 DMA Controller (DMAC)
Address TA
Transfer
Address TB
Repeat size = BKSZH x data access size
Address BA Total transfer size (DTCR)
Operation when the repeat area is specified to the source side
Address BB
Figure 10.9 Operations in Repeat Transfer Mode (3) Block Transfer Mode
In block transfer mode, one block size of data is transferred at a single transfer request. Up to 4 Gbytes can be specified as total transfer size by DTCR. The block size can be specified in DBSR up to 64 k data access size. While one block of data is being transferred, transfer requests from other channels are suspended. When the transfer is completed, the bus is released to the other bus master. The block area can be specified for the source or destination address side by bits ARS1 and ARS0 in DACR. The address specified as the block area returns to the transfer start address when the block size of data is completed. When the block area is specified as neither source nor destination address side, the operation continues without returning the address to the transfer start address. A repeat size end interrupt can be requested. The TEND signal is output every time 1-block data is transferred in the last DMA transfer cycle. When an interrupt request by an extended repeat area overflow is used in block transfer mode, settings should be selected carefully. For details, see section 10.5.5, Extended Repeat Area Function.
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Section 10 DMA Controller (DMAC)
Figure 10.10 shows an example of the DMA transfer timing in block transfer mode. The transfer conditions are as follows: * Address mode: single address mode * Data access size: byte * 1-block size: three bytes The block transfer mode operations in single address mode and in dual address mode are shown in figures 10.11 and 10.12, respectively.
DREQ Transfer cycles for one block Bus cycle CPU CPU DMAC DMAC DMAC CPU
No CPU cycle generated TEND
Figure 10.10 Operations in Block Transfer Mode
Address T Block BKSZH x data access size Address B
Transfer
DACK
Figure 10.11 Operation in Single Address Mode in Block Transfer Mode (Block Area Specified)
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Section 10 DMA Controller (DMAC)
Address TA First block
BKSZH x data access size
Address TB Transfer First block
Second block
Second block
Total transfer size (DTCR)
Nth block
Nth block Address BB
Address BA
Figure 10.12 Operation in Dual Address Mode in Block Transfer Mode (Block Area Not Specified)
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Section 10 DMA Controller (DMAC)
10.5.3
Activation Sources
The DMAC is activated by an auto request, an on-chip module interrupt, and an external request. The activation source is specified by bits DTF1 and DTF0 in DMDR. (1) Activation by Auto Request
The auto request activation is used when a transfer request from an external device or an on-chip peripheral module is not generated such as a transfer between memory and memory or between memory and an on-chip peripheral module which does not request a transfer. A transfer request is automatically generated inside the DMAC. In auto request activation, setting the DTE bit in DMDR starts a transfer. The bus mode can be selected from cycle stealing and burst modes. (2) Activation by On-Chip Module Interrupt
An interrupt request from an on-chip peripheral module (on-chip peripheral module interrupt) is used as a transfer request. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by an on-chip module interrupt. The activation source of the on-chip module interrupt is selected by the DMA module request select register (DMRSR). The activation sources are specified to the individual channels. Table 10.5 is a list of on-chip module interrupts for the DMAC. The interrupt request selected as the activation source can generate an interrupt request simultaneously to the CPU or DTC. For details, refer to section 7, Interrupt Controller. The DMAC receives interrupt requests by on-chip peripheral modules independent of the interrupt controller. Therefore, the DMAC is not affected by priority given in the interrupt controller. When the DMAC is activated while DTA = 1, the interrupt request flag is automatically cleared by a DMA transfer. If multiple channels use a single transfer request as an activation source, when the channel having priority is activated, the interrupt request flag is cleared. In this case, other channels may not be activated because the transfer request is not held in the DMAC. When the DMAC is activated while DTA = 0, the interrupt request flag is not cleared by the DMAC and should be cleared by the CPU or DTC transfer. When an activation source is selected while DTE = 0, the activation source does not request a transfer to the DMAC. It requests an interrupt to the CPU or DTC. In addition, make sure that an interrupt request flag as an on-chip module interrupt source is cleared to 0 before writing 1 to the DTE bit.
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Section 10 DMA Controller (DMAC)
Table 10.5 List of On-chip module interrupts to DMAC
On-Chip Module A/D_0 TPU_0 TPU_1 TPU_2 TPU_3 TPU_4 TPU_5 SCI_0 SCI_0 SCI_1 SCI_1 SCI_2 SCI_2 SCI_4 SCI_4 TPU_6 TPU_7 TPU_8 TPU_9 TPU_10 TPU_11 SCI_5 SCI_5 SCI_6 SCI_6 USB USB A/D_1 DMRSR (Vector Number) 86 88 93 97 101 106 110 145 146 149 150 153 154 161 162 164 169 173 177 182 188 220 221 224 225 232 233 237
On-Chip Module Interrupt Source ADI0 (conversion end interrupt for A/D_0 converter unit 0) TGI0A (TGI0A input capture/compare match) TGI1A (TGI1A input capture/compare match) TGI2A (TGI2A input capture/compare match) TGI3A (TGI3A input capture/compare match) TGI4A (TGI4A input capture/compare match) TGI5A (TGI5A input capture/compare match) RXI0 (receive data full interrupt for SCI channel 0) TXI0 (transmit data empty interrupt for SCI channel 0) RXI1 (receive data full interrupt for SCI channel 1) TXI1 (transmit data empty interrupt for SCI channel 1) RXI2 (receive data full interrupt for SCI channel 2) TXI2 (transmit data empty interrupt for SCI channel 2) RXI4 (receive data full interrupt for SCI channel 4) TXI4 (transmit data empty interrupt for SCI channel 4) TGI6A (TGI6A input capture/compare match) TGI7A (TGI7A input capture/compare match) TGI8A (TGI8A input capture/compare match) TGI9A (TGI9A input capture/compare match) TGI10A (TGI10A input capture/compare match) TGI11A (TGI11A input capture/compare match) RXI5 (receive data full interrupt for SCI channel 5) TXI5 (transmit data empty interrupt for SCI channel 5) RXI6 (receive data full interrupt for SCI channel 6) TXI6 (transmit data empty interrupt for SCI channel 6) USBINTN0 (EP1FIFO full interrupt) USBINTN1 (EP2FIFO empty interrupt) ADI1 (conversion end interrupt for A/D converter unit 1)
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Section 10 DMA Controller (DMAC)
(3)
Activation by External Request
A transfer is started by a transfer request signal (DREQ) from an external device. When a DMA transfer is enabled (DTE = 1), the DMA transfer is started by the DREQ assertion. When a DMA transfer between on-chip peripheral modules is performed, select an activation source from the auto request and on-chip module interrupt (the external request cannot be used). A transfer request signal is input to the DREQ pin. The DREQ signal is detected on the falling edge or low level. Whether the falling edge or low level detection is used is selected by the DREQS bit in DMDR. When an external request is selected as an activation source, clear the DDR bit to 0 and set the ICR bit to 1 for the corresponding pin. For details, see section 13, I/O Ports. 10.5.4 Bus Access Modes
There are two types of bus access modes: cycle stealing and burst. When an activation source is the auto request, the cycle stealing or burst mode is selected by bit DTF0 in DMDR. When an activation source is the on-chip module interrupt or external request, the cycle stealing mode is selected. (1) Cycle Stealing Mode
In cycle stealing mode, the DMAC releases the bus every time one unit of transfers (byte, word, longword, or 1-block size) is completed. After that, when a transfer is requested, the DMAC obtains the bus to transfer 1-unit data and then releases the bus on completion of the transfer. This operation is continued until the transfer end condition is satisfied. When a transfer is requested to another channel during a DMA transfer, the DMAC releases the bus and then transfers data for the requested channel. For details on operations when a transfer is requested to multiple channels, see section 10.5.8, Priority of Channels.
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Section 10 DMA Controller (DMAC)
Figure 10.13 shows an example of timing in cycle stealing mode. The transfer conditions are as follows: * Address mode: Single address mode * Sampling method of the DREQ signal: Low level detection
DREQ
Bus cycle
CPU
CPU
DMAC
CPU
DMAC
CPU
Bus released temporarily for the CPU
Figure 10.13 Example of Timing in Cycle Stealing Mode (2) Burst Access Mode
In burst mode, once it takes the bus, the DMAC continues a transfer without releasing the bus until the transfer end condition is satisfied. Even if a transfer is requested from another channel having priority, the transfer is not stopped once it is started. The DMAC releases the bus in the next cycle after the transfer for the channel in burst mode is completed. This is similarly to operation in cycle stealing mode. However, setting the IBCCS bit in BCR2 of the bus controller makes the DMAC release the bus to pass the bus to another bus master. In block transfer mode, the burst mode setting is ignored (operation is the same as that in burst mode during one block of transfers). The DMAC is always operated in cycle stealing mode. Clearing the DTE bit in DMDR stops a DMA transfer. A transfer requested before the DTE bit is cleared to 0 by the DMAC is executed. When an interrupt by a transfer size error, a repeat size end, or an extended repeat area overflow occurs, the DTE bit is cleared to 0 and the transfer ends. Figure 10.14 shows an example of timing in burst mode.
Bus cycle
CPU
CPU
DMAC
DMAC
DMAC
CPU
CPU
No CPU cycle generated
Figure 10.14 Example of Timing in Burst Mode
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Section 10 DMA Controller (DMAC)
10.5.5
Extended Repeat Area Function
The source and destination address sides can be specified as the extended repeat area. The contents of the address register repeat addresses within the area specified as the extended repeat area. For example, to use a ring buffer as the transfer target, the contents of the address register should return to the start address of the buffer every time the contents reach the end address of the buffer (overflow on the ring buffer address). This operation can automatically be performed using the extended repeat area function of the DMAC. The extended repeat areas can be specified independently to the source address register (DSAR) and destination address register (DDAR). The extended repeat area on the source address is specified by bits SARA4 to SARA0 in DACR. The extended repeat area on the destination address is specified by bits DARA4 to DARA0 in DACR. The extended repeat area sizes for each side can be specified independently. A DMA transfer is stopped and an interrupt by an extended repeat area overflow can be requested to the CPU when the contents of the address register reach the end address of the extended repeat area. When an overflow on the extended repeat area set in DSAR occurs while the SARIE bit in DACR is set to 1, the ESIF bit in DMDR is set to 1 and the DTE bit in DMDR is cleared to 0 to stop the transfer. At this time, if the ESIE bit in DMDR is set to 1, an interrupt by an extended repeat area overflow is requested to the CPU. When the DARIE bit in DACR is set to 1, an overflow on the extended repeat area set in DDAR occurs, meaning that the destination side is a target. During the interrupt handling, setting the DTE bit in DMDR resumes the transfer.
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Section 10 DMA Controller (DMAC)
Figure 10.15 shows an example of the extended repeat area operation.
When the area represented by the lower three bits of DSAR (eight bytes) is specified as the extended repeat area (SARA4 to SARA0 = B'00011) External memory Area specified by DSAR H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 An interrupt request by extended repeat area overflow can be generated. Repeat
Figure 10.15 Example of Extended Repeat Area Operation When an interrupt by an extended repeat area overflow is used in block transfer mode, the following should be taken into consideration. When a transfer is stopped by an interrupt by an extended repeat area overflow, the address register must be set so that the block size is a power of 2 or the block size boundary is aligned with the extended repeat area boundary. When an overflow on the extended repeat area occurs during a transfer of one block, the interrupt by the overflow is suspended and the transfer overruns.
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...
...
Section 10 DMA Controller (DMAC)
Figure 10.16 shows examples when the extended repeat area function is used in block transfer mode.
When the are represented by the lower three bits (eight bytes) of DSAR are specified as the extended repeat area (SARA4 to SARA0 = 3) and the block size in block transfer mode is specified to 5 (bits 23 to 16 in DTCR = 5). External memory Area specified 1st block 2nd block by DSAR transfer transfer H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 Block transfer continued H'240000 H'240001 Interrupt request generated
Figure 10.16 Example of Extended Repeat Area Function in Block Transfer Mode
...
...
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Section 10 DMA Controller (DMAC)
10.5.6
Address Update Function using Offset
The source and destination addresses are updated by fixing, increment/decrement by 1, 2, or 4, or offset addition. When the offset addition is selected, the offset specified by the offset register (DOFR) is added to the address every time the DMAC transfers the data access size of data. This function realizes a data transfer where addresses are allocated to separated areas. Figure 10.17 shows the address update method.
External memory External memory External memory
0
1, 2, or 4 + offset
Address not updated
Data access size added to or subtracted from address (addresses are continuous) (b) Increment or decrement by 1, 2, or 4
Offset is added to address (addresses are not continuous) (c) Offset addition
(a) Address fixed
Figure 10.17 Address Update Method In item (a), Address fixed, the transfer source or destination address is not updated indicating the same address. In item (b), Increment or decrement by 1, 2, or 4, the transfer source or destination address is incremented or decremented by the value according to the data access size at each transfer. Byte, word, or longword can be specified as the data access size. The value of 1 for byte, 2 for word, and 4 for longword is used for updating the address. This operation realizes the data transfer placed in consecutive areas. In item (c), Offset addition, the address update does not depend on the data access size. The offset specified by DOFR is added to the address every time the DMAC transfers data of the data access size.
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Section 10 DMA Controller (DMAC)
The address is calculated by the offset set in DOFR and the contents of DSAR and DDAR. Although the DMAC calculates only addition, an offset subtraction can be realized by setting the negative value in DOFR. In this case, the negative value must be 2's complement. (1) Basic Transfer Using Offset
Figure 10.18 shows a basic operation of a transfer using the offset addition.
Data 1
Address A1 Transfer
Offset
Data 1 Data 2 Data 3 Data 4 Data 5 :
Address B1 Address B2 = Address B1 + 4 Address B3 = Address B2 + 4 Address B4 = Address B3 + 4 Address B5 = Address B4 + 4
Data 2
Address A2 = Address A1 + Offset : : :
Offset
Data 3
Address A3 = Address A2 + Offset
Offset Transfer source: Offset addition Transfer destination: Increment by 4 (longword) Address A4 = Address A3 + Offset
Data 4
Offset
Data 5
Address A5 = Address A4 + Offset
Figure 10.18 Operation of Offset Addition In figure 10.18, the offset addition is selected as the transfer source address update and increment or decrement by 1, 2, or 4 is selected as the transfer destination address. The address update means that data at the address which is away from the previous transfer source address by the offset is read from. The data read from the address away from the previous address is written to the consecutive area in the destination side.
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Section 10 DMA Controller (DMAC)
(2)
XY Conversion Using Offset
Figure 10.19 shows the XY conversion using the offset addition in repeat transfer mode.
Data 1 Data 5 Data 9 Data 13
Data 1 Data 2 Data 3 Data 4
Data 5 Data 6 Data 7 Data 8
Data 9 Data 10 Data 11 Data 12
Data 13 Data 14 Data 15 Data 16
1st transfer 2nd transfer Transfer 3rd transfer 4th transfer
Data 2 Data 6 Data 10 Data 14
Data 3 Data 7 Data 11 Data 15
Data 4 Data 8 Data 12 Data 16
1st transfer
Offset
Offset
Offset
Data 1 Data 5 Data 9 Data 13 Data 2 Data 6 Data 10 Data 14 Data 3 Data 7 Data 11 Data 15 Data 4 Data 8 Data 12 Data 16
2nd transfer Transfer source 3rd transfer addresses changed by CPU Data 1 Data 1 Data 5 Data 5 Address initialized Data 9 Data 9 Address initialized Data 13 Data 13 Data 2 Data 2 Data 6 Data 6 Data 10 Data 10 Data 14 Data 14 Data 3 Data 3 Data 7 Data 7 Data 11 Data 11 Data 15 Data 15 Data 4 Data 4 Data 8 Data 8 Interrupt request Data 12 Data 12 Interrupt generated request Data 16 Data 16 generated
Transfer
Transfer source addresses changed by CPU
Interrupt request generated
Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
1st transfer
2nd transfer
3rd transfer
4th transfer
Figure 10.19 XY Conversion Operation Using Offset Addition in Repeat Transfer Mode In figure 10.19, the source address side is specified to the repeat area by DACR and the offset addition is selected. The offset value is set to 4 x data access size (when the data access size is longword, H'00000010 is set in DOFR, as an example). The repeat size is set to 4 x data access size (when the data access size is longword, the repeat size is set to 4 x 4 = 16 bytes, as an example). The increment or decrement by 1, 2, or 4 is specified as the transfer destination address. A repeat size end interrupt is requested when the RPTIE bit in DACR is set to 1 and the repeat size of transfers is completed.
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Section 10 DMA Controller (DMAC)
When a transfer starts, the transfer source address is added to the offset every time data is transferred. The transfer data is written to the destination continuous addresses. When data 4 is transferred meaning that the repeat size of transfers is completed, the transfer source address returns to the transfer start address (address of data 1 on the transfer source) and a repeat size end interrupt is requested. While this interrupt stops the transfer temporarily, the contents of DSAR are written to the address of data 5 by the CPU (when the data access size is longword, write the data 1 address + 4). When the DTE bit in DMDR is set to 1, the transfer is resumed from the state when the transfer is stopped. Accordingly, operations are repeated and the transfer source data is transposed to the destination area (XY conversion). Figure 10.20 shows a flowchart of the XY conversion.
Start Set address and transfer count Set repeat transfer mode Enable repeat escape interrupt
Set DTE bit to 1
Receives transfer request Transfers data Decrements transfer count and repeat size No Transfer count = 0? No Yes Repeat size = 0? Yes Initializes transfer source address Generates repeat size end interrupt request Set transfer source address + 4 (Longword transfer) End : User operation : DMAC operation
Figure 10.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode
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Section 10 DMA Controller (DMAC)
(3)
Offset Subtraction
When setting the negative value in DOFR, the offset value must be 2's complement. The 2's complement is obtained by the following formula. 2's complement of offset = 1 + ~offset (~: bit inversion) Example: 2's complement of H'0001FFFF = H'FFFE0000 + H'00000001 = H'FFFE0001 The value of 2's complement can be obtained by the NEG.L instruction. 10.5.7 Register during DMA Transfer
The DMAC registers are updated by a DMA transfer. The value to be updated differs according to the other settings and transfer state. The registers to be updated are DSAR, DDAR, DTCR, bits BKSZH and BKSZ in DBSR, and the DTE, ACT, ERRF, ESIF, and DTIF bits in DMDR. (1) DMA Source Address Register
When the transfer source address set in DSAR is accessed, the contents of DSAR are output and then are updated to the next address. The increment or decrement can be specified by bits SAT1 and SAT0 in DACR. When SAT1 and SAT0 = B'00, the address is fixed. When SAT1 and SAT0 = B'01, the address is added with the offset. When SAT1 and SAT0 = B'10, the address is incremented. When SAT1 and SAT0 = B'11, the address is decremented. The size of increment or decrement depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the source address is word or longword, when the source address is not aligned with the word or longword boundary, the read bus cycle is divided into byte or word cycles. While data of one word or one longword is being read, the size of increment or decrement is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After one word or one longword of data is read, the address when the read cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0.
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Section 10 DMA Controller (DMAC)
In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the source address side, the source address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the source address side, operation follows the setting. The upper address bits are fixed and is not affected by the address update. While data is being transferred, DSAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DSAR during the transfer may be updated regardless of the access by the CPU. Moreover, DSAR for the channel being transferred must not be written to. (2) DMA Destination Address Register
When the transfer destination address set in DDAR is accessed, the contents of DDAR are output and then are updated to the next address. The increment or decrement can be specified by bits DAT1 and DAT0 in DACR. When DAT1 and DAT0 = B'00, the address is fixed. When DAT1 and DAT0 = B'01, the address is added with the offset. When DAT1 and DAT0 = B'10, the address is incremented. When DAT1 and DAT0 = B'11, the address is decremented. The incrementing or decrementing size depends on the data access size. The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0 = B'00, the data access size is byte and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the address is incremented or decremented by 4. Even if the access data size of the destination address is word or longword, when the destination address is not aligned with the word or longword boundary, the write bus cycle is divided into byte and word cycles. While one word or one longword of data is being written, the incrementing or decrementing size is changing according to the actual data access size, for example, +1 or +2 for byte or word data. After the one word or one longword of data is written, the address when the write cycle is started is incremented or decremented by the value according to bits SAT1 and SAT0. In block or repeat transfer mode, when the block or repeat size of data transfers is completed while the block or repeat area is specified to the destination address side, the destination address returns to the transfer start address and is not affected by the address update. When the extended repeat area is specified to the destination address side, operation follows the setting. The upper address bits are fixed and is not affected by the address update.
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Section 10 DMA Controller (DMAC)
While data is being transferred, DDAR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DDAR during the transfer may be updated regardless of the access by the CPU. Moreover, DDAR for the channel being transferred must not be written to. (3) DMA Transfer Count Register (DTCR)
A DMA transfer decrements the contents of DTCR by the transferred bytes. When byte data is transferred, DTCR is decremented by 1. When word data is transferred, DTCR is decremented by 2. When longword data is transferred, DTCR is decremented by 4. However, when DTCR = 0, the contents of DTCR are not changed since the number of transfers is not counted. While data is being transferred, all the bits of DTCR may be changed. DTCR must be accessed in longwords. If the upper word and lower word are read separately, incorrect data may be read from since the contents of DTCR during the transfer may be updated regardless of the access by the CPU. Moreover, DTCR for the channel being transferred must not be written to. When a conflict occurs between the address update by DMA transfer and write access by the CPU, the CPU has priority. When a conflict occurs between change from 1, 2, or 4 to 0 in DTCR and write access by the CPU (other than 0), the CPU has priority in writing to DTCR. However, the transfer is stopped. (4) DMA Block Size Register (DBSR)
DBSR is enabled in block or repeat transfer mode. Bits 31 to 16 in DBSR function as BKSZH and bits 15 to 0 in DBSR function as BKSZ. The BKSZH bits (16 bits) store the block size and repeat size and its value is not changed. The BKSZ bits (16 bits) function as a counter for the block size and repeat size and its value is decremented every transfer by 1. When the BKSZ value is to change from 1 to 0 by a DMA transfer, 0 is not stored but the BKSZH value is loaded into the BKSZ bits. Since the upper 16 bits of DBSR are not updated, DBSR can be accessed in words. DBSR for the channel being transferred must not be written to.
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Section 10 DMA Controller (DMAC)
(5)
DTE Bit in DMDR
Although the DTE bit in DMDR enables or disables data transfer by the CPU write access, it is automatically cleared to 0 according to the DMA transfer state by the DMAC. The conditions for clearing the DTE bit by the DMAC are as follows: * * * * * * * * * When the total size of transfers is completed When a transfer is completed by a transfer size error interrupt When a transfer is completed by a repeat size end interrupt When a transfer is completed by an extended repeat area overflow interrupt When a transfer is stopped by an NMI interrupt When a transfer is stopped by and address error Reset state Hardware standby mode When a transfer is stopped by writing 0 to the DTE bit
Writing to the registers for the channels when the corresponding DTE bit is set to 1 is prohibited (except for the DTE bit). When changing the register settings after writing 0 to the DTE bit, confirm that the DTE bit has been cleared to 0. Figure 10.21 show the procedure for changing the register settings for the channel being transferred.
Changing register settings of channel during operation Write 0 to DTE bit [1]
[1] Write 0 to the DTE bit in DMDR. [2] Read the DTE bit. [3] Confirm that DTE = 0. DTE = 1 indicates that DMA is transferring. [4] Write the desired values to the registers.
Read DTE bit
[2] [3]
DTE = 0? Yes Change register settings End of changing register settings
No
[4]
Figure 10.21 Procedure for Changing Register Setting For Channel being Transferred
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Section 10 DMA Controller (DMAC)
(6)
ACT Bit in DMDR
The ACT bit in DMDR indicates whether the DMAC is in the idle or active state. When DTE = 0 or DTE = 1 and the DMAC is waiting for a transfer request, the ACT bit is 0. Otherwise (the DMAC is in the active state), the ACT bit is 1. When individual transfers are stopped by writing 0 and the transfer is not completed, the ACT bit retains 1. In block transfer mode, even if individual transfers are stopped by writing 0 to the DTE bit, the 1block size of transfers is not stopped. The ACT bit retains 1 from writing 0 to the DTE bit to completion of a 1-block size transfer. In burst mode, up to three times of DMA transfer are performed from the cycle in which the DTE bit is written to 0. The ACT bit retains 1 from writing 0 to the DTE bit to completion of DMA transfer. (7) ERRF Bit in DMDR
When an address error or an NMI interrupt occur, the DMAC clears the DTE bits for all the channels to stop a transfer. In addition, it sets the ERRF bit in DMDR_0 to 1 to indicate that an address error or an NMI interrupt has occurred regardless of whether or not the DMAC is in operation. However, when the DMAC is in the module stop state, the ERRF bit is not set to 1 for address errors or the NMI. (8) ESIF Bit in DMDR
When an interrupt by an transfer size error, a repeat size end, or an extended repeat area overflow is requested, the ESIF bit in DMDR is set to 1. When both the ESIF and ESIE bits are set to 1, a transfer escape interrupt is requested to the CPU or DTC. The ESIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle of the interrupt source is completed. The ESIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 10.8, Interrupt Sources.
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Section 10 DMA Controller (DMAC)
(9)
DTIF Bit in DMDR
The DTIF bit in DMDR is set to 1 after the total transfer size of transfers is completed. When both the DTIF and DTIE bits in DMDR are set to 1, a transfer end interrupt by the transfer counter is requested to the CPU or DTC. The DTIF bit is set to 1 when the ACT bit in DMDR is cleared to 0 to stop a transfer after the bus cycle is completed. The DTIF bit is automatically cleared to 0 and a transfer request is cleared if the transfer is resumed by setting the DTE bit to 1 during interrupt handling. For details on interrupts, see section 10.8, Interrupt Sources. 10.5.8 Priority of Channels
The channels of the DMAC are given following priority levels: channel 0 > channel 1 > channel 2 > channel3. Table 10.6 shows the priority levels among the DMAC channels. Table 10.6 Priority among DMAC Channels
Channel Channel 0 Channel 1 Channel 2 Channel 3 Low Priority High
The channel having highest priority other than the channel being transferred is selected when a transfer is requested from other channels. The selected channel starts the transfer after the channel being transferred releases the bus. At this time, when a bus master other than the DMAC requests the bus, the cycle for the bus master is inserted. In a burst transfer or a block transfer, channels are not switched.
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Section 10 DMA Controller (DMAC)
Figure 10.22 shows a transfer example when multiple transfer requests from channels 0 to 2.
Channel 0 transfer Channel 1 transfer Channel 2 transfer
B
Address bus DMAC operation
Channel 0
Bus released
Channel 1
Bus released
Channel 2
Wait
Channel 0
Channel 1
Channel 2
Wait
Channel 0
Request cleared
Channel 1
Request cleared Request Selected retained Request Not Request retained selected retained Selected Request cleared
Channel 2
Figure 10.22 Example of Timing for Channel Priority
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Section 10 DMA Controller (DMAC)
10.5.9
DMA Basic Bus Cycle
Figure 10.23 shows an examples of signal timing of a basic bus cycle. In figure 10.23, data is transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When the bus mastership is passed from the DMAC to the CPU, data is read from the source address and it is written to the destination address. The bus is not released between the read and write cycles by other bus requests. DMAC bus cycles follows the bus controller settings.
CPU cycle T1 B Source address Address bus T2 T1
DMAC cycle (one word transfer) T2 T3 T1 T2 T3
CPU cycle
Destination address
RD
LHWR LLWR
High
Figure 10.23 Example of Bus Timing of DMA Transfer
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Section 10 DMA Controller (DMAC)
10.5.10 Bus Cycles in Dual Address Mode (1) Normal Transfer Mode (Cycle Stealing Mode)
In cycle stealing mode, the bus is released every time one transfer size of data (one byte, one word, or one longword) is completed. One bus cycle or more by the CPU or DTC are executed in the bus released cycles. In figure 10.24, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by cycle stealing.
DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle
B
Address bus
RD
LHWR, LLWR
TEND
Bus released
Bus released
Bus released
Last transfer cycle
Bus released
Figure 10.24 Example of Transfer in Normal Transfer Mode by Cycle Stealing In figures 10.25 and 10.26, the TEND signal output is enabled and data is transferred in longwords from the external 16-bit 2-state access space to the 16-bit 2-state access space in normal transfer mode by cycle stealing. In figure 10.25, the transfer source (DSAR) is not aligned with a longword boundary and the transfer destination (DDAR) is aligned with a longword boundary. In figure 10.26, the transfer source (DSAR) is aligned with a longword boundary and the transfer destination (DDAR) is not aligned with a longword boundary.
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Section 10 DMA Controller (DMAC)
DMA byte read cycle
DMA word read cycle
DMA byte read cycle
DMA word write cycle
DMA word write cycle
DMA byte read cycle
DMA word read cycle
DMA byte read cycle
DMA word write cycle
DMA word write cycle
B Address bus RD LHWR LLWR TEND 4m + 1 4m + 2 4m + 4 4n 4n +2 4m + 5 4m + 6 4m + 8 4n + 4 4n + 6
Bus released
Bus released
Last transfer cycle
Bus released m and n are integers.
Figure 10.25 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Source DSAR = Odd Address and Source Address Increment)
DMA word read cycle DMA word read cycle DMA byte write cycle DMA word write cycle DMA byte write cycle DMA word read cycle DMA word read cycle DMA byte write cycle DMA word write cycle DMA byte write cycle
B Address bus RD LHWR LLWR TEND 4m 4m + 2 4n + 5 4n + 6 4n + 8 4m + 4 4m + 6 4n + 1 4n + 2 4n + 4
Bus released
Bus released
Last transfer cycle
Bus released
m and n are integers.
Figure 10.26 Example of Transfer in Normal Transfer Mode by Cycle Stealing (Transfer Destination DDAR = Odd Address and Destination Address Decrement)
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Section 10 DMA Controller (DMAC)
(2)
Normal Transfer Mode (Burst Mode)
In burst mode, one byte, one word, or one longword of data continues to be transferred until the transfer end condition is satisfied. When a burst transfer starts, a transfer request from a channel having priority is suspended until the burst transfer is completed. In figure 10.27, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in normal transfer mode by burst access.
DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle
B
Address bus
RD
LHWR, LLWR
TEND Last transfer cycle Burst transfer
Bus released
Bus released
Figure 10.27 Example of Transfer in Normal Transfer Mode by Burst Access
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Section 10 DMA Controller (DMAC)
(3)
Block Transfer Mode
In block transfer mode, the bus is released every time a 1-block size of transfers at a single transfer request is completed. In figure 10.28, the TEND signal output is enabled and data is transferred in words from the external 16-bit 2-state access space to the external 16-bit 2-state access space in block transfer mode.
DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle DMA read cycle DMA write cycle
B
Address bus
RD
LHWR, LLWR TEND
Bus released
Block transfer
Bus released
Last block transfer cycle
Bus released
Figure 10.28 Example of Transfer in Block Transfer Mode
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Section 10 DMA Controller (DMAC)
(4)
Activation Timing by DREQ Falling Edge
Figure 10.29 shows an example of normal transfer mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If a high level of the DREQ signal has been detected until completion of the DMA write cycle, receiving the next transfer request resumes and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed.
DMA read cycle DMA write cycle DMA read cycle DMA write cycle
Bus released
Bus released
Bus released
B
DREQ
Address bus DMA operation
Wait
Transfer source Transfer destination
Transfer source Transfer destination
Read
Write
Wait
Read
Write
Wait
Channel
Request
Duration of transfer request disabled
Request
Duration of transfer request disabled
Min. of 3 cycles
Min. of 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Transfer request enable resumed [1]
Transfer request enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the B signal is started to detect a high level of the DREQ signal. [4][7] When a high level of the DREQ signal has been detected, transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].)
Figure 10.29 Example of Transfer in Normal Transfer Mode Activated by DREQ Falling Edge
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Section 10 DMA Controller (DMAC)
Figure 10.30 shows an example of block transfer mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If a high level of the DREQ signal has been detected until completion of the DMA write cycle, receiving the next transfer request resumes and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed.
1-block transfer 1-block transfer
Bus released
DMA read cycle
DMA write cycle
Bus released
DMA read cycle
DMA write cycle
Bus released
B
DREQ
Address bus DMA operation
Wait
Transfer source Transfer destination
Transfer source Transfer destination
Read
Write
Wait
Read
Write
Wait
Channel
Request
Duration of transfer request disabled
Request
Duration of transfer request disabled
Min. of 3 cycles
Min. of 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Transfer request enable resumed [1]
Transfer request enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the B signal is started to detect a high level of the DREQ signal. [4][7] When a high level of the DREQ signal has been detected, transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].)
Figure 10.30 Example of Transfer in Block Transfer Mode Activated by DREQ Falling Edge
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Section 10 DMA Controller (DMAC)
(5)
Activation Timing by DREQ low Level
Figure 10.31 shows an example of normal transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed.
DMA read cycle DMA write cycle DMA read cycle DMA write cycle
Bus released
Bus released
Bus released
B
DREQ
Address bus DMA operation Wait Read
Transfer source Write
Transfer destination Wait Read
Transfer source Write
Transfer destination Wait
Channel
Request
Duration of transfer request disabled
Request
Duration of transfer request disabled
Min. of 3 cycles
Min. of 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Transfer request enable resumed [1]
Transfer request enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].)
Figure 10.31 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level
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Section 10 DMA Controller (DMAC)
Figure 10.32 shows an example of block transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed.
1-block transfer Bus released DMA read cycle DMA write cycle Bus released 1-block transfer DMA read cycle DMA write cycle Bus released
B
DREQ
Address bus DMA operation Wait
Read
Transfer source
Transfer destination
Transfer source
Transfer destination
Write
Wait
Read
Write
Wait
Channel
Request
Duration of transfer request disabled
Request
Duration of transfer request disabled
Min. of 3 cycles
Min. of 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Transfer request enable resumed [1]
Transfer request enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].)
Figure 10.32 Example of Transfer in Block Transfer Mode Activated by DREQ Low Level
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Section 10 DMA Controller (DMAC)
(6)
Activation Timing by DREQ Low Level with NRD = 1
When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is delayed for one cycle. Figure 10.33 shows an example of normal transfer mode activated by the DREQ signal low level with NRD = 1. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the write cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed.
DMA read cycle DMA write cycle DMA read cycle DMA write cycle
Bus released
Bus released
Bus released
B
DREQ Address bus
Transfer source Transfer destination Transfer source Transfer destination
Channel
Request
Duration of transfer request disabled
Duration of transfer request disabled which is extended by NRD
Request
Duration of transfer request disabled
Duration of transfer request disabled which is extended by NRD
Min. of 3 cycles
Min. of 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Transfer request enable resumed
Transfer request enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed one cycle after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].) [1]
Figure 10.33 Example of Transfer in Normal Transfer Mode Activated by DREQ Low Level with NRD = 1
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Section 10 DMA Controller (DMAC)
10.5.11 Bus Cycles in Single Address Mode (1) Single Address Mode (Read and Cycle Stealing)
In single address mode, one byte, one word, or one longword of data is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU or DTC are executed in the bus released cycles. In figure 10.34, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (read).
DMA read cycle B Address bus RD DACK TEND
Bus released Bus released Bus released Bus Last transfer Bus released released cycle
DMA read cycle
DMA read cycle
DMA read cycle
Figure 10.34 Example of Transfer in Single Address Mode (Byte Read)
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Section 10 DMA Controller (DMAC)
(2)
Single Address Mode (Write and Cycle Stealing)
In single address mode, data of one byte, one word, or one longword is transferred at a single transfer request and after the transfer the bus is released temporarily. One bus cycle or more by the CPU or DTC are executed in the bus released cycles. In figure 10.35, the TEND signal output is enabled and data is transferred in bytes from the external 8-bit 2-state access space to the external device in single address mode (write).
DMA write cycle B DMA write cycle DMA write cycle DMA write cycle
Address bus
LLWR
DACK TEND Last transfer Bus Bus cycle released released
Bus released
Bus released
Bus released
Figure 10.35 Example of Transfer in Single Address Mode (Byte Write)
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Section 10 DMA Controller (DMAC)
(3)
Activation Timing by DREQ Falling Edge
Figure 10.36 shows an example of single address mode activated by the DREQ signal falling edge. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared and starts detecting a high level of the DREQ signal for falling edge detection. If a high level of the DREQ signal has been detected until completion of the single cycle, receiving the next transfer request resumes and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed.
Bus released B DMA single cycle Bus released DMA single cycle Bus released
DREQ
Address bus
Transfer source/ Transfer destination
Transfer source/ Transfer destination
DACK DMA operation Wait Single Wait Single Wait
Channel
Request
Duration of transfer request disabled
Request
Duration of transfer request disabled
Min. of 3 cycles
Min. of 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Transfer request enable resumed [1]
Transfer request enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started and sampling the DREQ signal at the rising edge of the B signal is started to detect a high level of the DREQ signal. [4][7] When a high level of the DREQ signal has been detected, transfer enable is resumed after completion of the write cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].)
Figure 10.36 Example of Transfer in Single Address Mode Activated by DREQ Falling Edge
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Section 10 DMA Controller (DMAC)
(4)
Activation Timing by DREQ Low Level
Figure 10.37 shows an example of normal transfer mode activated by the DREQ signal low level. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after completion of the single cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed.
Bus released B DMA single cycle Bus released DMA single cycle Bus released
DREQ
Address bus DACK DMA Wait operation
Transfer source/ Transfer destination
Transfer source/ Transfer destination
Single
Wait
Single
Wait
Channel
Request
Duration of transfer request disabled
Request
Duration of transfer request disabled
Min. of 3 cycles
Min. of 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Transfer request enable resumed [1]
Transfer request enable resumed
After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed after completion of the single cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].)
Figure 10.37 Example of Transfer in Single Address Mode Activated by DREQ Low Level
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Section 10 DMA Controller (DMAC)
(5)
Activation Timing by DREQ Low Level with NRD = 1
When the NRD bit in DMDR is set to 1, the timing of receiving the next transfer request is delayed for one cycle. Figure 10.38 shows an example of single address mode activated by the DREQ signal low level with NRD = 1. The DREQ signal is sampled every cycle from the next rising edge of the B signal immediately after the DTE bit write cycle. When a low level of the DREQ signal is detected while a transfer request by the DREQ signal is enabled, a transfer request is held in the DMAC. When the DMAC is activated, the transfer request is cleared. Receiving the next transfer request resumes after one cycle of the transfer request duration inserted by NRD = 1 on completion of the single cycle and then a low level of the DREQ signal is detected. This operation is repeated until the transfer is completed.
Bus released DMA single cycle Bus released DMA single cycle Bus released
B
DREQ Address bus
Transfer source/ Transfer destination Transfer source/ Transfer destination
Channel
Request
Duration of transfer request disabled which is extended by NRD Duration of transfer Request request disabled
Duration of transfer request disabled which is extended by NRD Duration of transfer request disabled
Min. of 3 cycles
Min. of 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Transfer request enable resumed
Transfer request enable resumed
[1] After DMA transfer request is enabled, a low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. [2][5] The DMAC is activated and the transfer request is cleared. [3][6] A DMA cycle is started. [4][7] Transfer request enable is resumed one cycle after completion of the single cycle. (A low level of the DREQ signal is detected at the rising edge of the B signal and a transfer request is held. This is the same as [1].)
Figure 10.38 Example of Transfer in Single Address Mode Activated by DREQ Low Level with NRD = 1
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Section 10 DMA Controller (DMAC)
10.6
DMA Transfer End
Operations on completion of a transfer differ according to the transfer end condition. DMA transfer completion is indicated that the DTE and ACT bits in DMDR are changed from 1 to 0. (1) Transfer End by DTCR Change from 1, 2, or 4, to 0
When DTCR is changed from 1, 2, or 4 to 0, a DMA transfer for the channel is completed. The DTE bit in DMDR is cleared to 0 and the DTIF bit in DMDR is set to 1. At this time, when the DTIE bit in DMDR is set to 1, a transfer end interrupt by the transfer counter is requested. When the DTCR value is 0 before the transfer, the transfer is not stopped. (2) Transfer End by Transfer Size Error Interrupt
When the following conditions are satisfied while the TSEIE bit in DMDR is set to 1, a transfer size error occurs and a DMA transfer is terminated. At this time, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1. * In normal transfer mode and repeat transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the data access size * In block transfer mode, when the next transfer is requested while a transfer is disabled due to the DTCR value less than the block size When the TSEIE bit in DMDR is cleared to 0, data is transferred until the DTCR value reaches 0. A transfer size error is not generated. Operation in each transfer mode is shown below. * In normal transfer mode and repeat transfer mode, when the DTCR value is less than the data access size, data is transferred in bytes * In block transfer mode, when the DTCR value is less than the block size, the specified size of data in DTCR is transferred instead of transferring the block size of data. The transfer is performed in bytes.
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Section 10 DMA Controller (DMAC)
(3)
Transfer End by Repeat Size End Interrupt
In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat size data transfer while the RPTIE bit in DACR is set to 1, a repeat size end interrupt is requested. When the interrupt is requested to complete DMA transfer, the DTE bit in DMDR is cleared to 0 and the ESIF bit in DMDR is set to 1. Under this condition, setting the DTE bit to 1 resumes the transfer. In block transfer mode, when the next transfer is requested after completion of a 1-block size data transfer, a repeat size end interrupt can be requested. (4) Transfer End by Interrupt on Extended Repeat Area Overflow
When an overflow on the extended repeat area occurs while the extended repeat area is specified and the SARIE or DARIE bit in DACR is set to 1, an interrupt by an extended repeat area overflow is requested. When the interrupt is requested, the DMA transfer is terminated, the DTE bit in DMDR is cleared to 0, and the ESIF bit in DMDR is set to 1. In dual address mode, even if an interrupt by an extended repeat area overflow occurs during a read cycle, the following write cycle is performed. In block transfer mode, even if an interrupt by an extended repeat area overflow occurs during a 1block transfer, the remaining data is transferred. The transfer is not terminated by an extended repeat area overflow interrupt unless the current transfer is complete. (5) Transfer End by Clearing DTE Bit in DMDR
When the DTE bit in DMDR is cleared to 0 by the CPU, a transfer is completed after the current DMA cycle and a DMA cycle in which the transfer request is accepted are completed. In block transfer mode, a DMA transfer is completed after 1-block data is transferred.
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Section 10 DMA Controller (DMAC)
(6)
Transfer End by NMI Interrupt
When an NMI interrupt is requested, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an NMI interrupt is requested during a DMA transfer, the transfer is forced to stop. To perform DMA transfer after an NMI interrupt is requested, clear the ERRF bit to 0 and then set the DTE bits for the channels to 1. The transfer end timings after an NMI interrupt is requested are shown below. (a) Normal Transfer Mode and Repeat Transfer Mode
In dual address mode, a DMA transfer is completed after completion of the write cycle for one transfer unit. In single address mode, a DMA transfer is completed after completion of the bus cycle for one transfer unit. (b) Block Transfer Mode
A DMA transfer is forced to stop. Since a 1-block size of transfers is not completed, operation is not guaranteed. In dual address mode, the write cycle corresponding to the read cycle is performed. This is similar to (a) in normal transfer mode. (7) Transfer End by Address Error
When an address error occurs, the DTE bits for all the channels are cleared to 0 and the ERRF bit in DMDR_0 is set to 1. When an address error occurs during a DMA transfer, the transfer is forced to stop. To perform a DMA transfer after an address error occurs, clear the ERRF bit to 0 and then set the DTE bits for the channels. The transfer end timing after an address error is the same as that after an NMI interrupt. (8) Transfer End by Hardware Standby Mode or Reset
The DMAC is initialized by a reset and a transition to the hardware standby mode. A DMA transfer is not guaranteed.
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Section 10 DMA Controller (DMAC)
10.7
10.7.1
Relationship among DMAC and Other Bus Masters
CPU Priority Control Function Over DMAC
The CPU priority control function over DMAC can be used according to the CPU priority control register (CPUPCR) setting. For details, see section 7.7, CPU Priority Control Function Over DTC, DMAC, and EXDMAC. The priority level of the DMAC is specified by bits DMAP2 to DMAP0 and can be specified for each channel. The priority level of the CPU is specified by bits CPUP2 to CPUP0. The value of bits CPUP2 to CPUP0 is updated according to the exception handling priority. If the CPU priority control is enabled by the CPUPCE bit in CPUPCR, when the CPU has priority over the DMAC, a transfer request for the corresponding channel is masked and the transfer is not activated. When another channel has priority over or the same as the CPU, a transfer request is received regardless of the priority between channels and the transfer is activated. The transfer request masked by the CPU priority control function is suspended. When the transfer channel is given priority over the CPU by changing priority levels of the CPU or channel, the transfer request is received and the transfer is resumed. Writing 0 to the DTE bit clears the suspended transfer request. When the CPUPCE bit is cleared to 0, it is regarded as the lowest priority.
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Section 10 DMA Controller (DMAC)
10.7.2
Bus Arbitration among DMAC and Other Bus Masters
When DMA transfer cycles are consecutively performed, bus cycles of other bus masters may be inserted between the transfer cycles. The DMAC can release the bus temporarily to pass the bus to other bus masters. The consecutive DMA transfer cycles may not be divided according to the transfer mode settings to achieve high-speed access. The read and write cycles of a DMA transfer are not separated. Refreshing, external bus release, and on-chip bus master (CPU, DTC, or EXDMAC) cycles are not inserted between the read and write cycles of a DMA transfer. In block transfer mode and an auto request transfer by burst access, bus cycles of the DMA transfer are consecutively performed. For this duration, since the DMAC has priority over the CPU and DTC, accesses to the external space is suspended (the IBCCS bit in the bus control register 2 (BCR2) is cleared to 0). When the bus is passed to another channel or an auto request transfer by cycle stealing, bus cycles of the DMAC and on-chip bus master are performed alternatively. When the arbitration function among the DMAC and on-chip bus masters is enabled by setting the IBCCS bit in BCR2, the bus is used alternatively except the bus cycles which are not separated. For details, see section 9, Bus Controller (BSC). A conflict may occur between external space access of the DMAC and a refreshing cycle, EXDMAC cycle, or external bus release cycle. Even if a burst or block transfer is performed by the DMAC, the transfer is stopped temporarily and a refreshing cycle, EXDMAC cycle, or an external bus release cycle is inserted by the BSC according to the external bus priority (when the CPU external access and the DTC external access do not have priority over a DMAC transfer, the transfers are not operated until the DMAC releases the bus). In dual address mode, the DMAC releases the external bus after the external space write cycle. Since the read and write cycles are not separated, the bus is not released. An internal space (on-chip memory and internal I/O registers) access of the DMAC and refreshing cycle, EXDMAC cycle, or an external bus release cycle may be performed at the same time.
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Section 10 DMA Controller (DMAC)
10.8
Interrupt Sources
The DMAC interrupt sources are a transfer end interrupt by the transfer counter and a transfer escape end interrupt which is generated when a transfer is terminated before the transfer counter reaches 0. Table 10.7 shows interrupt sources and priority. Table 10.7 Interrupt Sources and Priority
Abbr. DMTEND0 DMTEND1 DMTEND2 DMTEND3 DMEEND0 Interrupt Sources Transfer end interrupt by channel 0 transfer counter Transfer end interrupt by channel 1 transfer counter Transfer end interrupt by channel 2 transfer counter Transfer end interrupt by channel 3 transfer counter Interrupt by channel 0 transfer size error Interrupt by channel 0 repeat size end Interrupt by channel 0 extended repeat area overflow on source address Interrupt by channel 0 extended repeat area overflow on destination address DMEEND1 Interrupt by channel 1 transfer size error Interrupt by channel 1 repeat size end Interrupt by channel 1 extended repeat area overflow on source address Interrupt by channel 1 extended repeat area overflow on destination address DMEEND2 Interrupt by channel 2 transfer size error Interrupt by channel 2 repeat size end Interrupt by channel 2 extended repeat area overflow on source address Interrupt by channel 2 extended repeat area overflow on destination address DMEEND3 Interrupt by channel 3 transfer size error Interrupt by channel 3 repeat size end Interrupt by channel 3 extended repeat area overflow on source address Interrupt by channel 3 extended repeat area overflow on destination address Low Priority High
Each interrupt is enabled or disabled by the DTIE and ESIE bits in DMDR for the corresponding channel. A DMTEND interrupt is generated by the combination of the DTIF and DTIE bits in DMDR. A DMEEND interrupt is generated by the combination of the ESIF and ESIE bits in DMDR. The DMEEND interrupt sources are not distinguished. The priority among channels are decided by the interrupt controller and it is shown in table 10.7. For details, see section 7, Interrupt Controller.
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Section 10 DMA Controller (DMAC)
Each interrupt source is specified by the interrupt enable bit in the register for the corresponding channel. A transfer end interrupt by the transfer counter, a transfer size error interrupt, a repeat size end interrupt, an interrupt by an extended repeat area overflow on the source address, and an interrupt by an extended repeat area overflow on the destination address are enabled or disabled by the DTIE bit in DMDR, the TSEIE bit in DMDR, the RPTIE bit in DACR, SARIE bit in DACR, and the DARIE bit in DACR, respectively. A transfer end interrupt by the transfer counter is generated when the DTIF bit in DMDR is set to 1. The DTIF bit is set to 1 when DTCR becomes 0 by a transfer while the DTIE bit in DMDR is set to 1. An interrupt other than the transfer end interrupt by the transfer counter is generated when the ESIF bit in DMDR is set to 1. The ESIF bit is set to 1 when the conditions are satisfied by a transfer while the enable bit is set to 1. A transfer size error interrupt is generated when the next transfer cannot be performed because the DTCR value is less than the data access size, meaning that the data access size of transfers cannot be performed. In block transfer mode, the block size is compared with the DTCR value for transfer error decision. A repeat size end interrupt is generated when the next transfer is requested after completion of the repeat size of transfers in repeat transfer mode. Even when the repeat area is not specified in the address register, the transfer can be stopped periodically according to the repeat size. At this time, when a transfer end interrupt by the transfer counter is generated, the ESIF bit is set to 1. An interrupt by an extended repeat area overflow on the source and destination addresses is generated when the address exceeds the extended repeat area (overflow). At this time, when a transfer end interrupt by the transfer counter, the ESIF bit is set to 1. Figure 10.39 is a block diagram of interrupts and interrupt flags. To clear an interrupt, clear the DTIF or ESIF bit in DMDR to 0 in the interrupt handling routine or continue the transfer by setting the DTE bit in DMDR after setting the register. Figure 10.40 shows procedure to resume the transfer by clearing a interrupt.
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Section 10 DMA Controller (DMAC)
TSIE bit DMAC is activated in transfer size error state RPTIE bit DMAC is activated after BKSZ bits are changed from 1 to 0 SARIE bit Extended repeat area overflow occurs in source address DARIE bit Extended repeat area overflow occurs in destination address
DTIE bit DTIF bit [Setting condition] When DTCR becomes 0 and transfer ends ESIE bit ESIF bit Transfer escape end interrupt Transfer end interrupt
Setting condition is satisfied
Figure 10.39 Interrupt and Interrupt Sources
Transfer end interrupt handling routine
Consecutive transfer processing Registers are specified DTE bit is set to 1 Interrupt handling routine ends (RTE instruction executed) [1] [2] [3]
Transfer resumed after interrupt handling routine DTIF and ESIF bits are cleared to 0 Interrupt handling routine ends Registers are specified DTE bit is set to 1 [4]
[5] [6] [7]
Transfer resume processing end Transfer resume processing end [1] Specify the values in the registers such as transfer counter and address register. [2] Set the DTE bit in DMDR to 1 to resume DMA operation. Setting the DTE bit to 1 automatically clears the DTIF or ESIF bit in DMDR to 0 and an interrupt source is cleared. [3] End the interrupt handling routine by the RTE instruction. [4] Read that the DTIF or the ESIF bit in DMDR = 1 and then write 0 to the bit. [5] Complete the interrupt handling routine and clear the interrupt mask. [6] Specify the values in the registers such as transfer counter and address register. [7] Set the DTE bit to 1 to resume DMA operation.
Figure 10.40 Procedure Example of Resuming Transfer by Clearing Interrupt Source
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Section 10 DMA Controller (DMAC)
10.9
Usage Notes
1. DMAC Register Access During Operation Except for clearing the DTE bit in DMDR, the settings for channels being transferred (including waiting state) must not be changed. The register settings must be changed during the transfer prohibited state. 2. Settings of Module Stop Function The DMAC operation can be enabled or disabled by the module stop control register. The DMAC is enabled by the initial value. Setting bit MSTPA13 in MSTPCRA stops the clock supplied to the DMAC and the DMAC enters the module stop state. However, when a transfer for a channel is enabled or when an interrupt is being requested, bit MSTPA13 cannot be set to 1. Clear the DTE bit to 0, clear the DTIF or DTIE bit in DMDR to 0, and then set bit MSTPA13. When the clock is stopped, the DMAC registers cannot be accessed. However, the following register settings are valid in the module stop state. Disable them before entering the module stop state, if necessary. TENDE bit in DMDR is 1 (the TEND signal output enabled) DACKE bit in DMDR is 1 (the DACK signal output enabled) 3. Activation by DREQ Falling Edge The DREQ falling edge detection is synchronized with the DMAC internal operation. A. Activation request waiting state: Waiting for detecting the DREQ low level. A transition to 2. is made. B. Transfer waiting state: Waiting for a DMAC transfer. A transition to 3. is made. C. Transfer prohibited state: Waiting for detecting the DREQ high level. A transition to 1. is made. After a DMAC transfer enabled, a transition to 1. is made. Therefore, the DREQ signal is sampled by low level detection at the first activation after a DMAC transfer enabled. 4. Acceptation of Activation Source At the beginning of an activation source reception, a low level is detected regardless of the setting of DREQ falling edge or low level detection. Therefore, if the DREQ signal is driven low before setting DMDR, the low level is received as a transfer request. When the DMAC is activated, clear the DREQ signal of the previous transfer.
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Section 11 EXDMA Controller (EXDMAC)
Section 11 EXDMA Controller (EXDMAC)
This LSI has an on-chip four-channel external bus transfer DMA controller (EXDMAC). The EXDMAC can carry out high-speed data transfer, in place of the CPU, to and from external devices and external memory. Also, the EXDMAC allows external bus transfer in parallel with the internal CPU operation when there is no external bus request from a controller other than the EXDMAC.
11.1
Features
* Up to 4-Gbyte address space accessible * Selection of byte, word, or longword transfer data length * Total transfer size of up to 4 Gbytes (4,294,967,295 bytes) Selection of free-running mode (with no total transfer size specified) * Selection of auto-requests or external requests for activating the EXDMAC Auto-request: Activation from the CPU (Cycle steal mode or burst mode can be selected.) External request: Low level sensing or falling edge sensing for the EDREQ signal can be selected. Only channel 0 or 1 can accept external requests. * Selection of dual address mode or single address mode Dual address mode: Both the transfer source and destination addresses are specified to transfer data. Single address mode: The EDACK signal is used to access the transfer source or destination peripheral device and the address of the other device is specified to transfer data. Only channel 0 or 1 can be selected for single address mode. * Normal, repeat, block, or cluster transfer (only for the EXDMAC) can be selected as transfer mode Normal transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat transfer mode: One byte, one word, or one longword data is transferred at a single transfer request Repeat size of data is transferred and then a transfer address returns to the transfer start address Up to 64-kbyte transfers can be set as repeat size (65,536 bytes/words/longwords)
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Section 11 EXDMA Controller (EXDMAC)
Block transfer mode:
*
*
*
*
* * *
One block data is transferred at a single transfer request Up to 64-kbyte data can be set as block size (65,536 bytes/words/longwords) Cluster transfer mode: One cluster data is transferred at a single transfer request Up to 32-byte data can be set as cluster size Selection of extended repeat area function (to transfer data such as ring buffer data by fixing the upper bit value in the transfer address register and repeating the address values in a specified range) For the extended repeat area, 1 bit (2 bytes) to 27 bits (128 Mbytes) can be set independently for the transfer source or destination. Selection of address update methods: Increment/decrement by 1, 2 or 4, fixed, or offset addition When offset addition is used to update addresses, the mid-addresses can be skipped during data transfer. Transfer of word or longword data to addresses beyond each data boundary Data can be divided into an optimal data size (byte or word) according to addresses when transferring data. Two kinds of interrupts requested to the CPU Transfer end interrupt: Requested after the number of data set by the transfer counter has been completely transferred Transfer escape end interrupt: Requested when the remaining transfer size is smaller than the size set for a single transfer request, after a repeat-size transfer is completed, or when an extended repeat area overflow occurs. Acceptance of a transfer request can be reported to an external device via the EDRAK pin (only for the EXDMAC). Operation of EXDMAC, connected to a dedicated bus, in parallel with a bus master such as the CPU, DTC, or DMAC (only for the EXDMAC). Module stop state can be set.
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Section 11 EXDMA Controller (EXDMAC)
Figure 11.1 shows a block diagram of the EXDMAC.
Internal address bus External pins EDREQm
Internal data bus
Data buffer
EDACKm ETENDm EDRAKm
Interrupt request signals to CPU for individual channels Control unit Address buffer
CLSBR0 CLSBR1
Processor Processor
CLSBR2
. . .
EDOFR_n EDSAR_n EDDAR_n EDMDR_n EDACR_n EDTCR_n EDBSR_n
CLSBR7
Module data bus
[Legend]
EDSAR_n: EDDAR_n: EDOFR_n: EDTCR_n: EDBSR_n: EDMDR_n: EDACR_n: CLSBR0 to CLSBR7:
EXDMA source address register EXDMA destination address register EXDMA offset register EXDMA transfer count register EXDMA block size register EXDMA mode control register EXDMA address control register Cluster buffer registers 0 to 7
EDREQm: EXDMA transfer request EDACKm: EXDMA transfer acknowledge ETENDm: EXDMA transfer end EDRAKm: EDREQ acceptance acknowledge (n: 0 to 3) (m:0 or 1)
Figure 11.1 Block Diagram of EXDMAC
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Section 11 EXDMA Controller (EXDMAC)
11.2
Input/Output Pins
Table 11.1 shows the EXDMAC pin configuration. Table 11.1 Pin Configuration
Channel 0 Name EXDMA transfer request 0 EXDMA transfer acknowledge 0 EXDMA transfer end 0 EDREQ0 acceptance acknowledge 1 EXDMA transfer request 1 EXDMA transfer acknowledge 1 EXDMA transfer end 1 EDREQ1 acceptance acknowledge Abbr. EDREQ0 EDACK0 ETEND0 EDRAK0 I/O Input Output Output Output Function Channel 0 external request Channel 0 single address transfer acknowledge Channel 0 transfer end Notification to external device of channel 0 external request acceptance and start of execution Channel 1 external request Channel 1 single address transfer acknowledge Channel 1 transfer end Notification to external device of channel 1 external request acceptance and start of execution
EDREQ1 EDACK1 ETEND1 EDRAK1
Input Output Output Output
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Section 11 EXDMA Controller (EXDMAC)
11.3
Registers Descriptions
The EXDMAC has the following registers. Channel 0 * * * * * * * EXDMA source address register_0 (EDSAR_0) EXDMA destination address register_0 (EDDAR_0) EXDMA offset register_0 (EDOFR_0) EXDMA transfer count register_0 (EDTCR_0) EXDMA block size register_0 (EDBSR_0) EXDMA mode control register_0 (EDMDR_0) EXDMA address control register_0 (EDACR_0)
Channel 1 * * * * * * * EXDMA source address register_1 (EDSAR_1) EXDMA destination address register_1 (EDDAR_1) EXDMA offset register_1 (EDOFR_1) EXDMA transfer count register_1 (EDTCR_1) EXDMA block size register_1 (EDBSR_1) EXDMA mode control register_1 (EDMDR_1) EXDMA address control register_1 (EDACR_1)
Channel 2 * * * * * * * EXDMA source address register_2 (EDSAR_2) EXDMA destination address register_2 (EDDAR_2) EXDMA offset register_2 (EDOFR_2) EXDMA transfer count register_2 (EDTCR_2) EXDMA block size register_2 (EDBSR_2) EXDMA mode control register_2 (EDMDR_2) EXDMA address control register_2 (EDACR_2)
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Section 11 EXDMA Controller (EXDMAC)
Channel 3 * * * * * * * EXDMA source address register_3 (EDSAR_3) EXDMA destination address register_3 (EDDAR_3) EXDMA offset register_3 (EDOFR_3) EXDMA transfer count register_3 (EDTCR_3) EXDMA block size register_3 (EDBSR_3) EXDMA mode control register_3 (EDMDR_3) EXDMA address control register_3 (EDACR_3)
Common register * Cluster buffer registers 0 to 7 (CLSBR0 to CLSBR7)
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Section 11 EXDMA Controller (EXDMAC)
11.3.1
EXDMA Source Address Register (EDSAR)
EDSAR is a 32-bit readable/writable register that specifies the transfer source address. An address update function is provided that updates the register contents to the next transfer source address each time transfer processing is performed. In single address mode, the EDSAR value is ignored when the address specified by EDDAR is transferred as a destination address (DIRS = 1 in EDACR). EDSAR can be read at all times by the CPU. When reading EDSAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDSAR for a channel on which EXDMA transfer is in progress.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24
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Section 11 EXDMA Controller (EXDMAC)
11.3.2
EXDMA Destination Address Register (EDDAR)
EDDAR is a 32-bit readable/writable register that specifies the transfer destination address. An address update function is provided that updates the register contents to the next transfer destination address each time transfer processing is performed. In single address mode, the EDDAR value is ignored when the address specified by EDSAR is transferred as a source address (DIRS = 0 in EDACR). EDDAR can be read at all times by the CPU. When reading EDDAR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDDAR for a channel on which EXDMA transfer is in progress.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24
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Section 11 EXDMA Controller (EXDMAC)
11.3.3
EXDMA Offset Register (EDOFR)
EDOFR is a 32-bit readable/writable register that sets the offset value when offset addition is selected for updating source or destination addresses. This register can be set independently for each channel, but the same offset value must be used for the source and destination addresses on the same channel.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24
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Section 11 EXDMA Controller (EXDMAC)
11.3.4
EXDMA Transfer Count Register (EDTCR)
EDTCR is a 32-bit readable/writable register that specifies the size of data to be transferred (total transfer size). When EDTCR is set to H'00000001, the total transfer size is 1 byte. When EDTCR is set to H'00000000, the total transfer size is not specified and the transfer counter is halted (free-running mode). In this case, no transfer end interrupt by the transfer counter is generated. When EDTCR is set to H'FFFFFFFF, up to 4 Gbytes (4,294,967,295 bytes) of the total transfer size is set. When the EXDMA is active, EDTCR indicates the remaining transfer size. The value according to the data access size (byte: -1, word: -2, longword: -4) is decremented each time of a data transfer. EDTCR can be read at all times by the CPU. When reading EDTCR for a channel on which EXDMA transfer processing is in progress, a longword-size read must be executed. Do not write to EDTCR for a channel on which EXDMA transfer is in progress.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 0 R/W 19 0 R/W 18 0 R/W 17 0 R/W 16 31 30 29 28 27 26 25 24
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Section 11 EXDMA Controller (EXDMAC)
11.3.5
EXDMA Block Size Register (EDBSR)
EDBSR sets the repeat size, block size, or cluster size. EDBSR is enabled in repeat transfer, block transfer, and cluster transfer modes. EDBSR is disabled in normal transfer mode. When BKSZH and BKSZ are set to H'0001 in cluster transfer mode (dual address mode), the EXDMAC operates in block transfer mode (dual address mode).
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 31 BKSZH31 0 R/W 23 BKSZH23 0 R/W 15 BKSZ15 0 R/W 7 BKSZ7 0 R/W 30 BKSZH30 0 R/W 22 BKSZH22 0 R/W 14 BKSZ14 0 R/W 6 BKSZ6 0 R/W 29 BKSZH29 0 R/W 21 BKSZH21 0 R/W 13 BKSZ13 0 R/W 5 BKSZ5 0 R/W 28 BKSZH28 0 R/W 20 BKSZH20 0 R/W 12 BKSZ12 0 R/W 4 BKSZ4 0 R/W 27 BKSZH27 0 R/W 19 BKSZH19 0 R/W 11 BKSZ11 0 R/W 3 BKSZ3 0 R/W 26 BKSZH26 0 R/W 18 BKSZH18 0 R/W 10 BKSZ10 0 R/W 2 BKSZ2 0 R/W 25 BKSZH25 0 R/W 17 BKSZH17 0 R/W 9 BKSZ9 0 R/W 1 BKSZ1 0 R/W 24 BKSZH24 0 R/W 16 BKSZH16 0 R/W 8 BKSZ8 0 R/W 0 BKSZ0 0 R/W
Bit 31 to 16
Bit Name BKSZH31 to BKSZH16
Initial value All 0
R/W R/W
Description Sets the repeat size, block size, or cluster size. When these bits are set to H'0001, one byte-, one word-, or one longword-size is set. When these bits are set to H'0000, the maximum values are set (see table 11.2). These bits are always fixed during an EXDMA operation.
15 to 0
BKSZ15 to BKSZ0
All 0
R/W
In an EXDMA operation, the remaining repeat size, block size, or cluster size is indicated. The value is decremented by one each time of a data transfer. When the remaining size becomes zero, the BKSZH value is loaded. Set the same initial value as for the BKSZH bit when writing.
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Section 11 EXDMA Controller (EXDMAC)
Table 11.2 Data Access Size, Enable Bit, and Allowable Size
Mode Repeat transfer mode Block transfer mode Data BKSZH Access Size enable bit Byte Word Longword Cluster transfer mode Byte Word Longword 20 to 16 19 to 16 18 to 16 4 to 0 3 to 0 2 to 0 31 to 16 BKSZ enable bit 15 to 0 Allowable size (in bytes) 1 to 65,536 2 to 131,072 4 to 262,144 1 to 32 2 to 32 4 to 32
11.3.6
EXDMA Mode Control Register (EDMDR)
EDMDR controls EXDMAC operations. * EDMDR_0
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 31 DTE 0 R/W 23 ACT 0 R 15 DTSZ1 0 R/W 7 DTF1 0 R/W 30 EDACKE 0 R/W 22 0 R 14 DTSZ0 0 R/W 6 DTF0 0 R/W 29 ETENDE 0 R/W 21 0 R 13 MDS1 0 R/W 5 0 R/W 28 EDRAKE 0 R/W 20 0 R 12 MDS0 0 R/W 4 0 R 27 EDREQS 0 R/W 19 ERRF 0 R/(W)* 11 TSEIE 0 R/W 3 0 R 26 NRD 0 R/W 18 0 R 10 0 R 2 EDMAP2 0 R/W 25 0 R 17 ESIF 0 R/(W)* 9 ESIE 0 R/W 1 EDMAP1 0 R/W 24 0 R 16 DTIF 0 R/(W)* 8 DTIE 0 R/W 0 EDMAP0 0 R/W
Only 0 can be written to this bit after having been read as 1, to clear the flag.
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Section 11 EXDMA Controller (EXDMAC)
* EDMDR_1 to EDMDR_3
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Note: * 31 DTE 0 R/W 23 ACT 0 R 15 DTSZ1 0 R/W 7 DTF1 0 R/W 30 EDACKE 0 R/W 22 0 R 14 DTSZ0 0 R/W 6 DTF0 0 R/W 29 ETENDE 0 R/W 21 0 R 13 MDS1 0 R/W 5 0 R/W 28 EDRAKE 0 R/W 20 0 R 12 MDS0 0 R/W 4 0 R 27 DREQS 0 R/W 19 0 R 11 TSEIE 0 R/W 3 0 R 26 NRD 0 R/W 18 0 R 10 0 R 2 EDMAP2 0 R/W 25 0 R 17 ESIF 0 R/(W)* 9 ESIE 0 R/W 1 EDMAP1 0 R/W 24 0 R 16 DTIF 0 R/(W)* 8 DTIE 0 R/W 0 EDMAP0 0 R/W
Only 0 can be written to this bit after having been read as 1, to clear the flag.
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Section 11 EXDMA Controller (EXDMAC)
Bit 31
Bit Name DTE
Initial value 0
R/W R/W
Description Data Transfer Enable Enables or disables data transfer on the corresponding channel. When this bit is set to 1, this indicates that an EXDMA operation is in progress. When auto-request mode is specified, transfer processing begins when this bit is set to 1. With external requests, transfer processing begins when a transfer request is issued after this bit has been set to 1. When this bit is cleared to 0 during an EXDMA operation, transfer is halted. If this bit is cleared to 0 during an EXDMA operation in block transfer mode, this bit is cleared to 0 on completion of the currently executing one-block transfer. When this bit is cleared to 0 during an EXDMA operation in cluster transfer mode, this bit is cleared to 0 on completion of the currently executing one-cluster transfer. If an external source that ends (aborts) transfer occurs, this bit is automatically cleared to 0 and transfer is terminated. Do not change the operating mode, transfer method, or other parameters while this bit is set to 1. 0: Data transfer disabled 1: Data transfer enabled (during an EXDMA operation) [Clearing conditions] * * * * * When transfer of the total transfer size specified ends When operation is halted by a repeat size end interrupt When operation is halted by an extended repeat area overflow interrupt When operation is halted by a transfer size error interrupt When 0 is written to terminate transfer In block transfer mode, the value written is effective after one-block transfer ends. In cluster transfer mode, the value written is effective after one-cluster transfer ends. When an address error or NMI interrupt occurs Reset, hardware standby mode
* *
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Section 11 EXDMA Controller (EXDMAC)
Bit 30
Bit Name EDACKE
Initial value 0
R/W R/W
Description EDACK Pin Output Enable In single address mode, enables or disables output from the EDACK pin. In dual address mode, the specification by this bit is ignored. This bit should be set to 0 for EDMDR_2 or EDMDR_3. 0: EDACK pin output disabled 1: EDACK pin output enabled
29
ETENDE
0
R/W
ETEND Pin Output Enable Enables or disables output from the ETEND pin. This bit should be set to 0 for EDMDR_2 or EDMDR_3. 0: ETEND pin output disabled 1: ETEND pin output enabled
28
EDRAKE
0
R/W
EDRAK Pin Output Enable Enables or disables output from the EDRAK pin. This bit should be set to 0 for EDMDR_2 or EDMDR_3. 0: EDRAK pin output disabled 1: EDRAK pin output enabled
27
EDREQS
0
R/W
EDREQ Select Selects whether a low level or the falling edge of the EDREQ signal used in external request mode is detected. This bit should be set to 0 for EDMDR_2 or EDMDR_3. 0: Low-level detection 1: Falling edge detection (the first transfer is detected on a low level after a transfer is enabled.)
26
NRD
0
R/W
Next Request Delay Selects the timing of the next transfer request to be accepted. 0: Next transfer request starts to be accepted after transfer of the bus cycle in progress ends. 1: Next transfer request starts to be accepted after one cycle of B from the completion of the bus cycle in progress.
25, 24
All 0
R
Reserved They are always read as 0 and cannot be modified.
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Section 11 EXDMA Controller (EXDMAC)
Bit 23
Bit Name ACT
Initial value 0
R/W R
Description Active State Indicates the operation state of the corresponding channel. 0: Transfer request wait state or transfer disabled state (DTE = 0) 1: Active state
22 to 20 19
ERRF
All 0 0
R R/(W)*
Reserved They are always read as 0 and cannot be modified. System Error Flag Flag that indicates the occurrence of an address error or NMI interrupt. This bit is only enabled in EDMDR_0. When this bit is set to 1, write to the DTE bit for all channels is disabled. This bit is reserved in EDMDR_1 to EDMDR_3. They are always read as 0 and cannot be modified. 0: Address error or NMI interrupt is not generated 1: Address error or NMI interrupt is generated [Clearing condition] * * Writing 0 to ERRF after reading ERRF = 1 When an address error or NMI interrupt occurred [Setting condition] However, when an address error or an NMI interrupt has been generated in EXDMAC module stop mode, this bit is not set to 1.
18
0
R
Reserved They are always read as 0 and cannot be modified.
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Section 11 EXDMA Controller (EXDMAC)
Bit 17
Bit Name ESIF
Initial value 0
R/W R/(W)*
Description Transfer Escape Interrupt Flag Flag indicating that a transfer escape end interrupt request has occurred before the transfer counter becomes 0 and transfer escape has ended. 0: Transfer escape end interrupt request is not generated 1: Transfer escape end interrupt request is generated [Clearing conditions] * * * * * Writing 1 to the DTE bit Writing 0 to ESIF while reading ESIF = 1 Transfer size error interrupt request is generated Repeat size end interrupt request is generated Extended repeat area overflow end interrupt request is generated
[Setting conditions]
16
DTIF
0
R/(W)*
Data Transfer Interrupt Flag Flag indicating that a transfer end interrupt request has occurred by the transfer counter. 0: Transfer end interrupt request is not generated by the transfer counter 1: Transfer end interrupt request is generated by the transfer counter [Clearing conditions] * * * Writing 1 to the DTE bit Writing 0 to DTIF while reading DTIF = 1 When EDTCR becomes 0 and transfer has ended
[Setting condition] 15 14 DTSZ1 DTSZ0 0 0 R/W R/W Data Access Size 1 and 0 Selects the data access size. 00: Byte-size (8 bits) 01: Word-size (16 bits) 10: Longword-size (32 bits) 11: Setting prohibited
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Section 11 EXDMA Controller (EXDMAC)
Bit 13 12
Bit Name MDS1 MDS0
Initial value 0 0
R/W R/W R/W
Description Transfer Mode Select 1 and 0 Selects the transfer mode. 00: Normal transfer mode 01: Block transfer mode 10: Repeat transfer mode 11: Cluster transfer mode
11
TSEIE
0
R/W
Transfer Size Error Interrupt Enable Enables or disables a transfer size error interrupt request. When this bit is set to 1 and the transfer counter value becomes smaller than the data access size for one transfer request by EXDMAC transfer, the DTE bit is cleared to 0 by the next transfer request. At the same time, the ESIF bit is set to 1 to indicate that a transfer size error interrupt request is generated. When cluster transfer read/write address mode is specified, this bit should be set to 1. Transfer size error interrupt request occurs in the following conditions: * In normal transfer and repeat transfer modes, the total transfer size set in EDTCR is smaller than the data access size In block transfer mode, the total transfer size set in EDTCR is smaller than the block size In cluster transfer mode, the total transfer size set in EDTCR is smaller than the cluster size
* *
0: Transfer size error interrupt request disabled 1: Transfer size error interrupt request enabled 10 0 R Reserved They are always read as 0 and cannot be modified.
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Section 11 EXDMA Controller (EXDMAC)
Bit 9
Bit Name ESIE
Initial value 0
R/W R/W
Description Transfer Escape Interrupt Enable Enables or disables a transfer escape end interrupt request occurred during EXDMA transfer. When this bit is set to 1, and the ESIF bit is set to 1, a transfer escape end interrupt is requested to the CPU or DTC. The transfer escape end interrupt request is canceled by clearing this bit or the ESIF bit to 0. 0: Transfer escape interrupt request disabled 1: Transfer escape interrupt request enabled
8
DTIE
0
R/W
Data Transfer Interrupt Enable Enables or disables a transfer end interrupt request by the transfer counter. When this bit is set to 1 and the DTIF bit is set to 1, a transfer end interrupt is requested to the CPU or DTC. The transfer end interrupt request is canceled by clearing this bit or the DTIF bit to 0. 0: Transfer end interrupt request disabled 1: Transfer end interrupt request enabled
7 6
DTF1 DTF0
0 0
R/W R/W
Data Transfer Factor 1 and 0 Selects a source to activate EXDMAC. For external requests, a sampling method is selected by the EDREQS bit. External requests should not be selected for EDMDR_2 or EDMDR_3. 00: Auto-request (cycle steal mode) 01: Auto-request (burst mode) 10: Setting prohibited 11: External request
5
0
R/W
Reserved The initial value should not be changed.
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Section 11 EXDMA Controller (EXDMAC)
Bit 4, 3 2 1 0
Bit Name EDMAP2 EDMAP1 EDMAP0
Initial value All 0 0 0 0
R/W R R/W R/W R/W
Description Reserved They are always read as 0 and cannot be modified. EXDMA Priority Levels 2 to 0 Selects the EXDMAC priority level when using the CPU priority control function over DTC and EXDMAC. When the EXDMAC priority level is lower than the CPU priority level, EXDMAC masks the acceptance of transfer source and waits until the CPU priority level becomes low. The priority level can be set independently for each channel. This bit is enabled when the CPUPCE bit in CPUPCR is 1. 000: Priority level 0 (lowest) 001: Priority level 1 010: Priority level 2 011: Priority level 3 100: Priority level 4 101: Priority level 5 110: Priority level 6 111: Priority level 7 (highest)
Note:
*
Only 0 can be written to these bits after 1 is read to clear the flag.
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Section 11 EXDMA Controller (EXDMAC)
11.3.7
EXDMA Address Control Register (EDACR)
EDACR sets the operating modes and transfer methods.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 31 AMS 0 R/W 23 0 R 15 SARIE 0 R/W 7 DARIE 0 R/W 30 DIRS 0 R/W 22 0 R 14 0 R 6 0 R 29 0 R 21 SAT1 0 R/W 13 0 R 5 0 R 28 0 R 20 SAT0 0 R/W 12 SARA4 0 R/W 4 DARA4 0 R/W 27 0 R 19 0 R 11 SARA3 0 R/W 3 DARA3 0 R/W 26 RPTIE 0 R/W 18 0 R 10 SARA2 0 R/W 2 DARA2 0 R/W 25 ARS1 0 R/W 17 DAT1 0 R/W 9 SARA1 0 R/W 1 DARA1 0 R/W 24 ARS0 0 R/W 16 DAT0 0 R/W 8 SARA0 0 R/W 0 DARA0 0 R/W
Bit 31
Bit Name AMS
Initial value 0
R/W R/W
Description Address Mode Select Selects single address mode or dual address mode. When single address mode is selected, EDACK pin is valid due to the EDACKE bit setting in EDMDR. 0: Dual address mode 1: Single address mode
30
DIRS
0
R/W
Single Address Direction Select Specifies the data transfer direction in single address mode. In dual address mode, the specification by this bit is ignored. In cluster transfer mode, the internal cluster buffer will be the source or destination in place of the external device with DACK. 0: EDSAR transferred as a source address 1: EDDAR transferred as a destination address
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Section 11 EXDMA Controller (EXDMAC)
Bit 29 to 27 26
Bit Name RPTIE
Initial value All 0 0
R/W R R/W
Description Reserved They are always read as 0 and cannot be modified. Repeat Size End Interrupt Enable Enables or disables a repeat size end interrupt request. When this bit is set to 1 and the next transfer source is generated at the end of a repeat-size transfer in repeat transfer mode, the DTE bit in EDMDR is cleared to 0. At the same time, the ESIF bit in EDMDR is set to 1 to indicate that a repeat size end interrupt is requested. Even if the repeat area is not specified (ARS1, ARS0 = B'10), the repeat size end interrupt can be requested at the end of a repeat-size transfer. When this bit is set to 1 and the next transfer source is generated at the end of a block- or cluster-size transfer in block transfer or cluster transfer mode, the DTE bit in EDMDR is cleared to 0. At the same time, the ESIF bit in EDMDR is set to 1 to indicate that the repeat size end interrupt is requested. 0: Repeat size end interrupt request disabled 1: Repeat size end interrupt request enabled
25 24
ARS1 ARS0
0 0
R/W R/W
Area Select 1 and 0 Select the block area or repeat area in block transfer, repeat transfer or cluster transfer mode. 00: Block area/repeat area on the source address side 01: Block area/repeat area on the destination address side 10: Block area/repeat area not specified 11: Setting prohibited
23, 22
All 0
R
Reserved They are always read as 0 and cannot be modified.
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Section 11 EXDMA Controller (EXDMAC)
Bit 21 20
Bit Name SAT1 SAT0
Initial value 0 0
R/W R/W R/W
Description Source Address Update Mode 1 and 0 These bits specify incrementing/decrementing of the transfer source address (EDSAR). When the transfer source is not specified in EDSAR in single address mode, the specification by these bits is ignored. 00: Fixed 01: Offset added 10: Incremented (+1, +2, or +4 according to the data access size) 11: Decremented (-1, -2, or -4 according to the data access size)
19, 18 17 16
DAT1 DAT0
All 0 0 0
R R/W R/W
Reserved They are always read as 0 and cannot be modified. Destination Address Update Mode 1 and 0 These bits specify incrementing/decrementing of the transfer destination address (EDDAR). When the transfer source is not specified in EDDAR in single address mode, the specification by these bits is ignored. 00: Fixed 01: Offset added 10: Incremented (+1, +2, or +4 according to the data access size) 11: Decremented (-1, -2, or -4 according to the data access size)
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Section 11 EXDMA Controller (EXDMAC)
Bit 15
Bit Name SARIE
Initial value 0
R/W R/W
Description Source Address Extended Repeat Area Overflow Interrupt Enable Enables or disables the source address extended repeat area overflow interrupt request. When this bit is set to 1, in the event of source address extended repeat area overflow, the DTE bit is cleared to 0 in EDMDR. At the same time, the ESIF bit is set to 1 in EDMDR to indicate that the source address extended repeat area overflow interrupt is requested. When used together with block transfer mode, an interrupt is requested at the end of a block-size transfer. If the DTE bit is set to 1 in EDMDR for the channel on which transfer is terminated by an interrupt, transfer can be resumed from the state in which it ended. If a source address extended repeat area is not designated, the specification by this bit is ignored. 0: Source address extended repeat area overflow interrupt request disabled 1: Source address extended repeat area overflow interrupt request enabled
14, 13 12 11 10 9 8
SARA4 SARA3 SARA2 SARA1 SARA0
All 0 0 0 0 0 0
R R/W R/W R/W R/W R/W
Reserved They are always read as 0 and cannot be modified. Source Address Extended Repeat Area These bits specify the source address (EDSAR) extended repeat area. The extended repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. An extended repeat area size of 4 bytes to 128 Mbytes can be specified. The setting interval is a power-of-two number of bytes. When extended repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the extended repeat area in the case of address incrementing, or the last address of the extended repeat area in the case of address decrementing. If SARIE bit is set to 1, an interrupt can be requested when an extended repeat area overflow occurs. Table 11.3 shows the settings and ranges of the extended repeat area.
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Section 11 EXDMA Controller (EXDMAC)
Bit 7
Bit Name DARIE
Initial value 0
R/W R/W
Description Destination Address Extended Repeat Area Overflow Interrupt Enable Enables or disables a destination address extended repeat area overflow interrupt request. When this bit is set to 1, in the event of destination address extended repeat area overflow, the DTE bit in EDMDR is cleared to 0. At the same time, the ESIF bit in EDMDR is set to 1 to indicate that a destination address extended repeat area overflow interrupt is requested. When used together with block transfer mode, an interrupt is requested at the end of a block-size transfer. If DTE bit is set to 1 in EDMDR for the channel on which transfer is terminated by an interrupt, transfer can be resumed from the state in which it ended. If a destination address extended repeat area is not designated, the specification by this bit is ignored. 0: Destination address extended repeat area overflow interrupt request disabled 1: Destination address extended repeat area overflow interrupt request enabled
6, 5 4 3 2 1 0
DARA4 DARA3 DARA2 DARA1 DARA0
All 0 0 0 0 0 0
R R/W R/W R/W R/W R/W
Reserved They are always read as 0 and cannot be modified. Destination Address Extended Repeat Area These bits specify the destination address (EDDAR) extended repeat area. The extended repeat area function updates the specified lower address bits, leaving the remaining upper address bits always the same. An extended repeat area size of 4 bytes to 128 Mbytes can be specified. The setting interval is a power-of-two number of bytes. When extended repeat area overflow results from incrementing or decrementing an address, the lower address is the start address of the extended repeat area in the case of address incrementing, or the last address of the extended repeat area in the case of address decrementing. If the DARIE bit is set to 1, an interrupt can be requested when an extended repeat area overflow occurs. Table 11.3 shows the settings and ranges of the extended repeat area.
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Section 11 EXDMA Controller (EXDMAC)
Table 11.3 Settings and Ranges of Extended Repeat Area
Value of SARA4 to SARA0/ DARA4 to DARA0 Range of Extended Repeat Area 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 111XX [Legend] X: Don't care Not designated as extended repeat area Lower 1 bit (2-byte area) designated as extended repeat area Lower 2 bit (4-byte area) designated as extended repeat area Lower 3 bit (8-byte area) designated as extended repeat area Lower 4 bit (16-byte area) designated as extended repeat area Lower 5 bit (32-byte area) designated as extended repeat area Lower 6 bit (64-byte area) designated as extended repeat area Lower 7 bit (128-byte area) designated as extended repeat area Lower 8 bit (256-byte area) designated as extended repeat area Lower 9 bit (512-byte area) designated as extended repeat area Lower 10 bit (1-kbyte area) designated as extended repeat area Lower 11 bit (2-kbyte area) designated as extended repeat area Lower 12 bit (4-kbyte area) designated as extended repeat area Lower 13 bit (8-kbyte area) designated as extended repeat area Lower 14 bit (16-kbyte area) designated as extended repeat area Lower 15 bit (32-kbyte area) designated as extended repeat area Lower 16 bit (64-kbyte area) designated as extended repeat area Lower 17 bit (128-kbyte area) designated as extended repeat area Lower 18 bit (256-kbyte area) designated as extended repeat area Lower 19 bit (512-kbyte area) designated as extended repeat area Lower 20 bit (1-Mbyte area) designated as extended repeat area Lower 21 bit (2-Mbyte area) designated as extended repeat area Lower 22 bit (4-Mbyte area) designated as extended repeat area Lower 23 bit (8-Mbyte area) designated as extended repeat area Lower 24 bit (16-Mbyte area) designated as extended repeat area Lower 25 bit (32-Mbyte area) designated as extended repeat area Lower 26 bit (64-Mbyte area) designated as extended repeat area Lower 27 bit (128-Mbyte area) designated as extended repeat area Setting prohibited
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Section 11 EXDMA Controller (EXDMAC)
11.3.8
Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7)
CLSBR0 to CLSBR7 are 32-bit readable/writable registers that store the transfer data. The transfer data is stored in order from CLSBR0 to CLSBR7 in cluster transfer mode. The data stored in cluster transfer mode or by the CPU write operation is held until the next cluster transfer or CPU write operation is performed. When reading the data stored in cluster transfer mode by the CPU, check the completion of cluster transfer and then perform only a cluster-size read specified for the cluster transfer. Data with another size is undefined. In cluster transfer mode, the same CLSBR is used for all channels. When the CPU write operation to CLSBR conflicts with cluster transfer, the contents of transferred data are not guaranteed. When cluster transfer read/write address mode is specified and if another channel is set for cluster transfer, the transferred data may be overwritten.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W Undefined R/W 7 Undefined R/W 6 Undefined R/W 5 Undefined R/W 4 Undefined R/W 3 Undefined R/W 2 Undefined R/W 1 Undefined R/W 0 Undefined R/W 15 Undefined R/W 14 Undefined R/W 13 Undefined R/W 12 Undefined R/W 11 Undefined R/W 10 Undefined R/W 9 Undefined R/W 8 Undefined R/W 23 Undefined R/W 22 Undefined R/W 21 Undefined R/W 20 Undefined R/W 19 Undefined R/W 18 Undefined R/W 17 Undefined R/W 16 31 30 29 28 27 26 25 24
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Section 11 EXDMA Controller (EXDMAC)
11.4
11.4.1
Transfer Modes
Ordinary Modes
The ordinary modes of EXDMAC are summarized in table 11.4. The transfer mode can be set independently for each channel. Table 11.4 Ordinary Modes
Address Mode Dual address mode Address Register Transfer Mode * * * Normal transfer mode Repeat transfer mode Block transfer mode (Repeat size/ block size = 1 to 65,536 bytes/ word/longword) Single address mode* * * * Direct data transfer to/from external devices using EDACK pin instead of source or destination address register Above transfer mode can be specified in addition to address register setting One transfer possible in one bus cycle EDSAR/ EDACK EDACK/ EDDAR * Activation Source * Auto-request (activated by the CPU) External request* * * Common Function * Total transfer size: 1 to 4 Gbytes, or no specification Offset addition Extended repeat area function Source EDSAR Destination EDDAR
(Transfer mode variations are the same as in dual address mode.)
Note
Only channel 0 or 1 can be selected.
When the activation source is an auto-request, cycle steal mode or burst mode can be selected. When the total transfer size is not specified (EDTCR = H'00000000), the transfer counter is halted and the transfer count is not restricted, allowing continuous transfer.
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Section 11 EXDMA Controller (EXDMAC)
11.4.2
Cluster Transfer Modes
Table 11.5 shows cluster transfer modes. Cluster transfer mode can be set independently for each channel. The cluster buffer is common to all channels. Table 11.5 Cluster Transfer Mode
Transfer Source EDSAR Cluster Buffer Function Read from the transfer source and written to the transfer destination Read from the transfer source Written to the transfer destination Transfer Destination EDDAR
Address Mode Cluster transfer Dual address mode
Activation Source * Auto-request (activated by the CPU) * External request*
Common Function * Cluster size One access size (byte/word/longword) to 32 bytes * Total transfer size 1 to 4 Gbytes, or no specification * * Offset addition Extended repeat area function
Cluster transfer Read address mode (DIRS = 0) Cluster transfer Write address mode (DIRS = 1)
EDSAR
EDDAR
Note
*
Only channel 0 or 1 can be selected.
In cluster transfer mode, the specified cluster size is transferred in response to a single transfer request. The cluster size can be from one access size (byte, word, or longword) to 32 bytes. Within a cluster, a cluster-size transfer is performed in burst transfer mode. With a cluster-size access in cluster transfer mode (dual address mode), block transfer mode (dual address mode) is used. With auto-requests, cycle steal mode is set.
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Section 11 EXDMA Controller (EXDMAC)
11.5
11.5.1 (1)
Mode Operation
Address Modes
Dual Address Mode
In dual address mode, the transfer source address is set in EDSAR, and the transfer destination address is set in EDDAR. One transfer operation is executed in two bus cycles. (When the data bus width is smaller than the data access size or when the address to be accessed is not at the data boundary of the data access size, the bus cycle is divided, resulting more than two bus cycles.) In a transfer operation, the data on the transfer source address is read in the first bus cycle, and is written to the transfer destination address in the next bus cycle. These consecutive read and write cycles are indivisible: another bus cycle (external access by another bus master, refresh cycle, or external bus release cycle) does not occur between these two cycles. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for two consecutive bus cycles. When an idle cycle is inserted before the bus cycle, the ETEND signal is also output in the idle cycle. The EDACK signal is not output. Figure 11.2 shows an example of the timing in dual address mode and figure 11.3 shows the dual address mode operation.
EXDMA read cycle B Address bus RD WR ETEND EDSAR EDDAR EXDMA write cycle
Figure 11.2 Example of Timing in Dual Address Mode
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Section 11 EXDMA Controller (EXDMAC)
Address TA
Transfer
Address TB
Address BA
Address update setting The source address incremented The destination adderss is fixed
Figure 11.3 Dual Address Mode Operation (2) Single Address Mode
In single address mode, the EDACK pin is used instead of EDSAR or EDDAR to transfer data directly between an external device and external memory. One transfer operation is executed in one bus cycle. Only channel 0 or 1 can be selected for single address mode. In this mode, the data bus width must be the same as the data access size. For details on the data bus width, see section 9, Bus Controller (BSC). In this mode, the EXDMAC accesses the transfer source or transfer destination external device by outputting the strobe signal (EDACK) for the external device with DACK, and at the same time accesses the other external device in the transfer by outputting an address. In this way, EXDMA transfer can be executed in one bus cycle. In the example of transfer between external memory and an external device with DACK shown in figure 11.4, data is output to the data bus by the external device and written to external memory in the same bus cycle. The transfer direction, that is whether the external device with DACK is the transfer source or transfer destination, can be specified with the DIRS bit in EDACR. Transfer is performed from the external memory (EDSAR) to the external device with DACK when DIRS = 0, and from the external device with DACK to the external memory (EDDAR) when DIRS = 1. The setting in the source or destination address register not used in the transfer is ignored. The EDACK pin output is valid by the setting of EDACKE bit in EDMDR when single address mode is selected. The EDACK pin output is active-low. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for one bus cycle. When an idle cycle is inserted before the bus cycle, the ETEND signal is also output in the idle cycle.
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Section 11 EXDMA Controller (EXDMAC)
Figure 11.5 shows an example of the timing in single address mode and figure 11.6 shows the single address mode operation.
External address bus LSI External memory External data bus
EXDMAC
External device with DACK EDACK EDREQ
Data flow
Figure 11.4 Data Flow in Single Address Mode
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Section 11 EXDMA Controller (EXDMAC)
Transfer from external memory to external device with DACK EXDMA cycle B Address bus RD WR EDACK Data bus ETEND Data output by external memory High EDSAR Address for external memory space RD signal to external memory space
Transfer from external device with DACK to external memory EXDMA cycle B Address bus RD WR EDACK Data bus ETEND Data output from external device with DACK High WR signal to external memory space EDDAR Address for external memory space
Figure 11.5 Example of Timing in Single Address Mode
Address T
Transfer
EDACK
Address B
Figure 11.6 Single Address Mode Operation
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Section 11 EXDMA Controller (EXDMAC)
11.5.2 (1)
Transfer Modes
Normal Transfer Mode
In normal transfer mode, transfer of one data access size unit is processed in response to one transfer request. The total transfer size of up to 4 Gbytes can be set by EDTCR. EDBSR is invalid in normal transfer mode. The ETEND signal is output only for the last EXDMA transfer. The EDRAK signal is output each time a transfer request is accepted and transfer processing is started. Figure 11.7 shows examples of transfer timing in normal transfer mode and figure 11.8 shows the normal transfer mode operation in dual address mode.
Transfer conditions: Dual address mode, auto-request mode EXDMA transfer cycle Bus cycle ETEND Transfer conditions: Single address mode, external request mode EDREQ
EDRAK Bus cycle
Last EXDMA transfer cycle
Read
Write
Read
Write
EXDMA
EXDMA
EDACK
Figure 11.7 Examples of Timing in Normal Transfer Mode
Address TA
Transfer Total transfer size (EDTCR)
Address TB
Address BA
Address BB
Figure 11.8 Normal Transfer Mode Operation
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Section 11 EXDMA Controller (EXDMAC)
(2)
Repeat Transfer Mode
In repeat transfer mode, transfer of one data access size unit is processed in response to one transfer request. The total transfer size of up to 4 Gbytes can be set by EDTCR. The repeat size of up to 64 kbytes x data access size can be set by EDBSR. The ARS1 and ARS0 bits in EDACR specify the repeat area on the source address or destination address side. The address specified for the repeat area is restored to the transfer start address at the end of a repeat-size transfer. This operation continues until transfer of total transfer size set in EDTCR ends. EDTCR specified with H'00000000 is assumed as free-running mode and the repeat transfer continues until the DTE bit in EDMDR is cleared to 0. At the end of a repeat-size transfer, the EXDMA transfer is halted temporarily and a repeat size end interrupt is requested to the CPU or DTC. When the RPTIE bit in EDACR is set to 1 and the next transfer request is generated at the end of a repeat-size transfer, the ESIF bit in EDMDR is set to 1 and the DTE bit in EDMDR is cleared to 0 to terminate the transfer. At this time, an interrupt is requested to the CPU or DTC when the ESIE bit in EDMDR is set to 1. The timing of EXDMA transfer including the ETEND or EDRAK output is the same as for normal transfer mode. Figure 11.9 shows the repeat transfer mode operation in dual address mode. The operation without specifying a repeat area on the source or destination address side is the same as for the normal transfer mode operation shown in figure 11.8. In this case, a repeat size end interrupt can also be generated at the end of a repeat-size transfer.
Address TA
Transfer
Repeat size (BKSZH x data access size)
Address TB
Address BA
Total transfer size (EDTCR)
Operation with the repeat area specified on the source address side
Address BB
Figure 11.9 Repeat Transfer Mode Operation
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Section 11 EXDMA Controller (EXDMAC)
(3)
Block Transfer Mode
In block transfer mode, transfer of one block size unit is processed in response to one transfer request. The total transfer size of up to 4 Gbytes can be set by EDTCR. The block size of up to 64 kbytes x data access size can be set by EDBSR. A transfer request from another channel is held pending during one block transfer. When oneblock transfer is completed, the bus mastership is released for another bus master. A block area can be specified by the ARS1 or ARS0 bit in EDACR on the source or destination address side. The address specified for the block area is restored to the transfer start address each time one-block transfer completes. When no repeat area is specified on the source and destination address sides, the address is not restored to the transfer start address and the operation proceeds to the next sequence. A repeat size end interrupt can be generated. The ETEND signal is output for each block transfer in the EXDMA transfer cycle in which the block ends. The EDRAK signal is output once for one transfer request (for transfer of one block). Caution is required when setting the extended repeat area overflow interrupt in block transfer mode. For details, see section 11.5.5, Extended Repeat Area Function. Figure 11.10 shows an example of EXDMA transfer timing in block transfer mode. The transfer conditions are as follows: Address mode: Single address mode Data access size: In bytes One block size: 3 bytes
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Section 11 EXDMA Controller (EXDMAC)
Figure 11.11 shows the block transfer mode operation in single address mode and figure 11.12 shows the block transfer mode operation in dual address mode.
EDREQ
EDRAK
One-block transfer cycle
Bus cycle
CPU
CPU
EXDMAC
EXDMAC
EXDMAC
CPU
CPU cycle not generated
ETEND
Figure 11.10 Example of Block Transfer Mode
Address T
Block
BKSZH x data access size
Transfer
EDACK
Address B
Figure 11.11 Block Transfer Mode Operation in Single Address Mode (with Block Area Specified)
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Section 11 EXDMA Controller (EXDMAC)
Address TA First block BKSZH x data access size
Transfer First block
Address TB
Second block
Second block
Total transfer size (EDTCR)
Nth block
Nth block Address BB
Address BA
Figure 11.12 Block Transfer Mode Operation in Dual Address Mode (without Block Area Specified)
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Section 11 EXDMA Controller (EXDMAC)
11.5.3
Activation Sources
The EXDMAC is activated by an auto request or an external request. This activation source is selected by the DTF1 or DTF0 bit in EDMDR. (1) Activation by Auto-Request
The transfer request signal is automatically generated in EXDMAC with auto-request activation when no transfer request signal is generated from external or peripheral modules, incase of transfer among memory or between memory and peripheral modules that cannot generate the transfer request signal. The transfer starts when the DTE bit in EDMDR is set to 1 with autorequest activation. The bus mode can be selected from cycle steal mode and burst mode with autorequest activation. (2) Activation by External Request
Transfer is started by the transfer request signal (EDREQ) from the external device for activation by an external request. When the EXDMA transfer is enabled (DTE = 1), the EXDMA transfer starts by EDREQ input. Only channel 0 or 1 can be selected for activation by an external request. The transfer request signal is accepted by the EDREQ pin. The EDREQS bit in EDMDR selects whether the EDREQ is detected by falling edge sensing or low level sensing. When the EDRAKE bit in EDMDR is set to 1, the signal notifying transfer request acceptance is output from the EDRAK pin. The EDRAK signal is accepted for one external request and is output when transfer processing starts. When specifying an external request as an activation source, set the DDR bit to 0 and the ICR bit to 1 on the corresponding pin in advance. For details, see section 13, I/O Ports.
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Section 11 EXDMA Controller (EXDMAC)
11.5.4
Bus Mode
There are two bus modes: cycle steal mode and burst mode. For auto-request activation, either cycle steal mode or burst mode can be selected by the DTF0 bit in EDMDR. When the activation source is an external request, cycle steal mode is used. (1) Cycle Steal Mode
In cycle steal mode, the EXDMAC releases the bus mastership at the end of each transfer of a transfer unit (byte, word, longword, one block size, or one cluster size). If there is a subsequent transfer request, the EXDMAC takes back the bus mastership, performs another transfer-unit transfer, and then releases the bus mastership again at the end of the transfer. This procedure is repeated until the transfer end condition is satisfied. If a transfer request occurs in another channel during EXDMA transfer, the bus mastership is temporarily released for another bus master, then transfer is performed on the channel for which the transfer request was issued. For details on the operation when there are transfer requests for a number of channels, see section 11.5.8, Channel Priority Order. Figure 11.13 shows an example of the timing in cycle steal mode. The transfer conditions are as follows: * Address mode: Single address mode * Sampling method on the EDREQ pin: Low level sensing * CPU internal bus master is operating in external space
EDREQ EDRAK Bus cycle
CPU
CPU
EXDMAC
CPU
EXDMAC
CPU
Bus mastership returned temporarily to CPU
Figure 11.13 Example of Timing in Cycle Steal Mode
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Section 11 EXDMA Controller (EXDMAC)
(2)
Burst Mode
In burst mode, once the EXDMAC acquires the bus mastership, it continues transferring data, without releasing the bus mastership, until the transfer end condition is satisfied. In burst mode, once transfer is started it is not interrupted even if there is a transfer request for another channel with higher priority. When the burst mode channel finishes its transfer, it releases the bus mastership in the next cycle in the same way as in cycle steal mode. However, when the EBCCS bit in BCR2 of the bus controller is set to 1, the EXDMAC can temporarily release the bus mastership for another bus master when an external access request is generated from another bus master. In block transfer mode and cluster transfer mode, the setting of burst mode is invalid (one-block or one-cluster transfer is processed in the same way as in burst mode). The EXDMAC always operates in cycle steal mode. When the DTE bit is cleared to 0 in EDMDR, EXDMA transfer is halted. However, EXDMA transfer is executed for all transfer requests generated within the EXDMAC until the DTE bit is cleared to 0. If a transfer size error interrupt, a repeat size end interrupt, or extended repeat area overflow interrupt is generated, the DTE bit is cleared to 0 and transfer is terminated. Figure 11.14 shows an example of the timing in burst mode.
Bus cycle
CPU
CPU
EXDMAC
EXDMAC
EXDMAC
CPU
CPU
CPU cycle not generated
Figure 11.14 Example of Timing in Burst Mode 11.5.5 Extended Repeat Area Function
The EXDMAC has a function for designating an extended repeat area for source addresses and/or destination addresses. When an extended repeat area is designated, the address register values repeat within the range specified as the extended repeat area. Normally, when a ring buffer is involved in a transfer, an operation is required to restore the address register value to the buffer start address each time the address register value becomes the last address in the buffer (i.e. when ring buffer address overflow occurs). However, if the extended repeat area function is used, the operation that restores the address register value to the buffer start address is processed automatically within the EXDMAC. The extended repeat area function can be set independently for the source address register (EDSAR) and the destination address register (EDDAR).
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Section 11 EXDMA Controller (EXDMAC)
The source address extended repeat area is specified by bits SARA4 to SARA0 in EDACR, and the destination address extended repeat area by bits DARA4 to DARA0 in EDACR. The size of each extended repeat area can be specified independently. When the address register value is the last address in the extended repeat area and extended repeat area overflow occurs, EXDMA transfer can be temporarily halted and an extended repeat area overflow interrupt request can be generated for the CPU. If the SARIE bit in EDACR is set to 1, and the EDSAR extended repeat area overflows, the ESIF bit is set to 1 and the DTE bit cleared to 0 in EDMDR, and transfer is terminated. If the ESIE bit is set to 1 in EDMDR, an extended repeat area overflow interrupt is requested to the CPU. If the DARIE bit in EDACR is set to 1, the above applies to the destination address register. If the DTE bit in EDMDR is set to 1 during interrupt generation, transfer is resumed. Figure 11.15 illustrates the operation of the extended repeat area function.
When lower 3 bits (8-byte area) of EDSAR are designated as extended repeat area (SARA4 to SARA0 = B'00011) External memory H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 Range of EDSAR values
H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007
...
Repeat
Extended repeat area overflow interrupt can be requested
Figure 11.15 Example of Extended Repeat Area Function Operation
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...
Section 11 EXDMA Controller (EXDMAC)
Caution is required when the extended repeat area overflow interrupt is used together with block transfer mode. If transfer is always terminated when extended repeat area overflow occurs in block transfer mode, the block size must be a power of two, or alternatively, the address register value must be set so that the end of a block coincides with the end of the extended repeat area range. If extended repeat area overflow occurs during a block-size transfer in block transfer mode, the extended repeat area overflow interrupt request is held pending until the end of the block, and transfer overrun will occur. The same caution is required when the extended repeat area overflow interrupt is used together with cluster transfer mode. Figure 11.16 shows an example in which block transfer mode is used together with the extended repeat area function.
When lower 3 bits (8-byte area) of EDSAR are designated as extended repeat area (SARA4 to SARA0 = 3), and block size of 5 (bits 23 to 16 in EDTCR = 5) is set in block transfer mode. External memory H'23FFFE H'23FFFF H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007 H'240008 H'240009 Range of EDSAR values First block transfer Second block transfer
...
H'240000 H'240001 H'240002 H'240003 H'240004 H'240005 H'240006 H'240007
H'240000 H'240001 H'240002 H'240003 H'240004
H'240000 H'240001
Interrupt requested
H'240005 H'240006 H'240007
Block transfer in progress
Figure 11.16 Example of Extended Repeat Area Function Operation in Block Transfer Mode
...
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Section 11 EXDMA Controller (EXDMAC)
11.5.6
Address Update Function Using Offset
There are the following update methods for transfer destination and source addresses: Fixed, increment/decrement by 1, 2 or 4, and offset addition. With the offset addition method, the offset specified by the offset register (EDOFR) is added each time the EXDMAC performs a dataaccess-size transfer. This function allows the mid-addresses being skipped during data transfer. Figure 11.17 shows the address update methods.
External memory
External memory
External memory
0
1, 2, or 4
+ Offset
Address not updated
Value, that corresponds to data access size, incremented, decremented to/from the address (Successive addresses) (b) Increment/decrement by 1, 2 or 4
Offset value added to the address (Insuccessive addresses)
(a) Fixed
(c) Offset addition
Figure 11.17 Address Update Method For the fixed method (a), the same address is always indicated without the transfer destination or source address being updated. For the method of increment/decrement by 1, 2 or 4 (b), the value corresponding to the data access size is incremented or decremented to or from the transfer destination or source address each time the data is transferred. A byte, word, or longword can be specified for the data access size. The value used for increment or decrement of an address is 1 for a byte-size , 2 for a word-size , and 4 for a longword-size transfer. This function allows continuous address transfer of EXDMAC.
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Section 11 EXDMA Controller (EXDMAC)
For the offset addition method (c), address operation is not performed based on the data access size. The EXDMAC adds the value set by EDOFR to the transfer destination or source address for each time the data is transferred. The EXDMAC sets the offset value in EDOFR and operates using EDSAR or EDDAR. The EXDMAC can only add the offset value, but subtraction of the offset value is also possible by setting a negative value in EDOFR. Specify a twos complement for a negative offset value. (1) Basic transfer using offset
Figure 11.18 shows the basic operation of transfer using an offset.
Data 1
Address A1 Transfer
Offset value
Data 1 Data 2 Data 3 Data 4 Data 5 :
Address B1 Address B2 = Address B1 + 4 Address B3 = Address B2 + 4 Address B4 = Address B3 + 4 Address B5 = Address B4 + 4
Data 2
Address A2 = Address A1 + Offset
: : :
Offset value
Data 3
Address A3 = Address A2 + Offset
Offset value
Data 4
Address A4 = Address A3 + Offset
Offset value
Transfer source: Offset added Transfer destination: Incremented by 4 (with a longword-size selected)
Data 5
Address A5 = Address A4 + Offset
Figure 11.18 Address Update Function Using Offset
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Section 11 EXDMA Controller (EXDMAC)
In figure 11.18, the offset addition method is set for updating the transfer source address, and the method of increment/decrement 1, 2 or 4 is set for updating the transfer destination address. For updating the second and subsequent transfer source addresses, the data of the address for which the offset value is added to the previous transfer address is read. This data is written to the successive area on the transfer destination. (2) Example of XY conversion using offset
Figure 11.19 shows the XY conversion by combining the repeat transfer mode and offset addition.
Data 1 Data 2 Data 3 Data 4 Data 5 Data 9 Data 13 Data 6 Data 10 Data 14 Data 7 Data 11 Data 15 Data 8 Data 12 Data 16 Data 1 Data 5 Data 9 Data 13 Data 2 Data 3 Data 6 Data 7 Data 10 Data 11 Data 14 Data 15
Transfer
First cycle Second cycle Third cycle First cycle
Data 4 Data 8 Data 12 Data 16
1st transfer
2nd transfer Transfer source 3rd transfer
address overwritten by CPU
Offset value
Offset value
Offset value
Data 1 Data 5 Data 9 Data 13 Data 2 Data 6 Data 10 Data 14 Data 3 Data 7 Data 11 Data 15 Data 4 Data 8 Data 12 Data 16
Address restored
Interrupt requested
Data 1 Data 5 Data 9 Data 13 Data 2 Data 6 Data 10 Data 14 Data 3 Data 7 Data 11 Data 15 Data 4 Data 8 Data 12 Data 16
Address restored
Interrupt requested
Data 1 Data 5 Data 9 Data 13 Data 2 Data 6 Data 10 Data 14 Data 3 Data 7 Data 11 Data 15 Data 4 Data 8 Data 12 Data 16
Transfer
Transfer source address overwritten by CPU
Interrupt requested
Data 1 Data 2 Data 3 Data 4 Data 5 Data 6 Data 7 Data 8 Data 9 Data 10 Data 11 Data 12 Data 13 Data 14 Data 15 Data 16
First cycle
Second cycle
Third cycle
Fourth cycle
Figure 11.19 XY Conversion by Combining Repeat Transfer Mode and Offset Addition In figure 11.19, the source address side is set as a repeat area in EDACR and the offset addition is set in EDACR. The offset value is the address that corresponds to 4 x data access size (example: for a longword-size transfer, H'00000010 is specified in EDOFR). The repeat size is 4 x data access size (example: for a longword-size transfer, 4 x 4 = 16 bytes are specified as a repeat size). The increment by 1, 2 or 4 is set for the transfer destination. The RPTIE bit in EDACR is set to 1 to generate a repeat size end interrupt request at the end of a repeat-size transfer.
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Section 11 EXDMA Controller (EXDMAC)
When transfer starts, the offset value is added to the transfer source address and the data is transferred. The data is aligned in the order of transfer in the transfer destination. After up to data 4 is transferred, the EXDMAC assumes that a repeat-size transfer completed, and restores the transfer source address to the transfer start address (address of transfer source data 1). At the same time, a repeat size end interrupt is requested. This interrupt request aborts the transfer temporarily. Overwrite the EDSAR value to the data 5 address by accessing the I/O register via the CPU. (For longword transfer, add 4 to the address of data 1.) When the DTE bit in EDMDR is set to 1, transfer is resumed from the state in which the transfer is aborted. The transfer source data is XYconverted and transferred to the transfer destination by repeating the above processing. Figure 11.20 shows the XY conversion flow.
Start Set address and transfer count Set repeat transfer mode Enable repeat cancel interrupt
Set DTE bit to 1
Transfer request accepted Data transfer Transfer counter and repeat size decremented No Transfer count = 0 Yes Set transfer source address + 4 (For longword transfer) End : User side :EXDMAC side No Repeat size = 0 Yes Transfer source address restored End of repeat size Interrupt requested
Figure 11.20 Flow of XY Conversion Combining Repeat Transfer Mode and Offset Addition
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Section 11 EXDMA Controller (EXDMAC)
(3)
Offset subtraction specification
To set a negative value in EDOFR, specify a twos complement as an offset value. A twos complement is derived by the following expression:
[Twos complement expression for negative offset value] = -[offset value] + 1 (-: bit reverse) Example: Twos complement expression of H'0001FFFF = H'FFFE0000 + H'00000001 = H'FFFE0001 A twos complement can be derived by the NEG.L instruction of the CPU.
11.5.7
Registers during EXDMA Transfer Operation
EXDMAC register values are updated as EXDMA transfer processing is performed. The updated values depend on various settings and the transfer status. The following registers and bits are updated: EDSAR, EDDAR, EDTCR, bits BKSZH and BKSZ in EDBSR, and bits DTE, ACT, ERRF, ESIF and DTIF in EDMDR. (1) EXDMA Source Address Register (EDSAR)
When the EDSAR address is accessed as the transfer source, the EDSAR value is output, and then EDSAR is updated with the address to be accessed next. Bits SAT1 and SAT0 in EDACR specify incrementing or decrementing. The address is fixed when SAT1 and SAT0 = B00, incremented by offset register value when SAT1 and SAT0 = B01, incremented when SAT1 and SAT0 = B10, and decremented when SAT1 and SAT0 = B11. (The increment or decrement value is determined by the data access size.) The DTSZ1 and DTSZ0 bits in EDMDR set the data access size. When DTSZ1 and DTSZ0 = B00, the data is byte-size and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B01, the data is word-size and the address is incremented or decremented by 2. When DTSZ1and DTSZ0 = B10, the data is longword-size and the address is incremented or decremented by 4. When a word-size or longword-size is specified but the source address is not at the word or longword boundary, the data is divided into bytes or words for reading. When a word or longword is divided for reading, the address is incremented or decremented by 1 or 2 according to an actual byte-or word-size read. After a word-size or longword-size read, the address is incremented or decremented to or from the read start address according to the setting of SAT1 and SAT0.
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Section 11 EXDMA Controller (EXDMAC)
When a block area (repeat area) is set for the source address in block transfer mode (or repeat transfer mode), the source address is restored to the transfer start address at the end of block-size (repeat-size) transfer and is not affected by address updating. When an extended repeat area is set for the source address, the operation conforms to that setting. The upper addresses set for the extended repeat area is fixed, and is not affected by address updating. When EDSAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDSAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. Do not write to EDSAR for a channel on which a transfer operation is in progress. (2) EXDMA Destination Address Register (EDDAR)
When the EDDAR address is accessed as the transfer destination, the EDDAR value is output, and then EDDAR is updated with the address to be accessed next. Bits DAT1 and DAT0 in EDACR specify incrementing or decrementing. The address is fixed when DAT1 and DAT0 = B00, incremented by offset register value when DAT1 and DAT0 = B01, incremented when DAT1 and DAT0 = B10, and decremented when DAT1 and DAT0 = B11. (The increment or decrement value is determined by the data access size.) The DTSZ1 and DTSZ0 bits in EDMDR set the data access size. When DTSZ1 and DTSZ0 = B00, the data is byte-size and the address is incremented or decremented by 1. When DTSZ1 and DTSZ0 = B01, the data is word-size and the address is incremented or decremented by 2. When DTSZ1 and DTSZ0 = B10, the data is longword-size and the address is incremented or decremented by 4. When a word-size or longword-size is specified but the destination address is not at the word or longword boundary, the data is divided into bytes or words for writing. When a word or a longword is divided for writing, the address is incremented or decremented by 1 or 2 according to an actual byte- or word-size written. After a word-size or longword-size write, the address is incremented or decremented to or from the write start address according to the setting of SAT1 and SAT0. When a block area (repeat area) is set for the destination address in block transfer mode (or repeat transfer mode), the destination address is restored to the transfer start address at the end of blocksize (repeat-size) transfer and is not affected by address updating. When an extended repeat area is set for the destination address, the operation conforms to that setting. The upper addresses set for the extended repeat area is fixed, and is not affected by address updating.
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Section 11 EXDMA Controller (EXDMAC)
When EDDAR is read during a transfer operation, a longword access must be used. During a transfer operation, EDDAR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. Do not write to EDDAR for a channel on which a transfer operation is in progress. (3) EXDMA Transfer Count Register (EDTCR)
When an EXDMA transfer is performed, the value in EDTCR is decremented by the number of bytes transferred. When a byte is transferred, the value is decremented by 1; when a word is transferred, the value is decremented by 2; when a longword is transferred, the value is decremented by 4. However, when the EDTCR value is 0, transfers are not counted and the EDTCR value does not change. All of the bits of EDTCR may change, so when EDTCR is read by the CPU during EXDMA transfer, a longword access must be used. During a transfer operation, EDTCR may be updated without regard to accesses from the CPU, and the correct values may not be read if the upper and lower words are read separately. Do not write to EDTCR for a channel on which a transfer operation is in progress. If there is conflict between an address update associated with EXDMA transfer and a write by the CPU, the CPU write has priority. In the event of conflict between an EDTCR update from 1, 2, or 4 to 0 and a write (of a nonzero value) by the CPU, the CPU write value has priority as the EDTCR value, but transfer is terminated. (4) EXDMA Block Size Register (EDBSR)
EDBSR is valid in block transfer or repeat transfer mode. EDBSR31 and EDBSR16 are used as BKSZH and EDBSR15 and EDBSR0 for BKSZ. The 16 bits of BKSZH holds a block size and repeat size and their values do not change. The 16 bits of BKSZ functions as a block size or repeat size counter, the value of which is decremented by 1 when one data transfer is performed. When the BKSZ value is determined as 0 during EXDMA transfer, the EXDMAC does not store 0 in BKSZ and stores the BKSZH value. The upper 16 bits of EDBSR is never updated, allowing a word-size access. Do not write to EDBSR for a channel on which a transfer operation is in progress.
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Section 11 EXDMA Controller (EXDMAC)
(5)
DTE Bit in EDMDR
The DTE bit in EDMDR is written to by the CPU to control enabling and disabling of data transfer, but may be cleared to 0 automatically by the EXDMAC due to the EXDMA transfer status. Conditions for DTE bit clearing by the EXDMAC include the following: * * * * * * * * * When the specified total transfer size is completely transferred A transfer size error interrupt is requested, and transfer ends A repeat size end interrupt is requested, and transfer ends When an extended repeat area overflow interrupt is requested, and transfer ends When an NMI interrupt is generated, and transfer halts When an address error is generated, and transfer halts A reset Hardware standby mode When 0 is written to the DTE bit, and transfer halts
Writes (except to the DTE bit) are prohibited to registers of a channel for which the DTE bit is set to 1. When changing register settings after a 0-write to the DTE bit, it is necessary to confirm that the DTE bit has been cleared to 0. Figure 11.21 shows the procedure for changing register settings in an operating channel.
Changing register settings in operating channel Write 0 to DTE bit [1] [1] Write 0 to the DTE bit in EDMDR [2] Read DTE bit. [3] Confirm that DTE bit = 0. If DTE bit = 1, this indicates that EXDMA transfer is in progress. [4] Write the required set values to the registers.
Read DTE bit
[2]
DTE bit = 0 Yes Change register settings Register setting changes completed
No
[3]
[4]
Figure 11.21 Procedure for Changing Register Settings in Operating Channel
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Section 11 EXDMA Controller (EXDMAC)
(6)
ACT bit in EDMDR
The ACT bit in EDMDR indicates whether the EXDMAC is in standby or active state. When DTE = 0 and DTE = 1 (transfer request wait status) are specified, the ACT bit is set to 0. In another case (EXDMAC in the active state), the ACT bit is set to 1. The ACT bit is held to 1 during EXDMA transfer even if 0 is written to the DTE bit to halt transfer. In block transfer mode, a block-size transfer is not halted even if 0 is written to the DTE bit to halt transfer. The ACT bit is held to 1 until a block-size transfer completes after 0 is written to the DTE bit. In burst mode, transfer is halted after up to three times of EXDMA transfers are performed since the bus cycle in which 0 is written to the DTE bit has been processed. The ACT bit is held to 1 between termination of the last EXDMA cycle and 0-write in the DTE bit. (7) ERRF bit in EDMDR
This bit specifies termination of transfer by EXDMAC clearing the DTE bit to 0 for all channels if an address error or NMI interrupt is generated. The EXDMAC also sets 1 to the ERRF bit of EDMDR_0 regardless of the EXDMAC operation to indicate that an address error or NMI interrupt is generated. However, when an address error or an NMI interrupt has been generated in EXDMAC module stop mode, the ERRF bit is not set to 1. (8) ESIF bit in EDMDR
The ESIF bit in EDMDR is set to 1 when a transfer size interrupt, repeat size end interrupt, or an extended repeat area overflow interrupt is requested. When the ESIF bit is set to 1 and the ESIE bit in EDMDR is set to 1, a transfer escape interrupt is requested to the CPU or DTC. The timing that the ESIF bit is set to 1 is when the EXDMA transfer bus cycle (the source of an interrupt request) terminates, the ACT bit in EDMDR is set to 0, and transfer is terminated. When the DTE bit is set to 1 to resume transfer during interrupt processing, the ESIF bit is automatically cleared to 0 to cancel the interrupt request. For details on interrupts, see section 11.9, Interrupt Sources.
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Section 11 EXDMA Controller (EXDMAC)
(9)
DTIF bit in EDMDR
The DTIF bit in EDMDR is set to 1 after the data of total transfer size is transferred completely by EXDMA transfer. When the DTIF bit is set to 1 and the DTIE bit in EDMDR is set to 1, a transfer end interrupt by the transfer counter is requested to the CPU or DTC. The timing that the DTIF bit is set to 1 is when the EXDMA transfer bus cycle is terminated, the ACT bit in EDMDR is set to 0, and the transfer is terminated. When the DTE bit is set to 1 to resume transfer during interrupt processing, the DTIF bit is automatically cleared to 0 to cancel the interrupt request. For details on interrupts, see section 11.9, Interrupt Sources. 11.5.8 Channel Priority Order
The priority order of the EXDMAC channels is: channel 0 > channel 1 > channel 2 > channel 3. Table 11.6 shows the EXDMAC channel priority order. Table 11.6 EXDMAC Channel Priority Order
Channel Channel 0 Channel 1 Channel 2 Channel 3 Low Channel Priority High
If transfer requests occur simultaneously for a number of channels, the highest-priority channel according to the priority order is selected for transfer. Transfer starts after the channel in progress releases the bus. If a bus request is issued from another bus master other than EXDMAC during a transfer operation, another bus master cycle is initiated. Channels are not switched during burst transfer, a block-size transfer in block transfer mode or a cluster-size transfer in cluster transfer mode. Figure 11.22 shows an example of the transfer timing when transfer requests occur simultaneously for channels 0, 1, and 2.
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Section 11 EXDMA Controller (EXDMAC)
Channel 0 transfer
B
Channel 1 transfer
Channel 2 transfer
Address bus
EXDMAC control
Channel 0 Idle Channel 0
Request cleared
Channel 1 Channel 2
Channel 2 Idle
Channel 1
Channel 0
Channel 1
Request cleared Request Selected held Request Not Request selected held held Selected Request cleared
Channel 2
Figure 11.22 Example of Channel Priority Timing 11.5.9 Basic Bus Cycles
An example of the basic bus cycle timing is shown in figure 11.23. In this example, word-size transfer is performed from 16-bit, 2-state access space to 8-bit, 3-state access space. When the bus mastership is transferred from the CPU to the EXDMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As like CPU cycles, EXDMAC cycles conform to the bus controller settings.
CPU cycle
T1
B
EXDMAC cycle (one word transfer)
T2 T1 T2 T3 T1 T2 T3
CPU cycle
Source address
Destination address
Address bus
RD High
LHWR
LLWR
Figure 11.23 Example of EXDMA Transfer Bus Timing
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Section 11 EXDMA Controller (EXDMAC)
11.5.10 Bus Cycles in Dual Address Mode (1) Normal Transfer Mode (Cycle Steal Mode)
In cycle steal mode, the bus is released after one byte, word, or longword has been transferred. While the bus is released, one CPU, DMAC, or DTC bus cycle is initiated. Figure 11.24 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space.
EXDMA read EXDMA write
EXDMA read EXDMA write
EXDMA read EXDMA write
B
Address bus
RD
LHWR, LLWR ETEND
Bus release
Bus release
Bus release
Last transfer cycle
Bus release
Figure 11.24 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer Figures 11.25 and 11.26 show examples of transfer when ETEND output is enabled, and longword-size, normal transfer mode (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. In figure 11.25, the transfer source (SAR) address is not at a longword boundary and the transfer destination (DAR) address is at the longword boundary. In figure 11.26, the transfer source (SAR) address is at the longword boundary and the transfer destination (DAR) address is not at the longword boundary.
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Section 11 EXDMA Controller (EXDMAC)
EXDMA byte EXDMA word EXDMA byte EXDMA word EXDMA word read cycle read cycle read cycle write cycle write cycle
EXDMA byte EXDMA word EXDMA byte EXDMA word EXDMA word read cycle read cycle read cycle write cycle write cycle
B Address bus RD LHWR LLWR TEND
Bus released Bus released Last transfer cycle Bus released
4m + 1
4m + 2
4m + 4
4n
4n + 2
4m + 5
4m + 6
4m + 8
4n + 4
4n + 6
m and n are integers.
Figure 11.25 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer (Transfer Source EDSAR = Odd Address, Source Address Incremented)
EXDMA word EXDMA word EXDMA byte EXDMA word EXDMA byte read cycle read cycle write cycle write cycle write cycle EXDMA word EXDMA word EXDMA byte EXDMA word EXDMA byte read cycle read cycle write cycle write cycle write cycle
B Address bus RD LHWR LLWR ETEND Bus released Bus released Last transfer cycle Bus released 4m 4m + 2 4n + 5 4n + 6 4n + 8 4m + 4 4m + 6 4n + 1 4n + 2 4n + 4
m and n are integers.
Figure 11.26 Example of Normal Transfer Mode (Cycle Steal Mode) Transfer (Transfer Destination EDDAR = Odd Address, Destination Address Decremented)
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Section 11 EXDMA Controller (EXDMAC)
(2)
Normal Transfer Mode (Burst Mode)
In burst mode, one-byte, one-word, or one-longword transfer is executed continuously until the transfer end condition is satisfied. Once burst transfer starts, requests from other channels, even of higher priority, are held pending until burst transfer ends. Figure 11.27 shows an example of transfer when ETEND output is enabled, and word-size, normal transfer mode (burst mode) is performed from external 16-bit, 2-state access space to external 16bit, 2-state access space.
EXDMA read EXDMA write B Address bus EXDMA read
EXDMA write EXDMA read
EXDMA write
RD LHWR, LLWR ETEND Bus release Burst transfer Last transfer cycle Bus release
Figure 11.27 Example of Normal Transfer Mode (Burst Mode) Transfer
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Section 11 EXDMA Controller (EXDMAC)
(3)
Block Transfer Mode
In block transfer mode, one block is transferred in response to one transfer request, and after the transfer, the bus is released. Figure 11.28 shows an example of transfer when ETEND output is enabled, and word-size, block transfer mode is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space.
EXDMA read B Address bus RD LHWR, LLWR ETEND Bus release Block transfer Bus release Last block transfer cycle Bus release EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write EXDMA read EXDMA write
Figure 11.28 Example of Block Transfer Mode Transfer
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Section 11 EXDMA Controller (EXDMAC)
(4)
EDREQ Pin Falling Edge Activation Timing
Figure 11.29 shows an example of normal transfer mode transfer activated by the EDREQ pin falling edge. EDREQ pin sampling is performed in each cycle starting at the next rise of B after the end of the DTE bit write cycle. When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the EXDMA write cycle, acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is performed again. This sequence of operations is repeated until the end of the transfer.
Bus release EXDMA read EXDMA write Bus release EXDMA read EXDMA write Bus release
B EDREQ Address bus EXDMA control Channel
Idle Read
Transfer source Transfer destination Transfer source Transfer destination
Write
Idle
Read
Write
Idle
Request
Request clearance period
Request
Request clearance period
Minimum 3 cycles
Minimum 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Acceptance resumed
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of B, and request is held. [2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC. [3], [6] EXDMA cycle starts; EDREQ pin high level sampling is started at rise of B. [4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle. (As in [1], EDREQ pin low level is sampled at rise of B, and request is held.)
Figure 11.29 Example of Normal Transfer Mode Transfer Activated by EDREQ Pin Falling Edge
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Section 11 EXDMA Controller (EXDMAC)
Figure 11.30 shows an example of block transfer mode transfer activated by the EDREQ pin falling edge. EDREQ pin sampling is performed in each cycle starting at the next rise of B after the end of the DTE bit write cycle. When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the EXDMA write cycle, acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is performed again. This sequence of operations is repeated until the end of the transfer.
One block transfer Bus release EXDMA read EXDMA write Bus release One block transfer EXDMA read EXDMA write Bus release
B EDREQ Address bus EXDMA control
Idle Read Transfer source Write Transfer destination Idle Read Transfer source Write Transfer destination Idle
Channel
Request
Request clearance period
Request
Request clearance period
Minimum 3 cycles
Minimum 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Acceptance resumed
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of B, and request is held. [2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC. [3], [6] EXDMA cycle starts; EDREQ pin high level sampling is started at rise of B. [4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle. (As in [1], EDREQ pin low level is sampled at rise of B, and request is held.)
Figure 11.30 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Falling Edge
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Section 11 EXDMA Controller (EXDMAC)
(5)
EDREQ Pin Low Level Activation Timing
Figure 11.31 shows an example of normal transfer mode transfer activated by the EDREQ pin low level. EDREQ pin sampling is performed in each cycle starting at the next rise of B after the end of the DTE bit write cycle. When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. After the end of the write cycle, acceptance resumes and EDREQ pin low level sampling is performed again. This sequence of operations is repeated until the end of the transfer.
Bus release
EXDMA read EXDMA write
Bus release
EXDMA read
EXDMA write
Bus release
B EDREQ Address bus EXDMA control
Idle Read Transfer source Write Transfer destination Idle Read Transfer source Write Transfer destination Idle
Channel
Request
Duration of transfer request disabled
Request
Duration of transfer request disabled
Minimum 3 cycles
Minimum 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Transfer request enable resumed
Transfer request enable resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of B, and request is held. [2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC. [3], [6] EXDMA cycle starts. [4], [7] Acceptance is resumed after completion of write cycle. (As in [1], EDREQ pin low level is sampled at rise of B, and request is held.)
Figure 11.31 Example of Normal Transfer Mode Transfer Activated by EDREQ Pin Low Level
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Section 11 EXDMA Controller (EXDMAC)
Figure 11.32 shows an example of block transfer mode transfer activated by the EDREQ pin low level. EDREQ pin sampling is performed in each cycle starting at the next rise of B after the end of the DTE bit write cycle. When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. After the end of the write cycle, acceptance resumes and EDREQ pin low level sampling is performed again. This sequence of operations is repeated until the end of the transfer.
One block transfer Bus release EXDMA read EXDMA write Bus release One block transfer EXDMA read EXDMA write Bus release
B EDREQ Address bus EXDMA control
Idle Read Transfer source Write Transfer destination Idle Read Transfer source Write Transfer destination Idle
Channel
Request
Request clearance period
Request
Request clearance period
Minimum 3 cycles
Minimum 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Acceptance resumed
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of B, and request is held. [2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC. [3], [6] EXDMA cycle starts. [4], [7] Acceptance is resumed after completion of write cycle. (As in [1], EDREQ pin low level is sampled at rise of B, and request is held.)
Figure 11.32 Example of Block Transfer Mode Transfer Activated by EDREQ Pin Low Level
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Section 11 EXDMA Controller (EXDMAC)
(6)
EDREQ Pin Low Level Activation Timing with NRD = 1 Specified
When the NRD bit is set to 1 in EDMDR, the acceptance timing of the next transfer request can be delayed one cycle later. Figure 11.33 shows an example of normal transfer mode transfer activated by the EDREQ pin low level with NRD = 1 specified. EDREQ pin sampling is performed in each cycle starting at the next rise of B after the end of the DTE bit write cycle. When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. After the end of the write cycle, acceptance resumes when one cycle of the request clearance period specified by NRD = 1 expires and EDREQ pin low level sampling is performed again. This sequence of operations is repeated until the end of the transfer.
EXDMA read EXDMA write Bus release EXDMA read EXDMA write
Bus release
Bus release
B EDREQ Address bus
Transfer source Transfer destination Transfer source Transfer destination
Channel
Extended request clearance period specified by NRD
Request
Request clearance period
Request
Request clearance period
Extended request clearance period specified by NRD
Minimum 3 cycles
Minimum 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Acceptance resumed
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of B, and request is held. [2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC. [3], [6] EXDMA cycle starts. [4], [7] Acceptance is resumed after completion of write cycle plus one cycle. (As in [1], EDREQ pin low level is sampled at rise of B, and request is held.)
Figure 11.33 Example of Normal Transfer Mode Transfer Activated by EDREQ Pin Low Level with NRD = 1 Specified
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Section 11 EXDMA Controller (EXDMAC)
11.5.11 Bus Cycles in Single Address Mode (1) Single Address Mode (Read in Cycle Steal Mode)
In single address mode, the bus is released after one byte, word, or longword has been transferred in response to one transfer request. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. Figure 11.34 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device.
EXDMA read B Address bus RD EDACK ETEND
Bus released Bus release Bus release Bus Last transfer Bus release release cycle
EXDMA read
EXDMA read
EXDMA read
Figure 11.34 Example of Single Address Mode (Byte Read) Transfer
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Section 11 EXDMA Controller (EXDMAC)
(2)
Single Address Mode (Write in Cycle Steal Mode)
In single address mode, the bus is released after one byte, word, or longword has been transferred in response to one transfer request. While the bus is released, one or more CPU, DMAC, or DTC bus cycles are initiated. Figure 11.35 shows an example of transfer when ETEND output is enabled, and byte-size, single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space.
EXDMA write B EXDMA write EXDMA write EXDMA write
Address bus
LLWR
EDACK
ETEND Bus release Bus release Bus release Bus release Last transfer Bus release cycle
Figure 11.35 Example of Single Address Mode (Byte Write) Transfer
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Section 11 EXDMA Controller (EXDMAC)
(3)
EDREQ Pin Falling Edge Activation Timing
Figure 11.36 shows an example of single address mode transfer activated by the EDREQ pin falling edge. EDREQ pin sampling is performed in each cycle starting at the next rise of B after the end of the DTE bit write cycle. When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the EXDMA single cycle, acceptance resumes after the end of the single cycle, and EDREQ pin low level sampling is performed again. This sequence of operations is repeated until the end of the transfer.
Bus release B Bus release Bus EXDMA single release
EXDMA single
EDREQ Address bus EDACK EXDMA control Idle Single Idle Single Idle
Transfer source/ Transfer destination Transfer source/ Transfer destination
Channel
Request
Request clearance period
Request
Request clearance period
Minimum 3 cycles [1] [2] [3] [4]
Minimum 3 cycles [5] [6] [7]
Acceptance resumed
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of B, and request is held. [2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC. [3], [6] EXDMA cycle starts; EDREQ pin high level sampling is started at rise of B. [4], [7] When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle. (As in [1], EDREQ pin low level is sampled at rise of B, and request is held.)
Figure 11.36 Example of Single Address Mode Transfer Activated by EDREQ Pin Falling Edge
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Section 11 EXDMA Controller (EXDMAC)
(4)
EDREQ Pin Low Level Activation Timing
Figure 11.37 shows an example of single address mode transfer activated by the EDREQ pin low level. EDREQ pin sampling is performed in each cycle starting at the next rise of B after the end of the DTE bit write cycle. When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. After the end of the single cycle, acceptance resumes and EDREQ pin low level sampling is performed again. This sequence of operations is repeated until the end of the transfer.
Bus release B Bus release Bus release
EXDMA single
EXDMA single
EDREQ
Transfer source/ Transfer destination
Address bus EDACK EXDMA control Idle
Transfer source/ Transfer destination
Single
Idle
Single
Idle
Channel
Request
Request clearance period
Request
Request clearance period
Minimum 3 cycles [1] [2] [3]
Minimum 3 cycles [4] [5] [6] [7]
Acceptance resumed
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of B, and request is held. [2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC. [3], [6] EXDMA cycle starts. [4], [7] Acceptance is resumed after completion of single cycle. (As in [1], EDREQ pin low level is sampled at rise of B, and request is held.)
Figure 11.37 Example of Single Address Mode Transfer Activated by EDREQ Pin Low Level
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Section 11 EXDMA Controller (EXDMAC)
(5)
EDREQ Pin Low Level Activation Timing with NRD = 1 Specified
When the NRD bit is set to 1 in EDMDR, the acceptance timing of the next transfer request can be delayed one cycle later. Figure 11.38 shows an example of single address mode transfer activated by the EDREQ pin low level with NRD = 1 specified. EDREQ pin sampling is performed in each cycle starting at the next rise of B after the end of the DTE bit write cycle. When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. After the end of the single cycle, acceptance resumes when one cycle of the request clearance period specified by NRD = 1 expires and EDREQ pin low level sampling is performed again. This sequence of operations is repeated until the end of the transfer.
Bus release Bus release Bus release
EXDMA single
EXDMA single
B
EDREQ
Transfer source/ Transfer destination Transfer source/ Transfer destination
Address bus
Extended request clearance period specified by NRD Extended request clearance period specified by NRD Request clearance period
Channel
Request
Request clearance period
Request
Minimum 3 cycles
Minimum 3 cycles
[1]
[2]
[3]
[4]
[5]
[6]
[7]
Acceptance resumed
Acceptance resumed
[1] Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of B, and request is held. [2], [5] Request is cleared at end of next bus cycle, and activation is started in EXDMAC. [3], [6] EXDMA cycle starts. [4], [7] Acceptance is resumed after completion of write cycle plus one cycle. (As in [1], EDREQ pin low level is sampled at rise of B, and request is held.)
Figure 11.38 Example of Single Address Mode Transfer Activated by EDREQ Pin Low Level with NRD = 1 Specified
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Section 11 EXDMA Controller (EXDMAC)
11.5.12 Operation Timing in Each Mode This section describes examples of operation timing in each mode. The CPU external bus cycle is shown as an example of conflict with another bus master. (1) Auto-Request/Normal Transfer Mode/Cycle Steal Mode
With auto-request (in cycle steal mode), when the DTE bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. If there is a transfer request for another channel of higher priority, the transfer request by the original channel is held pending, and transfer is performed on the higher-priority channel from the next transfer. Transfer on the original channel is resumed on completion of the higher-priority channel transfer. Figures 11.39 and 11.40 show operation timing examples for various conditions.
3 cycles
3 cycles
3 cycles
B
Last transfer cycle
Bus cycle CPU operation ETEND
Bus release
EXDMA read
EXDMA write
Bus release
EXDMA read
EXDMA write
Bus release
EXDMA read
EXDMA write
Bus release
DTE 1 write
Internal bus space cycles
DTE bit
0
1
0
Figure 11.39 Auto-Request/Normal Transfer Mode/Cycle Steal Mode (No Conflict/Dual Address Mode)
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Section 11 EXDMA Controller (EXDMAC)
B
One bus cycle Last transfer cycle
Bus cycle
CPU operation
CPU cycle
EXDMA single transfer cycle
CPU cycle
EXDMA single transfer cycle
CPU cycle
EXDMA single transfer cycle
CPU cycle
External space
External space
External space
External space
EDACK ETEND
Figure 11.40 Auto-Request/Normal Transfer Mode/Cycle Steal Mode (CPU Cycles/Single Address Mode) (2) Auto-Request/Normal Transfer Mode/Burst Mode
With auto-request (in burst mode), when the DTE bit is set to 1 in EDMDR, an EXDMA transfer cycle is started a minimum of three cycles later. Once transfer is started, it continues (as a burst) until the transfer end condition is satisfied. Transfer requests for other channels are held pending until the end of transfer on the current channel. Figures 11.41 to 11.43 show operation timing examples for various conditions.
B Last transfer cycle Bus cycle CPU cycle CPU cycle EXDMAC read EXDMAC write EXDMAC read EXDMAC write Repeated EXDMAC read EXDMAC write CPU cycle
CPU operation ETEND DTE bit
External space
External space
External space
1
0
Figure 11.41 Auto-Request/Normal Transfer Mode/Burst Mode (CPU Cycles/Dual Address Mode)
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Section 11 EXDMA Controller (EXDMAC)
B
Last transfer cycle
Bus cycle EDACK of current channel ETEND of current channel Transfer request of another channel EDREQ
Bus release
EXDMAC single transfer cycle
EXDMAC single transfer cycle
EXDMAC single transfer cycle
EXDMAC cycle of another channel
Bus release
Figure 11.42 Auto-Request/Normal Transfer Mode/Burst Mode (Conflict with Another Channel/Single Address Mode)
Bus cycle EXDMA EXDMA CPU EXDMA CPU EXDMA EXDMA
CPU operation Internal space
External space
External space
Internal space
Figure 11.43 External Bus Master Cycle Steal Function (Auto-Request/Normal Transfer Mode/Burst Mode with CPU Cycles/Single Address Mode/EBCCS = 1) (3) External Request/Normal Transfer Mode/Cycle Steal Mode
In external request mode, an EXDMA transfer cycle is started a minimum of three cycles after a transfer request is accepted. The next transfer request is accepted after the end of a one-transferunit EXDMA cycle. For external bus space CPU cycles, at least one bus cycle is generated before the next EXDMA cycle. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next EXDMA cycle. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing.
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Section 11 EXDMA Controller (EXDMAC)
Figures 11.44 to 11.47 show operation timing examples for various conditions.
B
EDREQ EDRAK 3 cycles Bus cycle Bus release EXDMA read EXDMA write Bus release Last transfer cycle EXDMA read EXDMA write Bus release
ETEND DTE bit
1
0
Figure 11.44 External Request/Normal Transfer Mode/Cycle Steal Mode (No Conflict/Dual Address Mode/Low Level Sensing)
B
EDREQ EDRAK One bus cycle Bus cycle CPU cycle CPU cycle EXDMAC single transfer cycle CPU cycle Last transfer cycle EXDMAC single transfer cycle CPU cycle
CPU operation
External space
External space
External space
External space
EDACK
ETEND
Figure 11.45 External Request/Normal Transfer Mode/Cycle Steal Mode (CPU Cycles/Single Address Mode/Low Level Sensing)
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Section 11 EXDMA Controller (EXDMAC)
B
EDREQ
EDRAK EDREQ acceptance internal processing state CPU operation
Start of transfer by Start of transfer by Start of high level sensing internal edge Start of high level sensing internal edge confirmation confirmation
Start of transfer by internal edge Start of high level sensing confirmation
Bus release
EXDMAC single transfer cycle
Bus release
EXDMAC single transfer cycle
Bus release
EXDMAC single transfer cycle
EDACK
Figure 11.46 External Request/Normal Transfer Mode/Cycle Steal Mode (No Conflict/Single Address Mode/Falling Edge Sensing)
B
EDREQ of current channel
EDRAK of current channel
3 cycles
Bus cycle
EXDMAC transfer cycle
Bus release
EXDMA read
EXDMA write
Transfer cycles of another channel
EXDMA read
EXDMA write
EDREQ of another channel
EDRAK of another channel
Figure 11.47 External Request/Normal Transfer Mode/Cycle Steal Mode (Conflict with Another Channel/Dual Address Mode/Low Level Sensing)
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Section 11 EXDMA Controller (EXDMAC)
(4)
External Request/Block Transfer Mode/Cycle Steal Mode
In block transfer mode, transfer of one block is performed continuously in the same way as in burst mode. The timing of the start of the next block transfer is the same as in normal transfer mode. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next block transfer. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 11.48 to 11.52 show operation timing examples for various conditions.
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B
EDREQ
EDRAK
One block size transfer period
Last block End of block 3 cycles Last transfer cycle
Bus cycle
Repeated
Bus release
EXDMA read EXDMA write EXDMA write
EXDMA read
EXDMA read
EXDMA write
Bus release
EXDMA read
EXDMA write
EXDMA read Repeated
EXDMA write Bus release
ETEND
Figure 11.48 External Request/Block Transfer Mode/Cycle Steal Mode (No Conflict/Dual Address Mode/Low Level Sensing)
1
Section 11 EXDMA Controller (EXDMAC)
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DTE bit
0
REJ09B0413-0200
REJ09B0413-0200
One block size transfer period End of block 3 cycles Last block Last transfer cycle EXDMA single transfer cycle Repeated EXDMA single transfer cycle EXDMA single transfer cycle Bus release EXDMA single transfer cycle EXDMA single transfer cycle Repeated Bus release
B
Section 11 EXDMA Controller (EXDMAC)
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EDREQ
EDRAK
Bus cycle
Bus release
EDACK
Figure 11.49 External Request/Block Transfer Mode/Cycle Steal Mode (No Conflict/Single Address Mode/Falling Edge Sensing)
ETEND
B
EDREQ
EDRAK
One block size transfer period End of block Bus cycle CPU cycle One block size transfer period Last block
Bus cycle CPU cycle
CPU cycle
Repeated
EXDMA single transfer cycle
EXDMA single transfer cycle
EXDMA single transfer cycle
EXDMA single transfer cycle
Repeated External space
CPU cycle
CPU operation
External space External space
External space
EDACK
Figure 11.50 External Request/Block Transfer Mode/Cycle Steal Mode (CPU Cycles/Single Address Mode/Low Level Sensing)
Section 11 EXDMA Controller (EXDMAC)
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ETEND
REJ09B0413-0200
REJ09B0413-0200
One block size transfer period End of block One block size transfer period Last block
B
Section 11 EXDMA Controller (EXDMAC)
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Bus release
Repeated
EDREQ
EDRAK
Bus cycle
EXDMA read
EXDMA write
EXDMA read
EXDMA write
EXDMA cycle of another channel
EXDMA read
EXDMA write
EXDMA read
Repeated
EXDMA write
ETEND
EDREQ of another channel
Figure 11.51 External Request/Block Transfer Mode/Cycle Steal Mode (Conflict with Another Channel/Dual Address Mode/Low Level Sensing)
EDRAK of another channel
B
EDREQ
EDRAK
One block size transfer period End of block One block size transfer period
Bus cycle
CPU cycle EXDMA single transfer cycle
Last block
EXDMA single transfer cycle
Repeated
Bus cycle
CPU cycle CPU cycle
Repeated
EXDMA single transfer cycle
EXDMA single transfer cycle
CPU cycle
CPU operation External space External space External space
External space
EDACK
Figure 11.52 External Request/Block Transfer Mode/Cycle Steal Mode (CPU Cycles/EBCCS = 1/Single Address Mode/Low Level Sensing)
Section 11 EXDMA Controller (EXDMAC)
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ETEND
REJ09B0413-0200
Section 11 EXDMA Controller (EXDMAC)
11.6
Operation in Cluster Transfer Mode
In cluster transfer mode, transfer is performed by the consecutive read and write operations of 1 to 32 bytes using the cluster buffer. A part of the cluster transfer mode function differs from the ordinary transfer mode functions (normal transfer, repeat transfer, and block transfer modes). 11.6.1 (1) Address Mode
Cluster Transfer Dual Address Mode (AMS = 0)
In this mode, both the transfer source and destination addresses are specified for transfer in the EXDMAC internal registers. The transfer source address is set in the source address register (EDSAR), and the transfer destination address is set in the destination address register (EDDAR). The transfer is processed by performing the consecutive read of a cluster-size from the transfer source address and then the consecutive write of that data to the transfer destination address. One data access size to 32 bytes can be specified as a cluster size. When one data access size is specified as a cluster size, block transfer mode (dual address mode) is used. The cycles in a cluster-size transfer are indivisible: another bus cycle (external access by another bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for the last write cycle. The EDACK signal is not output. Figure 11.53 shows the data flow in the cluster transfer mode (dual address mode), figure 11.54 shows an example of the timing in cluster transfer dual address mode, and figure 11.55 shows the cluster transfer dual address mode operation.
LSI Transfer source: External memory
EDSAR access Read Read Read Read
Transfer destination: External device EDDAR acces
Write Write Write Write
Cluster buffer One cluster size Consecutive read Consecutive write One cluster size
Figure 11.53 Data Flow in Cluster Transfer Dual Address Mode
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Section 11 EXDMA Controller (EXDMAC)
EXDMA read cycle B Address bus RD WR ETEND EDSAR EDSAR EDSAR EDDAR
EXDMA write cycle
EDDAR
EDDAR
Figure 11.54 Timing in Cluster Transfer Dual Address Mode
Address TA First cluster
Transfer Cluster size: BKSZH x Data accsess size
Address TB First cluster
Second cluster
Second cluster
Nth cluster Address BA
Nth cluster
Address BB
Figure 11.55 Cluster Transfer Dual Address Mode Operation When a word or longword is specified as a data access size but the source or destination address is not at the word or longword boundary, use the appropriate data access size for efficient data transfer. In an example shown in figure 11.56, a longword-size transfer is performed with 4-longword specified as a cluster size in the cluster transfer dual address mode from the lower two bits of B'11 to B'10.
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Section 11 EXDMA Controller (EXDMAC)
The cluster size is decremented regardless of the read or write operation in the consecutive write sequences.
Transfer source memory MSB
LSB
CLSBR0
1
2
3
4
5
Cluster buffer
Transfer destination memory
2
3
4
Byte 1 H'AA0000 H'AA0004 H'AA0008 H'AA000C H'AA0010 Long Word 2 Long Word 3 Long Word 4 Word 5 Byte 6
CLSBR3 CLSBR4 CLSBR5 CLSBR6
CLSBR7
CLSBR1 CLSBR2
H'BB0000 H'BB0004 6 H'BB0008 H'BB000C H'BB0010
Word Long Word Long Word Long Word Word
Figure 11.56 Odd Address Transfer (2) Cluster Transfer Read Address Mode (AMS = 1, DIRS = 0)
In this mode, the transfer source address is specified in the source address register (EDSAR) and data is read from the transfer source and transferred to the cluster buffer. In this mode, the TSEIE bit in the mode control register (EDMDR) must be set to 1. Two data access size to 32 bytes can be specified as a cluster size for the consecutive read operation. The cycles in a cluster-size transfer are indivisible: another bus cycle (external access by another bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for the last read cycle. When an idle cycle is inserted before the last read cycle, the ETEND signal is also output in the idle cycle. In this mode, the EDACKE bit in EDMDR must be set to 0 to disable the EDACK pin output. Figure 11.57 shows the data flow in the cluster transfer read address mode (from the external memory to the cluster buffer), and figure 11.58 shows an example of the timing in cluster transfer read address mode.
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Section 11 EXDMA Controller (EXDMAC)
LSI
Address bus
Cluster buffer
EDSAR access
Transfer source external memory
External data bus
CPU Register read
Figure 11.57 Data Flow in Cluster Transfer Read Address Mode ( from External Memory to Cluster Buffer)
EXDMA read cycle
B
Address bus
EDSAR
EDSAR
EDSAR
RD WR
High
ETEND
Figure 11.58 Timing in Cluster Transfer Read Address Mode (from External Memory to Cluster Buffer)
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Section 11 EXDMA Controller (EXDMAC)
(3)
Cluster Transfer Write Address Mode (AMS = 1, DIRS = 1)
In this mode, the transfer destination address is specified in the destination address register (EDDAR) and data in the cluster butter is written to the transfer destination. In this mode, the TSEIE bit in the mode control register (EDMDR) must be set to 1. One data access size to 32 bytes can be specified as a cluster size for the consecutive write operation. When one data access size is specified as a cluster size, the cluster transfer write address mode is used. The cycles in a cluster-size transfer are indivisible: another bus cycle (external access by another bus master, refresh cycle, or external bus release cycle) does not occur in a cluster-size transfer. ETEND pin output can be enabled or disabled by means of the ETENDE bit in EDMDR. ETEND is output for the last write cycle. When an idle cycle is inserted before the last write cycle, the ETEND signal is also output in the idle cycle. In this mode, the EDACKE bit in EDMCR must be set to 0 to disable the EDACK pin output. Figure 11.59 shows the data flow in the cluster transfer write address mode (from the cluster buffer to the external memory), and figure 11.60 shows an example of the timing in cluster transfer write address mode.
LSI
Address bus
Cluster buffer
EDDAR access
External data bus
Transfer destination external memory
When initializing an area by the specified data, write the specified data from cluster buffer 0 into a register sequentially. Then, specify the buffer size written in the register as a cluster size and the area to be initialized as DAR, and then execute transfer in this mode.
Figure 11.59 Data Flow in Cluster Transfer Write Address Mode (from Cluster Buffer to External Memory)
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Section 11 EXDMA Controller (EXDMAC)
EXDMA write cycle
B
Address bus
EDDAR
EDDAR
EDDAR
RD WR
High
ETEND
Figure 11.60 Timing in Cluster Transfer Write Address Mode (from Cluster Buffer to External Memory) 11.6.2 Setting of Address Update Mode
The cluster transfer mode transfer is restricted by the address update mode function. There are the following four address update methods: increment, decrement, fixed, and offset addition. When the address increment method is specified and if the specified address is not at the address boundary for the data access size (odd address for a word-size transfer, address beyond the 4n boundary for a longword-size transfer), the bus cycle is divided for transfer until the address becomes at the address boundary. When the address matches the boundary, transfer is processed in units of data access sizes. At the end of transfer, the bus cycle is divided again to transfer the remaining data in cluster transfer mode. With address decrement, fixed, or offset addition method, specify the address, that matches the address boundary for the data access size, in EDSAR and EDDAR. When specifying the address, that is not at the address boundary for the data access size, in EDSAR and EDDAR, fix the lower bit to 0 (lower one bit for a word-size transfer, and lower two bits for a longword-size transfer) in the address register so that the transfer is processed in units of data access sizes. The block transfer mode must be used for transfer of data by dividing the bus cycle according to the address boundary. When the EDTCR value is smaller than the cluster size, a transfer size error occurs. In this case, when the TSEIE bit in EDMDR is cleared to 0, the cluster transfer mode is switched to the block transfer mode to process the remaining data. With the decrement, fixed, or offset addition method, transfer is performed without fixing the lower bit to 0.
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Section 11 EXDMA Controller (EXDMAC)
11.6.3
Caution for Combining with Extended Repeat Area Function
As with the block transfer mode, the address register value must be set in cluster transfer mode, so that the end of the cluster size coincides with the end of the extended repeat area range. When an extended repeat area overflow occurs during a cluster-size transfer in the cluster transfer mode, the extended repeat area overflow interrupt request is held pending until the end of a cluster-size transfer, and transfer overrun will occur. 11.6.4 (1) Bus Cycles in Cluster Transfer Dual Address Mode
Cluster transfer mode
In cluster transfer mode, a cluster-size transfer is processed in response to one transfer request. In an example shown in figure 11.61, the ETEND pin output is enabled, and word-size transfer is performed with 4-byte cluster size in cluster transfer mode from the external 16-bit, 2-state access space to the external 16-bit, 2-state access space.
Bus release
EXDMA read B Address bus RD LHWR, LLWR ETEND
EXDMA write
EXDMA read
EXDMA write
Figure 11.61 Example of Cluster Transfer Mode Transfer
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Section 11 EXDMA Controller (EXDMAC)
(2)
EDREQ Pin Falling Edge Activation Timing
Figure 11.62 shows an example of cluster transfer mode transfer activated by the EDREQ pin falling edge. EDREQ pin sampling is performed in each cycle starting at the next rise of B after the end of the DTE bit write cycle. When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared, and EDREQ pin high level sampling for edge sensing is started. If EDREQ pin high level sampling is completed by the end of the last cluster write cycle, acceptance resumes after the end of the write cycle, and EDREQ pin low level sampling is performed again. This sequence of operations is repeated until the end of the transfer.
Bus release B EDREQ Address bus
EXDMA control
Transfer source
One cluster transfer
Bus release
One cluster transfer
Transfer destination
Transfer source
Transfer destination
Consecutive read
Consecutive write
Consecutive read
Consecutive write
Channel
Request
Request clearance period
Request
Request clearance period
[1] [1] [2] [5] [3] [6] [4] [7]
Minimum 3 cycles [2]
[3]
[4]
Minimum 3 cycles [5]
[6]
[7]
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of B, and request is held. Request is cleared at end of next bus cycle, and activation is started in EXDMAC. EXDMA cycle starts; EDREQ pin high level sampling is started at rise of B. When EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle. (As in [1], EDREQ pin low level is sampled at rise of B, and request is held.)
Figure 11.62 Example of Cluster Transfer Mode Transfer Activated by EDREQ Pin Falling Edge
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Section 11 EXDMA Controller (EXDMAC)
(3)
EDREQ Pin Low Level Activation Timing
Figure 11.63 shows an example of cluster transfer mode transfer activated by the EDREQ pin low level. EDREQ pin sampling is performed in each cycle starting at the next rise of B after the end of the DTE bit write cycle. When a low level is sampled at the EDREQ pin while acceptance of a transfer request via the EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated within the EXDMAC, the request is cleared. At the end of the last cluster write cycle, acceptance resumes and EDREQ pin low level sampling is performed again. This sequence of operations is repeated until the end of the transfer. When NRD bit = 0 in EDMDR, acceptance resumes at the end of the last cluster write cycle and EDREQ pin low level sampling is performed again. This sequence of operations is repeated until the end of the transfer. When NRD bit = 1 in EDMDR, acceptance resumes after one cycle from the end of the last cluster write cycle, and EDREQ pin low level sampling is performed again. This sequence of operations is repeated until the end of the transfer.
Bus release B EDREQ Address bus EXDMA control Channel
Request Minimum 3 cycles Transfer source Transfer destination Transfer source Transfer destination
One cluster transfer
Bus release
One cluster transfer
Consecutive read
Consecutive write
Consecutive read
Consecutive write
Request clearance period
Request Minimum 3 cycles
Request clearance period
[1] [1] [2] [5] [3] [6] [4] [7]
[2]
[3]
[4]
[5]
[6]
[7]
Acceptance after transfer enabling; EDREQ pin low level is sampled at rise of B, and request is held. Request is cleared at the end of next bus cycle, and activation is started in EXDMAC. EXDMA cycle stars. Acceptance is resumed after completion of write cycle. (As in [1], EDREQ pin low level is sampled at rise of B, and request is held.)
Figure 11.63 Example of Cluster Transfer Mode Transfer Activated by EDREQ Pin Low Level
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Section 11 EXDMA Controller (EXDMAC)
11.6.5
Operation Timing in Cluster Transfer Mode
This section describes examples of operation timing in cluster transfer mode. The CPU external bus cycle is shown as an example of conflict with another bus master. (1) Auto-Request/Cluster Transfer Mode/Cycle Steal Mode
With auto-request (in cycle steal mode), when the DTE bit is set to 1 in EDMDR, a continuous EXDMA transfer cycle is started a minimum of three cycles later. If there is a transfer request for another channel of higher priority, the transfer request by the original channel is held pending, and transfer is performed on the higher-priority channel from the next transfer. Transfer on the original channel is resumed on completion of the higher-priority channel transfer. The cluster transfer mode (read address mode and write address mode) can not be used with the cluster transfer mode (dual address mode) among more than one channel at the same time. When using the cluster transfer mode (read address mode and write address mode), do not set the cluster transfer mode for another channel. Figures 11.64 to 11.66 show operation timing examples for various conditions.
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3 cycles One cluster transfer One cluster transfer 3 cycles 3 cycles Last cluster cycle Consecutive EXDMA read Consecutive EXDMA write Bus release Consecutive EXDMA read Consecutive EXDMA write Bus release Consecutive EXDMA read Consecutive EXDMA write
Section 11 EXDMA Controller (EXDMAC)
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1 0
B
Bus cycle
Bus release
CPU operation
DTE = 1 write
Internal bus space cycles
ETEND
Figure 11.64 Auto-Request/Cluster Transfer Mode/Cycle Steal Mode (No Confict/Dual Address Mode)
DTE bit
0
B
One cluster transfer One cluster transfer CPU cycle CPU cycle
Last cluster cycle
Bus cycle
CPU cycle
CPU cycle
Consecutive EXDMA read
Consecutive EXDMA write
Consecutive EXDMA read
Consecutive EXDMA write
Consecutive EXDMA read
Consecutive EXDMA write
CPU operation
External space
External space
External space
External space
DTE = 1 write
ETEND
Figure 11.65 Auto-Request/Cluster Transfer Mode/Cycle Steal Mode (CPU Cycles/Dual Address Mode)
0 1
Section 11 EXDMA Controller (EXDMAC)
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DTE bit
0
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One cluster transfer Last cluster transfer Consecutive EXDMA write Bus release Consecutive EXDMA read Consecutive EXDMA write EXDMA single transfer cycle of another channel with higher priority Consecutive EXDMA read Consecutive EXDMA write
Section 11 EXDMA Controller (EXDMAC)
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B
One cluster transfer
Bus cycle
Consecutive EXDMA read
Figure 11.66 Auto-Request/Cluster Transfer Mode/Cycle Steal Mode (Conflict with Another Channel/Dual Address Mode)
Transfer request from another channel (EDREQ)
Section 11 EXDMA Controller (EXDMAC)
(2)
External Request/Cluster Transfer Mode/Cycle Steal Mode
With external requests, a cluster-size transfer is performed continuously. The start timing of the next cluster transfer is the same as for normal transfer mode. If a transfer request is generated for another channel, an EXDMA cycle for the other channel is generated before the next cluster transfer. The cluster transfer mode (read address mode and write address mode) can not be used with the cluster transfer mode (dual address mode) among more than one channel at the same time. When using the cluster transfer mode (read address mode and write address mode), do not set the cluster transfer mode for another channel. The EDREQ pin sensing timing is different for low level sensing and falling edge sensing. The same applies to transfer request acceptance and transfer start timing. Figures 11.67 to 11.69 show operation timing examples for various conditions.
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One cluster transfer Consecutive read Consecutive write EXDMA read EXDMA read EXDMA write EXDMA write 3 cycles Bus release Consecutive read EXDMA read EXDMA read Last cluster Consecutive write EXDMA write EXDMA write
Section 11 EXDMA Controller (EXDMAC)
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1 0
B
EDREQ
EDRAK
Bus cycle
Bus release
ETEND
Figure 11.67 External Request/Cluster Transfer Mode/Cycle Steal Mode (No Conflict/Dual Address Mode/Low Level Sensing)
DTE bit
Section 11 EXDMA Controller (EXDMAC)
CPU cycle
One cluster size transfer period
EXDMA write
EXDMA write
CPU cycle
EXDMA read
EXDMA read
CPU cycle
Figure 11.68 External Request/Cluster Transfer Mode/Cycle Steal Mode (CPU Cycles/Dual Address Mode/Low Level Sensing)
CPU operation
Bus cycle
EDREQ
B
EDRAK
External space
CPU cycle
External space
External space
CPU cycle
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One cluster size transfer period CPU cycle CPU cycle Consecutive EXDMA read Consecutive EXDMA write EXDMA cycle of another channel One cluster size transfer period (Last cluster transfer) Consecutive EXDMA read Consecutive EXDMA write
Section 11 EXDMA Controller (EXDMAC)
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B
EDREQ
EDRAK
Bus cycle
ETEND
EDREQ of another channel
Figure 11.69 External Request/Cluster Transfer Mode/Cycle Steal Mode (Conflict with Another Channel/Dual Address Mode/Low Level Sensing)
EDRAK of another channel
Section 11 EXDMA Controller (EXDMAC)
11.7
Ending EXDMA Transfer
The operation for ending EXDMA transfer depends on the transfer end conditions. When EXDMA transfer ends, the DTE bit and the ACT bit in EDMDR change from 1 to 0, indicating that EXDMA transfer has ended. (1) Transfer End by EDTCR Change from 1, 2, or 4 to 0
When the value of EDTCR changes from 1, 2, or 4 to 0, EXDMA transfer ends on the corresponding channel. The DTE bit in EDMDR is cleared to 0, and the DTIF bit in EDMDR is set to 1. If the DTIE bit in EDMDR is set to 1 at this time, a transfer end interrupt request is generated by the transfer counter. EXDMA transfer does not end if the EDTCR value has been 0 since before the start of transfer. (2) Transfer End by Transfer Size Error Interrupt
When the following conditions are satisfied while the TSEIE bit in EDMDR is set to 1, a transfer size error occurs and an EXDMA transfer is terminated. At this time, the DTE bit in EDMDR is cleared to 0 and the ESIF bit in EDMDR is set to 1. * In normal transfer mode and repeat transfer mode, when the next transfer is requested while a transfer is disabled due to the EDTCR value less than the data access size. * In block transfer mode, when the next transfer is requested while a transfer is disabled due to the EDTCR value less than the block size. * In cluster transfer mode, when the next transfer is requested while a transfer is disabled due to the EDTCR value less than the cluster size. When the TSEIE bit in EDMDR is cleared to 0, data is transferred until the EDTCR value reaches 0. A transfer size error is not generated. Operation in each transfer mode is described below. * In normal transfer mode and repeat mode, when the EDTCR value is less than the data access size, data is transferred in bytes. * In block transfer mode, when the EDTCR value is less than the block size, the specified size of data in EDTCR is transferred instead of transferring the block size of data. When the EDTCR value is less than the data access size, data is transferred in bytes. * In cluster transfer mode, when the EDTCR value is less than the cluster size, the specified size of data in EDTCR is transferred instead of transferring the cluster size of data. When the EDTCR value is less than the data access size, data is transferred in bytes.
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Section 11 EXDMA Controller (EXDMAC)
(3)
Transfer End by Repeat Size End Interrupt
In repeat transfer mode, when the RPTIE bit in EDACR is set to 1 and the next transfer request is generated on completion of a repeat-size transfer, a repeat size end interrupt request is generated. The interrupt request terminates EXDMA transfer, the DTE bit in EDMDR is cleared to 0, and the ESIF bit in EDMDR is set to 1 at the same time. If the DTE bit is set to 1 in this state, transfer resumes. In block transfer or cluster transfer mode, a repeat size end interrupt request can be generated. In block transfer mode, if the next transfer request is generated at the end of a block-size transfer, a repeat size end interrupt request is generated. In cluster transfer mode, if the next transfer request is generated at the end of a cluster-size transfer, a repeat size end interrupt request is generated. (4) Transfer End by Extended Repeat Area Overflow Interrupt
If an address overflows the extended repeat area when an extended repeat area specification has been made and the SARIE or DARIE bit in EDACR is set to 1, an extended repeat area overflow interrupt is requested. The interrupt request terminates EXDMA transfer, the DTE bit in EDMDR is cleared to 0, and the ESIF bit in EDMDR is set to 1 at the same time. In dual address mode, if an extended repeat area overflow interrupt is requested during a read cycle, the following write cycle processing is still executed. In block transfer mode, if an extended repeat area overflow interrupt is requested during transfer of a block, transfer continues to the end of the block. Transfer end by means of an extended repeat area overflow interrupt occurs between block-size transfers. In cluster transfer mode, if an extended repeat area overflow interrupt is requested during transfer of a cluster, transfer continues to the end of the cluster. Transfer end by means of an extended repeat area overflow interrupt occurs between cluster-size transfers. (5) Transfer End by 0-Write to DTE Bit in EDMDR
When 0 is written to the DTE bit in EDMDR by the CPU, etc., transfer ends after completion of the EXDMA cycle in which transfer is in progress or a transfer request was accepted. In block transfer mode, EXDMA transfer ends after completion of one-block-size transfer in progress. In cluster transfer mode, EXDMA transfer ends after completion of one-cluster-size transfer in progress.
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Section 11 EXDMA Controller (EXDMAC)
(6)
Transfer End by NMI Interrupt
If an NMI interrupt occurs, the EXDMAC clears the DTE bit to 0 in all channels and sets the ERRF bit in EDMDR_0 to 1. EXDMA transfer is aborted when an NMI interrupt is generated during EXDMA transfer. To perform EXDMA transfer after an NMI interrupt occurs, clear the ERRF bit to 0 and then set the DTE bit to 1 in all channels. The following explains the transfer end timing in each mode after an NMI interrupt is detected. (a) Normal transfer mode and repeat transfer mode
In dual address mode, EXDMA transfer ends at the end of the EXDMA transfer write cycle in units of transfers. In single address mode, EXDMA transfer ends at the end of the EXDMA transfer bus cycle in units of transfers. (b) Block transfer mode
A block size EXDMA transfer is aborted. A block size transfer is not correctly executed, thus matching between the actual transfer and the transfer request is not guaranteed. In dual address mode, a write cycle corresponding to a read cycle is executed as well as in the normal transfer mode. (c) Cluster transfer mode
A cluster size EXDMA transfer is aborted. If transfer is aborted in a read cycle, the read data is not guaranteed. If transfer is aborted in a write cycle, the data not transferred is not guaranteed. Matching between the transfer counter and the address register is not guaranteed since the transfer processing cannot be controlled. (7) Transfer End by Address Error
If an address error occurs, the EXDMAC clears the DTE bit to 0 in all channels, and set the ERRF bit in EDMDR_0 to 1. An address error during EXDMA transfer forcibly terminates the transfer. To perform EXDMA transfer after an address error occurs, clear the ERRF bit to 0 and then set the DTE bit to 1 in each channel. The transfer end timing after address error detection is the same as for the one when an NMI interrupt occurs.
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Section 11 EXDMA Controller (EXDMAC)
(8)
Transfer End by Hardware Standby Mode and Reset Input
The EXDMAC is initialized in hardware standby mode and by a reset. EXDMA transfer is not guaranteed in these cases.
11.8
11.8.1
Relationship among EXDMAC and Other Bus Masters
CPU Priority Control Function Over EXDMAC
The EXDMAC priority level control function can be used for the CPU by setting the CPU priority control register (CPUPCR). For details, see section 7.7, CPU Priority Control Function Over DTC, DMAC, and EXDMAC. The EXDMAC priority level can be set independently for each channel by the EDMAP2 to EDMAP0 bits in EDMDR. The CPU priority level, which corresponds to the priority level of exception handling, can be set by updating the values of the CPUP2 to CPUP0 bits in CPUPCR with the interrupt mask bit values. When the CPUPCE bit in CPUPCR is set to 1 to enable the CPU priority level control and the EXDMAC priority level is lower than the CPU priority level, the transfer request of the corresponding channel is masked and the channel activation is disabled. When the priority level of another channel is the same or higher than the CPU priority level, the transfer request for another channel is accepted and transfer is enabled regardless of the priority levels of channels. The CPU priority level control function holds pending the transfer source, which masked the transfer request. When the CPU priority level becomes lower than the channel priority level by updating one of them, the transfer request is accepted and transfer starts. The transfer request held pending is cleared by writing 0 to the DTE bit. When the CPUPCE bit is cleared to 0, the lowest CPU priority level is assumed.
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Section 11 EXDMA Controller (EXDMAC)
11.8.2
Bus Arbitration with Another Bus Master
A cycle of another bus master may (or not) be inserted among consecutive EXDMA transfer bus cycles. The EXDMAC bus mastership can be set so that it is released and transferred to another bus master. Some of the consecutive EXDMA transfer bus cycles may be indivisible due to the transfer mode specification, may be consecutive bus cycles for high-speed access due to the transfer mode specification, or may be consecutive bus cycles because another bus master does not request the bus mastership. These consecutive EXDMA read and write cycles are indivisible: refresh cycle, external bus release cycle, or external space access cycle by internal bus master (CPU, DTC, DMAC) does not occur between a read cycle and a write cycle. In cluster transfer mode, the transfer cycle in one cluster is indivisible. In block transfer mode and auto-request burst mode, the EXDMA transfer bus cycles continues. In this period, the bus priority level of the internal bus master is lower than the EXDMAC so that the external space access is held pending (when EBCCS = 0 in the bus control register 2 (BCR2)). When switching to another channel, or in the auto-request cycle steal mode, the EXDMA transfer cycles and internal bus master cycles are alternatively executed. When the internal bus master is not issuing an external space access cycle, the EXDMA transfer bus cycles are continuously executed in the allowable range. When the EBCCS bit in BCR2 is set to 1 to enable the arbitration function between the EXDMAC and the internal bus master, the bus mastership is released, except for indivisible bus cycles, and transferred between the EXDMAC and the internal bus master alternatively. For details, see section 9, Bus Controller (BSC).
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Section 11 EXDMA Controller (EXDMAC)
11.9
Interrupt Sources
EXDMAC interrupt sources are a transfer end by the transfer counter, and an escape end interrupt which is caused by the transfer counter not becoming 0. Table 11.7 shows the interrupt sources and their priority order. Table 11.7 Interrupt Sources and Priority Order
Interrupt EXDMTEND0 EXDMTEND1 EXDMTEND2 EXDMTEND3 EXDMEEND0 Interrupt Source Transfer end indicated by channel 0 transfer counter Transfer end indicated by channel 1 transfer counter Transfer end indicated by channel 2 transfer counter Transfer end indicated by channel 3 transfer counter Channel 0 transfer size error Channel 0 repeat size end Channel 0 source address extended repeat area overflow Channel 0 destination address extended repeat area overflow EXDMEEND1 Channel 1 transfer size error Channel 1 repeat size end Channel 1 source address extended repeat area overflow Channel 1 destination address extended repeat area overflow EXDMEEND2 Channel 2 transfer size error Channel 2 repeat size end Channel 2 source address extended repeat area overflow Channel 2 destination address extended repeat area overflow EXDMEEND3 Channel 3 transfer size error Channel 3 repeat size end Channel 3 source address extended repeat area overflow Channel 3 destination address extended repeat area overflow Low Interrupt Priority High
Interrupt source can be enabled or disabled by setting the DTIE and ESIE bits in EDMDR for the relevant channels. The DTIE bit can be combined with the DTIF bit in EDMDR to generate an EXDMTEND interrupt. The ESIE bit can be combined with the ESIF bit in EDMDR to generate an EXDMEEND interrupt. Interrupt sources in EXDMEEND are not identified as common interrupts. The interrupt priority order among channels is determined by the interrupt controller as shown in table 11.7. For detains see section 7, Interrupt Controller.
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Section 11 EXDMA Controller (EXDMAC)
Interrupt source settings are made individually with the interrupt enable bits in the registers for the relevant channels. The transfer counter's transfer end interrupt is enabled or disabled by means of the DTIE bit in EDMDR, the transfer size error interrupt by means of the TSEIE bit in EDMDR, the repeat size end interrupt by means of the RPTIE bit in EDACR, the source address extended repeat area overflow interrupt by means of the SARIE bit in EDACR, and the destination address extended repeat area overflow interrupt by means of the DARIE bit in EDACR. The transfer end interrupt by the transfer counter occurs when the DTIE bit in EDMDR is set to 1, the EDTCR becomes 0 by transfer, and then the DTIF bit in EDMDR is set to 1. Interrupts other than the transfer end interrupt by the transfer counter occurs when the corresponding interrupt enable bit is set to 1, the condition for that interrupt is satisfied, and then the ESIF bit in EDMDR is set to 1. The transfer size error interrupt occurs when the EDTCR value is smaller than the data access size and a data-access-size transfer for one request cannot be performed for a transfer request. In block transfer mode, the block size is compared to the EDTCR value to determine a transfer size error. In cluster transfer mode, the cluster size is compared to the EDTCR value to determine a transfer size error. The repeat size end interrupt occurs when the next transfer request is generated after the end of a repeat size transfer in repeat transfer mode. When the repeat area is not set in the address register, transfer can be aborted periodically based on the set repeat size value. If the transfer end interrupt by the transfer counter occurs at the same time, the ESIF bit is set to 1. The source/destination address extended repeat area overflow interrupt occurs when the addresses overflow the specified extended repeat area. If the transfer end interrupt by the transfer counter occurs at the same time, the ESIF bit is set to 1. Figure 11.70 shows the block diagram of various interrupts and their interrupt flags. The transfer end interrupt can be cleared either by clearing the DTIF or ESIF bit to 0 in EDMDR within the interrupt handling routine, or by re-setting the address registers and then setting the DTE bit to 1 in EDMDR to perform transfer continuation processing. An example of the procedure for clearing the transfer end interrupt and restarting transfer is shown in figure 11.71.
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Section 11 EXDMA Controller (EXDMAC)
TSEIE bit Activation source occurred in the transfer size error state RPTIE bit Activation source occurred after BKSZ changed from 1 to 0 SARIE bit Source address extended repeat area overflow occurred DARIE bit Destination address extended repeat area overflow occurred
DTIE bit DTIF bit Transfer end interrupt
Condition to set DTIF bit to 1: DTCR is set to 0 and transfer ends.
ESIE bit ESIF bit Transfer escape end interrupt
Condition to set ESIF bit to 1
Figure 11.70 Interrupts and Interrupt Sources
Transfer end interrupt of exception handling routine
Transfer continuation processing Change register settings Write 1 to DTE bit End of interrupt handling routine (RTE instruction execution) [1]
Transfer restart after end of interrupt handling routine Clear DTIF or ESIF bit to 0 [2] End of interrupt handling routine [3] [5] [6] [7] [4]
Change register settings Write 1 to DTE bit
End of transfer restart processing End of transfer restart processing [1] Write set values to the registers (transfer counter, address registers, etc.) [2] Write 1 to the DTE bit in EDMDR to restart EXDMA operation. When 1 is written to the DTE bit, the DTIF or ESIF bit in EDMDR is automatically cleared to 0 and the interrupt source is cleared. [3] The interrupt handling routine is ended with an RTE instruction, etc. [4] Write 0 to the DTIF or ESIF bit in EDMDR by first reading 1 from it. [5] After the interrupt handling routine is ended with an RTE instruction, etc., interrupt masking is cleared. [6] Write set values to the registers (transfer counter, address registers, etc.). [7] Write 1 to the DTE bit in EDMDR to restart EXDMA operation.
Figure 11.71 Procedure for Clearing Transfer End Interrupt and Restarting Transfer
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Section 11 EXDMA Controller (EXDMAC)
11.10
(1)
Usage Notes
EXDMAC Register Access during Operation
Except for clearing the DTE bit to 0 in EDMDR, settings should not be changed for a channel in operation (including the transfer standby state). Transfer must be disabled before changing a setting for an operational channel. (2) Module Stop State
The EXDMAC operation can be enabled or disabled by the module stop control register. The initial value is "enabled". When the MSTPA14 bit is set to 1 in MSTPCRA, the EXDMAC clock stops and the EXDMAC enters the module stop state. However, 1 cannot be written to the MSTPA14 bit when any of the EXDMAC's channels is enabled for transfer, or when an interrupt is being requested. Before setting the MSTPA14 bit, first clear the DTE bit in EDMDR to 0, then clear the DTIF or DTIE bit in EDMDR to 0. When the EXDMAC clock stops, EXDMAC registers can no longer be accessed. The following EXDMAC register settings remain valid in the module stop state, and so should be disabled, if necessary, before making the module stop transition. * ETENDE = 1 in EDMDR (ETEND pin enable) * EDRAKE = 1 in EDMDR (EDRAK pin enable) * EDACKE = 1 in EDMDR (EDACK pin enable) (3) EDREQ Pin Falling Edge Activation
Falling edge sensing on the EDREQ pin is performed in synchronization with EXDMAC internal operations, as indicated below. 1. Activation request standby state: Waits for low level sensing on EDREQ pin, then goes to [2]. 2. Transfer standby state: Waits for EXDMAC data transfer to become possible, then goes to [3]. 3. Activation request disabled state: Waits for high level sensing on EDREQ pin, then goes to [1]. After EXDMAC transfer is enabled, the EXDMAC goes to state [1], so low level sensing is used for the initial activation after transfer is enabled.
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Section 11 EXDMA Controller (EXDMAC)
(4)
Activation Source Acceptance
At the start of activation source acceptance, low level sensing is used for both falling edge sensing and low level sensing on the c Therefore, a request is accepted in the case of a low level at the EDREQ pin that occurs before execution of the EDMDR write for setting the transfer-enabled state. At EXDMAC activation, low level on the EDREQ pin must not remain at the end of the previous transfer. (5) Conflict in Cluster Transfer
In cluster transfer mode, the same cluster buffer is used for all channels. When more than one cluster transfer conflicts, the cluster buffer register holds the value of the last cluster transfer. When the transfer between the transfer source/destination and the cluster buffer conflicts with another cluster transfer, the transferred data in the cluster buffer may be overwritten by another channel cluster transfer. Therefore, in the cluster transfer mode (single address mode), do not set the cluster transfer mode for any other channels. (6) Cluster Transfer Mode and Endian
In cluster transfer mode, only a transfer to the areas in the big endian format is supported. When cluster transfer mode is specified, do not specify the areas in the little endian format for EDSAR and EDDAR. For details on the endian, see section 9, Bus Controller (BSC).
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Section 12 Data Transfer Controller (DTC)
Section 12 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated to transfer data by an interrupt request.
12.1
Features
* Transfer possible over any number of channels: Multiple data transfer enabled for one activation source (chain transfer) Chain transfer specifiable after data transfer (when the counter is 0) * Three transfer modes Normal/repeat/block transfer modes selectable Transfer source and destination addresses can be selected from increment/decrement/fixed * Short address mode or full address mode selectable Short address mode Transfer information is located on a 3-longword boundary The transfer source and destination addresses can be specified by 24 bits to select a 16Mbyte address space directly Full address mode Transfer information is located on a 4-longword boundary The transfer source and destination addresses can be specified by 32 bits to select a 4Gbyte address space directly * Size of data for data transfer can be specified as byte, word, or longword The bus cycle is divided if an odd address is specified for a word or longword transfer. The bus cycle is divided if address 4n + 2 is specified for a longword transfer. * A CPU interrupt can be requested for the interrupt that activated the DTC A CPU interrupt can be requested after one data transfer completion A CPU interrupt can be requested after the specified data transfer completion * Read skip of the transfer information specifiable * Writeback skip executed for the fixed transfer source and destination addresses * Module stop state specifiable
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Section 12 Data Transfer Controller (DTC)
Figure 12.1 shows a block diagram of the DTC. The DTC transfer information can be allocated to the data area*. When the transfer information is allocated to the on-chip RAM, a 32-bit bus connects the DTC to the on-chip RAM, enabling 32-bit/1-state reading and writing of the DTC transfer information. Note: * When the transfer information is stored in the on-chip RAM, the RAME bit in SYSCR must be set to 1.
Interrupt controller DTCERA to DTCERF DTCCR On-chip ROM
DTC MRA
Internal bus (32 bits)
On-chip RAM
Register control
MRB
Peripheral bus
DAR CRA Activation control CRB
DTC activation request vector number CPU interrupt request Interrupt source clear request
8
Interrupt control
External device (memory mapped)
External bus
External memory
Bus interface
Bus controller DTCVBR
REQ ACK
[Legend] MRA, MRB: SAR: DAR: CRA, CRB: DTCERA to DTCERF: DTCCR: DTCVBR: DTC mode registers A, B DTC source address register DTC destination address register DTC transfer count registers A, B DTC enable registers A to F DTC control register DTC vector base register
Figure 12.1 Block Diagram of DTC
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DTC internal bus
On-chip peripheral module
SAR
Section 12 Data Transfer Controller (DTC)
12.2
Register Descriptions
DTC has the following registers. * * * * * * DTC mode register A (MRA) DTC mode register B (MRB) DTC source address register (SAR) DTC destination address register (DAR) DTC transfer count register A (CRA) DTC transfer count register B (CRB)
These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the CPU. The contents of these registers are stored in the data area as transfer information. When a DTC activation request occurs, the DTC reads a start address of transfer information that is stored in the data area according to the vector address, reads the transfer information, and transfers data. After the data transfer, it writes a set of updated transfer information back to the data area. * DTC enable registers A to F (DTCERA to DTCERF) * DTC control register (DTCCR) * DTC vector base register (DTCVBR)
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Section 12 Data Transfer Controller (DTC)
12.2.1
DTC Mode Register A (MRA)
MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU.
Bit Bit Name Initial Value R/W 7 MD1 Undefined 6 MD0 Undefined 5 Sz1 Undefined 4 Sz0 Undefined 3 SM1 Undefined 2 SM0 Undefined 1 Undefined 0 Undefined
Bit 7 6
Bit Name MD1 MD0
Initial Value
R/W
Description DTC Mode 1 and 0 Specify DTC transfer mode. 00: Normal mode 01: Repeat mode 10: Block transfer mode 11: Setting prohibited
Undefined Undefined
5 4
Sz1 Sz0
Undefined Undefined
DTC Data Transfer Size 1 and 0 Specify the size of data to be transferred. 00: Byte-size transfer 01: Word-size transfer 10: Longword-size transfer 11: Setting prohibited
3 2
SM1 SM0
Undefined Undefined
Source Address Mode 1 and 0 Specify an SAR operation after a data transfer. 0x: SAR is fixed (SAR writeback is skipped) 10: SAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: SAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
1, 0
Undefined
Reserved The write value should always be 0.
[Legend] x: Don't care
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Section 12 Data Transfer Controller (DTC)
12.2.2
DTC Mode Register B (MRB)
MRB selects DTC operating mode. MRB cannot be accessed directly by the CPU.
Bit Bit Name Initial Value R/W 7 CHNE Undefined 6 CHNS Undefined 5 DISEL Undefined 4 DTS Undefined 3 DM1 Undefined 2 DM0 Undefined 1 Undefined 0 Undefined
Bit 7
Bit Name CHNE
Initial Value
R/W
Description DTC Chain Transfer Enable Specifies the chain transfer. For details, see section 12.5.7, Chain Transfer. The chain transfer condition is selected by the CHNS bit. 0: Disables the chain transfer 1: Enables the chain transfer
Undefined
6
CHNS
Undefined
DTC Chain Transfer Select Specifies the chain transfer condition. If the following transfer is a chain transfer, the completion check of the specified transfer count is not performed and activation source flag or DTCER is not cleared. 0: Chain transfer every time 1: Chain transfer only when transfer counter = 0
5
DISEL
Undefined
DTC Interrupt Select When this bit is set to 1, a CPU interrupt request is generated every time after a data transfer ends. When this bit is set to 0, a CPU interrupt request is only generated when the specified number of data transfer ends.
4
DTS
Undefined
DTC Transfer Mode Select Specifies either the source or destination as repeat or block area during repeat or block transfer mode. 0: Specifies the destination as repeat or block area 1: Specifies the source as repeat or block area
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Section 12 Data Transfer Controller (DTC)
Bit 3 2
Bit Name DM1 DM0
Initial Value
R/W
Description Destination Address Mode 1 and 0 Specify a DAR operation after a data transfer. 0X: DAR is fixed (DAR writeback is skipped) 10: DAR is incremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10) 11: SAR is decremented after a transfer (by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
Undefined Undefined
1, 0
Undefined
Reserved The write value should always be 0.
[Legend] x: Don't care
12.2.3
DTC Source Address Register (SAR)
SAR is a 32-bit register that designates the source address of data to be transferred by the DTC. In full address mode, 32 bits of SAR are valid. In short address mode, the lower 24 bits of SAR is valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of bit 23. If a word or longword access is performed while an odd address is specified in SAR or if a longword access is performed while address 4n + 2 is specified in SAR, the bus cycle is divided into multiple cycles to transfer data. For details, see section 12.5.1, Bus Cycle Division. SAR cannot be accessed directly from the CPU.
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Section 12 Data Transfer Controller (DTC)
12.2.4
DTC Destination Address Register (DAR)
DAR is a 32-bit register that designates the destination address of data to be transferred by the DTC. In full address mode, 32 bits of DAR are valid. In short address mode, the lower 24 bits of DAR is valid and bits 31 to 24 are ignored. At this time, the upper eight bits are filled with the value of bit 23. If a word or longword access is performed while an odd address is specified in DAR or if a longword access is performed while address 4n + 2 is specified in DAR, the bus cycle is divided into multiple cycles to transfer data. For details, see section 12.5.1, Bus Cycle Division. DAR cannot be accessed directly from the CPU. 12.2.5 DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal transfer mode, CRA functions as a 16-bit transfer counter (1 to 65,536). It is decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRA = H'0001, 65,535 when CRA = H'FFFF, and 65,536 when CRA = H'0000. In repeat transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The transfer count is 1 when CRAH = CRAL = H'01, 255 when CRAH = CRAL = H'FF, and 256 when CRAH = CRAL = H'00. In block transfer mode, CRA is divided into two parts: the upper eight bits (CRAH) and the lower eight bits (CRAL). CRAH holds the block size while CRAL functions as an 8-bit block-size counter (1 to 256 for byte, word, or longword). CRAL is decremented by 1 every time a byte (word or longword) data is transferred, and the contents of CRAH are sent to CRAL when the count reaches H'00. The block size is 1 byte (word or longword) when CRAH = CRAL =H'01, 255 bytes (words or longwords) when CRAH = CRAL = H'FF, and 256 bytes (words or longwords) when CRAH = CRAL =H'00. CRA cannot be accessed directly from the CPU.
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Section 12 Data Transfer Controller (DTC)
12.2.6
DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1 every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The transfer count is 1 when CRB = H'0001, 65,535 when CRB = H'FFFF, and 65,536 when CRB = H'0000. CRB is not available in normal and repeat modes and cannot be accessed directly by the CPU. 12.2.7 DTC enable registers A to F (DTCERA to DTCERF)
DTCER, which is comprised of eight registers, DTCERA to DTCERF, is a register that specifies DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is shown in table 12.1. Use bit manipulation instructions such as BSET and BCLR to read or write a DTCE bit. If all interrupts are masked, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 DTCE15 0 R/W 7 DTCE7 0 R/W 14 DTCE14 0 R/W 6 DTCE6 0 R/W 13 DTCE13 0 R/W 5 DTCE5 0 R/W 12 DTCE12 0 R/W 4 DTCE4 0 R/W 11 DTCE11 0 R/W 3 DTCE3 0 R/W 10 DTCE10 0 R/W 2 DTCE2 0 R/W 9 DTCE9 0 R/W 1 DTCE1 0 R/W 8 DTCE8 0 R/W 0 DTCE0 0 R/W
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Section 12 Data Transfer Controller (DTC)
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Bit Name DTCE15 DTCE14 DTCE13 DTCE12 DTCE11 DTCE10 DTCE9 DTCE8 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0
Initial Value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description DTC Activation Enable 15 to 0 Setting this bit to 1 specifies a relevant interrupt source to a DTC activation source. [Clearing conditions] * * * When writing 0 to the bit to be cleared after reading 1 When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended
These bits are not cleared when the DISEL bit is 0 and the specified number of transfers have not ended
12.2.8
DTC Control Register (DTCCR)
DTCCR specifies transfer information read skip.
Bit Bit Name Initial Value R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 RRS 0 R/W 3 RCHNE 0 R/W 2 0 R 1 0 R 0 ERR 0 R/(W)*
Note: * Only 0 can be written to clear the flag.
Bit 7 to 5
Bit Name
Initial Value All 0
R/W R/W
Description Reserved These bits are always read as 0. The write value should always be 0.
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Section 12 Data Transfer Controller (DTC)
Bit 4
Bit Name RRS
Initial Value 0
R/W R/W
Description DTC Transfer Information Read Skip Enable Controls the vector address read and transfer information read. A DTC vector number is always compared with the vector number for the previous activation. If the vector numbers match and this bit is set to 1, the DTC data transfer is started without reading a vector address and transfer information. If the previous DTC activation is a chain transfer, the vector address read and transfer information read are always performed. 0: Transfer read skip is not performed. 1: Transfer read skip is performed when the vector numbers match.
3
RCHNE
0
R/W
Chain Transfer Enable After DTC Repeat Transfer Enables/disables the chain transfer while transfer counter (CRAL) is 0 in repeat transfer mode. In repeat transfer mode, the CRAH value is written to CRAL when CRAL is 0. Accordingly, chain transfer may not occur when CRAL is 0. If this bit is set to 1, the chain transfer is enabled when CRAH is written to CRAL. 0: Disables the chain transfer after repeat transfer 1: Enables the chain transfer after repeat transfer
2, 1 0
ERR
All 0 0
R
Reserved These are read-only bits and cannot be modified.
R/(W)* Transfer Stop Flag Indicates that an address error or an NMI interrupt occurs. If an address error or an NMI interrupt occurs, the DTC stops. 0: No interrupt occurs 1: An interrupt occurs [Clearing condition] * When writing 0 after reading 1
Note:
*
Only 0 can be written to clear this flag.
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Section 12 Data Transfer Controller (DTC)
12.2.9
DTC Vector Base Register (DTCVBR)
DTCVBR is a 32-bit register that specifies the base address for vector table address calculation. Bits 31 to 28 and bits 11 to 0 are fixed 0 and cannot be written to. The initial value of DTCVBR is H'00000000.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 0 R 14 0 R 13 0 R 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
12.3
Activation Sources
The DTC is activated by an interrupt request. The interrupt source is selected by DTCER. A DTC activation source can be selected by setting the corresponding bit in DTCER; the CPU interrupt source can be selected by clearing the corresponding bit in DTCER. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source interrupt flag or corresponding DTCER bit is cleared.
12.4
Location of Transfer Information and DTC Vector Table
Locate the transfer information in the data area. The start address of transfer information should be located at the address that is a multiple of four (4n). Otherwise, the lower two bits are ignored during access ([1:0] = B'00.) Transfer information can be located in either short address mode (three longwords) or full address mode (four longwords). The DTCMD bit in SYSCR specifies either short address mode (DTCMD = 1) or full address mode (DTCMD = 0). For details, see section 3.2.2, System Control Register (SYSCR). Transfer information located in the data area is shown in figure 12.2 The DTC reads the start address of transfer information from the vector table according to the activation source, and then reads the transfer information from the start address. Figure 12.3 shows correspondences between the DTC vector address and transfer information.
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Section 12 Data Transfer Controller (DTC)
Transfer information in short address mode Lower addresses Start address 0 MRA MRB Chain transfer CRA MRA MRB CRA 4 bytes 1 2 SAR DAR CRB SAR DAR CRB Transfer information for one transfer (3 longwords) Transfer information for the 2nd transfer in chain transfer (3 longwords) Chain transfer 3 Start address
Transfer information in full address mode Lower addresses 0 1 2 3 Transfer information for one transfer (4 longwords)
Reserved (0 write)
MRA MRB
SAR DAR CRA MRA MRB CRB
Reserved (0 write)
SAR DAR CRA 4 bytes CRB
Transfer information for the 2nd transfer in chain transfer (4 longwords)
Figure 12.2 Transfer Information on Data Area
Upper: DTCVBR Lower: H'400 + vector number x 4 DTC vector address +4
Vector table Transfer information (1)
Transfer information (1) start address Transfer information (2) start address : : : Transfer information (n) start address 4 bytes Transfer information (n) : : :
Transfer information (2)
+4n
Figure 12.3 Correspondence between DTC Vector Address and Transfer Information
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Section 12 Data Transfer Controller (DTC)
Table 12.1 shows correspondence between the DTC activation source and vector address. Table 12.1 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Origin of Activation Activation Source Source External pin IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 A/D_0 ADI0 (A/D_0 conversion end) TGI0A TGI0B TGI0C TGI0D TPU_1 TGI1A TGI1B TPU_2 TGI2A TGI2B Vector Number 64 65 66 67 68 69 70 71 72 73 74 75 86 DTC Vector Address Offset H'500 H'504 H'508 H'50C H'510 H'514 H'518 H'51C H'520 H'524 H'528 H'52C H'558 DTCE* DTCEA15 DTCEA14 DTCEA13 DTCEA12 DTCEA11 DTCEA10 DTCEA9 DTCEA8 DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEB15 Priority High
TPU_0
88 89 90 91 93 94 97 98
H'560 H'564 H'568 H'56C H'574 H'578 H'584 H'588
DTCEB13 DTCEB12 DTCEB11 DTCEB10 DTCEB9 DTCEB8 DTCEB7 DTCEB6 Low
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Section 12 Data Transfer Controller (DTC)
Origin of Activation Source TPU_3
Activation Source TGI3A TGI3B TGI3C TGI3D
Vector Number 101 102 103 104 106 107 110 111 116 117 119 120 122 123 125 126 128 129 130 131
DTC Vector Address Offset H'594 H'598 H'59C H'5A0 H'5A8 H'5AC H'5B8 H'5BC H'5D0 H'5D4 H'5DC H'5E0 H'5E8 H'5EC H'5F4 H'5F8 H'600 H'604 H'608 H'60C H'610 H'614 H'618 H'61C H'620 H'624 H'628 H'62C H'630 H'634 H'638 H'63C
DTCE* DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC15 DTCEC14 DTCEC13 DTCEC12 DTCEC11 DTCEC10 DTCEC9 DTCEC8 DTCEC7 DTCEC6 DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCEC15 DTCEC14 DTCED13 DTCED12 DTCED11 DTCED10 DTCECD9 DTCECD8 DTCED7 DTCED6
Priority High
TPU_4
TGI4A TGI4B
TPU_5
TGI5A TGI5B
TMR_0
CMI0A CMI0B
TMR_1
CMI1A CMI1B
TMR_2
CMI2A CMI2B
TMR_3
CMI3A CMI3B
DMAC
DMTEND0 DMTEND1 DMTEND2 DMTEND3
EXDMAC
EXDMTEND0 132 EXDMTEND1 133 EXDMTEND2 134 EXDMTEND3 135
DMAC
DMEEND0 DMEEND1 DMEEND2 DMEEND3
136 137 138 139
EXDMAC
EXDMEEND0 140 EXDMEEND1 141 EXDMEEND2 142 EXDMEEND3 143
Low
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Section 12 Data Transfer Controller (DTC)
Origin of Activation Source SCI_0
Activation Source RXI0 TXI0
Vector Number 145 146 149 150 153 154 161 162 164 165 166 167 169 170 173 174 177 178 179 180 182 183 186 188 189
DTC Vector Address Offset H'644 H'648 H'654 H'658 H'664 H'668 H'684 H'688 H'690 H'694 H'698 H'69C H'6A4 H'6A8 H'6B4 H'6B8 H'6C4 H'6C8 H'6CC H'6D0 H'6D8 H'6DC H'6E8 H'6F0 H'6F4
DTCE* DTCED5 DTCED4 DTCED3 DTCED2 DTCED1 DTCED0 DTCEE13 DTCEE12 DTCEE11 DTCEE10 DTCEE9 DTCEE8 DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0 DTCEF15 DTCEF14 DTCEF11 DTCEF10 DTCEF9
Priority High
SCI_1
RXI1 TXI1
SCI_2
RXI2 TXI2
SCI_4
RXI4 TXI4
TPU_6
TGI6A TGI6B TGI6C TGI6D
TPU_7
TGI7A TGI7B
TPU_8
TGI8A TGI8B
TPU_9
TGI9A TGI9B TGI9C TGI9D
TPU_10
TGI10A TGI10B TGI10V
TPU_11 Note: *
TGI11A TGI11B
Low
The DTCE bits with no corresponding interrupt are reserved, and the write value should always be 0. To leave software standby mode or all-module-clock-stop mode with an interrupt, write 0 to the corresponding DTCE bit.
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Section 12 Data Transfer Controller (DTC)
12.5
Operation
The DTC stores transfer information in the data area. When activated, the DTC reads transfer information that is stored in the data area and transfers data on the basis of that transfer information. After the data transfer, it writes updated transfer information back to the data area. Since transfer information is in the data area, it is possible to transfer data over any required number of channels. There are three transfer modes: normal, repeat, and block. The DTC specifies the source address and destination address in SAR and DAR, respectively. After a transfer, SAR and DAR are incremented, decremented, or fixed independently. Table 12.2 shows the DTC transfer modes. Table 12.2 DTC Transfer Modes
Transfer Mode Normal Repeat*1 Block*2 Size of Data Transferred at One Transfer Request 1 byte/word/longword 1 byte/word/longword Memory Address Increment or Decrement Transfer Count
Incremented/decremented by 1, 2, or 4, 1 to 65536 or fixed Incremented/decremented by 1, 2, or 4, 1 to 256*3 or fixed
Block size specified by CRAH (1 Incremented/decremented by 1, 2, or 4, 1 to 65536 to 256 bytes/words/longwords) or fixed
Notes: 1. Either source or destination is specified to repeat area. 2. Either source or destination is specified to block area. 3. After transfer of the specified transfer count, initial state is recovered to continue the operation.
Setting the CHNE bit in MRB to 1 makes it possible to perform a number of transfers with a single activation (chain transfer). Setting the CHNS bit in MRB to 1 can also be made to have chain transfer performed only when the transfer counter value is 0. Figure 12.4 shows a flowchart of DTC operation, and table 12.3 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted).
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Section 12 Data Transfer Controller (DTC)
Start Match & RRS = 1
Vector number comparison Not match | RRS = 0 Read DTC vector Next transfer Read transfer information
Transfer data
Update transfer information
Update the start address of transfer information
Write transfer information
CHNE = 1 Yes No
Transfer counter = 0 or DISEL = 1 Yes No
CHNS = 0 Yes No Transfer counter = 0 Yes No DISEL = 1 No
Yes
Clear activation source flag
Clear DTCER/request an interrupt to the CPU
End
Figure 12.4 Flowchart of DTC Operation
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Section 12 Data Transfer Controller (DTC)
Table 12.3 Chain Transfer Conditions
1st Transfer Transfer CHNE CHNS DISEL Counter*1 0 0 0 1 0 0 0 1 Not 0 0*
2
2nd Transfer Transfer CHNE CHNS DISEL Counter*1 DTC Transfer 0 0 0 0 0 1 0 0 1 Not 0 0*2 Not 0 0*
2
Ends at 1st transfer Ends at 1st transfer Interrupt request to CPU Ends at 2nd transfer Ends at 2nd transfer Interrupt request to CPU Ends at 1st transfer Ends at 2nd transfer Ends at 2nd transfer Interrupt request to CPU Ends at 1st transfer Interrupt request to CPU
1 1
1 1
0
Not 0 0*2
0 0 0
1
1
1
Not 0
Notes: 1. CRA in normal mode transfer, CRAL in repeat transfer mode, or CRB in block transfer mode 2. When the contents of the CRAH is written to the CRAL in repeat transfer mode
12.5.1
Bus Cycle Division
When the transfer data size is word and the SAR and DAR values are not a multiple of 2, the bus cycle is divided and the transfer data is read from or written to in bytes. Table 12.4 shows the relationship among, SAR, DAR, transfer data size, bus cycle divisions, and access data size. Figure 12.5 shows the bus cycle division example. Table 12.4 Number of Bus Cycle Divisions and Access Size
Specified Data Size SAR and DAR Values Byte (B) Address 4n Address 2n + 1 Address 4n + 2 1 (B) 1 (B) 1 (B) Word (W) 1 (W) 2 (B-B) 1 (W) Longword (LW) 1 (LW) 3 (B-W-B) 2 (W-W)
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Section 12 Data Transfer Controller (DTC)
[Example 1: When an odd address and even address are specified in SAR and DAR, respectively, and when the data size of transfer is specified as word]
Clock
DTC activation request DTC request
R W B W
Address
B
Vector read
Transfer information Data transfer Transfer information read write
[Example 2: When an odd address and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword]
Clock
DTC activation request DTC request
R W B L
Address
B
W
Vector read
Transfer information read
Data transfer
Transfer information write
[Example 3: When address 4n + 2 and address 4n are specified in SAR and DAR, respectively, and when the data size of transfer is specified as longword]
Clock
DTC activation request DTC request
R W W L
Address
W
Vector read
Transfer information Data transfer Transfer information read write
Figure 12.5 Bus Cycle Division Example
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Section 12 Data Transfer Controller (DTC)
12.5.2
Transfer Information Read Skip Function
By setting the RRS bit of DTCCR, the vector address read and transfer information read can be skipped. The current DTC vector number is always compared with the vector number of previous activation. If the vector numbers match when RRS = 1, a DTC data transfer is performed without reading the vector address and transfer information. If the previous activation is a chain transfer, the vector address read and transfer information read are always performed. Figure 12.6 shows the transfer information read skip timing. To modify the vector table and transfer information, temporarily clear the RRS bit to 0, modify the vector table and transfer information, and then set the RRS bit to 1 again. When the RRS bit is cleared to 0, the stored vector number is deleted, and the updated vector table and transfer information are read at the next activation.
Clock
DTC activation (1) request DTC request Transfer information read skip Address
Vector read R W
(2)
R
W
Transfer information Data Transfer information read transfer write
Data Transfer information transfer write
Note: Transfer information read is skipped when the activation sources of (1) and (2) (vector numbers) are the same while RRS = 1.
Figure 12.6 Transfer Information Read Skip Timing
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Section 12 Data Transfer Controller (DTC)
12.5.3
Transfer Information Writeback Skip Function
By specifying bit SM1 in MRA and bit DM1 in MRB to the fixed address mode, a part of transfer information will not be written back. This function is performed regardless of short or full address mode. Table 12.5 shows the transfer information writeback skip condition and writeback skipped registers. Note that the CRA and CRB are always written back regardless of the short or full address mode. In addition in full address mode, the writeback of the MRA and MRB are always skipped. Table 12.5 Transfer Information Writeback Skip Condition and Writeback Skipped Registers
SM1 0 0 1 1 DM1 0 1 0 1 SAR Skipped Skipped Written back Written back DAR Skipped Written back Skipped Written back
12.5.4
Normal Transfer Mode
In normal transfer mode, one operation transfers one byte, one word, or one longword of data. From 1 to 65,536 transfers can be specified. The transfer source and destination addresses can be specified as incremented, decremented, or fixed. When the specified number of transfers ends, an interrupt can be requested to the CPU. Table 12.6 lists the register function in normal transfer mode. Figure 12.7 shows the memory map in normal transfer mode. Table 12.6 Register Function in Normal Transfer Mode
Register SAR DAR CRA CRB Note: * Function Source address Destination address Transfer count A Transfer count B Transfer information writeback is skipped. Written Back Value Incremented/decremented/fixed* Incremented/decremented/fixed* CRA - 1 Not updated
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Section 12 Data Transfer Controller (DTC)
Transfer source data area
Transfer destination data area
SAR Transfer
DAR
Figure 12.7 Memory Map in Normal Transfer Mode 12.5.5 Repeat Transfer Mode
In repeat transfer mode, one operation transfers one byte, one word, or one longword of data. By the DTS bit in MRB, either the source or destination can be specified as a repeat area. From 1 to 256 transfers can be specified. When the specified number of transfers ends, the transfer counter and address register specified as the repeat area is restored to the initial state, and transfer is repeated. The other address register is then incremented, decremented, or left fixed. In repeat transfer mode, the transfer counter (CRAL) is updated to the value specified in CRAH when CRAL becomes H'00. Thus the transfer counter value does not reach H'00, and therefore a CPU interrupt cannot be requested when DISEL = 0. Table 12.7 lists the register function in repeat transfer mode. Figure 12.8 shows the memory map in repeat transfer mode.
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Section 12 Data Transfer Controller (DTC)
Table 12.7 Register Function in Repeat Transfer Mode
Written Back Value Register Function SAR Source address CRAL is not 1 CRAL is 1
Incremented/decremented/fixed DTS =0: Incremented/ * decremented/fixed* DTS = 1: SAR initial value
DAR
Destination address Incremented/decremented/fixed DTS = 0: DAR initial value * DTS =1: Incremented/ decremented/fixed* Transfer count storage Transfer count A Transfer count B * CRAH CRAL - 1 Not updated CRAH CRAH Not updated
CRAH CRAL CRB Note:
Transfer information writeback is skipped.
Transfer source data area (specified as repeat area)
Transfer destination data area
SAR Transfer
DAR
Figure 12.8 Memory Map in Repeat Transfer Mode (When Transfer Source is Specified as Repeat Area)
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Section 12 Data Transfer Controller (DTC)
12.5.6
Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area by the DTS bit in MRB. The block size is 1 to 256 bytes (1 to 256 words, or 1 to 256 longwords). When the transfer of one block ends, the block size counter (CRAL) and address register (SAR when DTS = 1 or DAR when DTS = 0) specified as the block area is restored to the initial state. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. When the specified number of transfers ends, an interrupt is requested to the CPU. Table 12.8 lists the register function in block transfer mode. Figure 12.9 shows the memory map in block transfer mode. Table 12.8 Register Function in Block Transfer Mode
Register Function SAR DAR CRAH CRAL CRB Note: * Source address Destination address Block size storage Block size counter Block transfer counter Written Back Value DTS =0: Incremented/decremented/fixed* DTS = 1: SAR initial value DTS = 0: DAR initial value DTS =1: Incremented/decremented/fixed* CRAH CRAH CRB - 1
Transfer information writeback is skipped.
Transfer source data area
Transfer destination data area (specified as block area)
SAR
1st block : : Nth block
Transfer Block area DAR
Figure 12.9 Memory Map in Block Transfer Mode (When Transfer Destination is Specified as Block Area)
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Section 12 Data Transfer Controller (DTC)
12.5.7
Chain Transfer
Setting the CHNE bit in MRB to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. Setting the CHNE and CHNS bits in MRB set to 1 enables a chain transfer only when the transfer counter reaches 0. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 12.10 shows the chain transfer operation. In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting the DISEL bit to 1, and the interrupt source flag for the activation source and DTCER are not affected. In repeat transfer mode, setting the RCHNE bit in DTCCR and the CHNE and CHNS bits in MRB to 1 enables a chain transfer after transfer with transfer counter = 1 has been completed.
Data area
Transfer source data (1)
Vector table
Transfer information stored in user area
Transfer destination data (1)
DTC vector address
Transfer information start address
Transfer information CHNE = 1 Transfer information CHNE = 0
Transfer source data (2)
Transfer destination data (2)
Figure 12.10 Operation of Chain Transfer
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Section 12 Data Transfer Controller (DTC)
12.5.8
Operation Timing
Figures 12.11 to 12.14 show the DTC operation timings.
Clock
DTC activation request DTC request
Address
Vector read Transfer information read
R
W
Data transfer
Transfer information write
Figure 12.11 DTC Operation Timing (Example of Short Address Mode in Normal Transfer Mode or Repeat Transfer Mode)
Clock
DTC activation request DTC request
Address
Vector read Transfer information read
R
W
R
W
Data transfer
Transfer information write
Figure 12.12 DTC Operation Timing (Example of Short Address Mode in Block Transfer Mode with Block Size of 2)
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Section 12 Data Transfer Controller (DTC)
Clock
DTC activation request DTC request
Address
R
W
R
W
Vector read
Transfer information read
Data transfer
Transfer information write
Transfer information read
Data transfer
Transfer information write
Figure 12.13 DTC Operation Timing (Example of Short Address Mode in Chain Transfer)
Clock
DTC activation request
DTC request
Address
R
W
Vector read
Transfer information read
Data Transfer information transfer write
Figure 12.14 DTC Operation Timing (Example of Full Address Mode in Normal Transfer Mode or Repeat Transfer Mode)
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Section 12 Data Transfer Controller (DTC)
12.5.9
Number of DTC Execution Cycles
Table 12.9 shows the execution status for a single DTC data transfer, and table 12.10 shows the number of cycles required for each execution. Table 12.9 DTC Execution Status
Vector Read I Transfer Information Read J Transfer Information Write L Internal Operation N
Mode
Data Read L
Data Write M
Normal 1 Repeat 1 Block 1 transfer
0*1 0*1 0*1
4*2 4*2 4*2
3*3 3*3 3*3
0*1 0*1 0*1
3*2.3 2*4 3*2.3 2*4 3*2.3 2*4
1*5 1*5 1*5
3*6 3*6
6
2*7 2*7
7
1 1
3*6 3*6
6
2*7 2*7
7
1 1
1 1
0*1 0*1 0*1
3*P* 2*P* 1*P 3*P* 2*P* 1*P 1
[Legend] P: Block size (CRAH and CRAL value) Note: 1. When transfer information read is skipped 2. In full address mode operation 3. In short address mode operation 4. When the SAR or DAR is in fixed mode 5. When the SAR and DAR are in fixed mode 6. When a longword is transferred while an odd address is specified in the address register 7. When a word is transferred while an odd address is specified in the address register or when a longword is transferred while address 4n + 2 is specified
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Section 12 Data Transfer Controller (DTC)
Table 12.10 Number of Cycles Required for Each Execution State
On-Chip On-Chip
Object to be Accessed Bus width Access cycles
Execution Vector read SI status
RAM
ROM
On-Chip I/O Registers 8 2 2 4 8 2 4 8 16 2 2 2 4 2 2 4 32 2 2 2 2 2 2 2 1 2 8 8 8 2 4 8 2 4 8
External Devices 8 3 12 + 4m 12 + 4m 12 + 4m 3+m 4 + 2m 12 + 4m 3+m 4 + 2m 12 + 4m 2 4 4 4 2 2 4 2 2 4 16 3 6 + 2m 6 + 2m 6 + 2m 3+m 3+m 6 + 2m 3+m 3+m 6 + 2m
32 1 1
32 1 1 1 1 1 1 1 1 1 1
Transfer information read SJ 1 Transfer information write Sk 1 Byte data read SL Word data read SL Longword data read SL Byte data write SM Word data write SM Longword data write SM Internal operation SN 1 1 1 1 1 1
[Legend] m: Number of wait cycles 0 to 7 (For details, see section 9, Bus Controller (BSC).)
The number of execution cycles is calculated from the formula below. Note that means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution cycles = I * SI + (J * SJ + K * SK + L * SL + M * SM) + N * SN 12.5.10 DTC Bus Release Timing The DTC requests the bus mastership to the bus arbiter when an activation request occurs. The DTC releases the bus after a vector read, transfer information read, a single data transfer, or transfer information writeback. The DTC does not release the bus during transfer information read, single data transfer, or transfer information writeback. 12.5.11 DTC Priority Level Control to the CPU The priority of the DTC activation sources over the CPU can be controlled by the CPU priority level specified by bits CPUP2 to CPUP0 in CPUPCR and the DTC priority level specified by bits DTCP2 to DTCP0. For details, see section 7, Interrupt Controller.
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Section 12 Data Transfer Controller (DTC)
12.6
DTC Activation by Interrupt
The procedure for using the DTC with interrupt activation is shown in figure 12.15.
DTC activation by interrupt [1] Clearing the RRS bit in DTCCR to 0 clears the read skip flag of transfer information. Read skip is not performed when the DTC is activated after clearing the RRS bit. When updating transfer information, the RRS bit must be cleared. [2] Set the MRA, MRB, SAR, DAR, CRA, and CRB transfer information in the data area. For details on setting transfer information, see section 12.2, Register Descriptions. For details on location of transfer information, see section 12.4, Location of Transfer Information and DTC Vector Table. [3] Set the start address of the transfer information in the DTC vector table. For details on setting DTC vector table, see section 12.4, Location of Transfer Information and DTC Vector Table. [4] [4] Setting the RRS bit to 1 performs a read skip of second time or later transfer information when the DTC is activated consecutively by the same interrupt source. Setting the RRS bit to 1 is always allowed. However, the value set during transfer will be valid from the next transfer. [5] Set the bit in DTCER corresponding to the DTC activation interrupt source to 1. For the correspondence of interrupts and DTCER, refer to table 12.1. The bit in DTCER may be set to 1 on the second or later transfer. In this case, setting the bit is not needed. [6] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. For details on the settings of the interrupt enable bits, see the corresponding descriptions of the corresponding module. Clear activation source [7] [7] After the end of one data transfer, the DTC clears the activation source flag or clears the corresponding bit in DTCER and requests an interrupt to the CPU. The operation after transfer depends on the transfer information. For details, see section 12.2, Register Descriptions and figure 12.4.
Clear RRS bit in DTCCR to 0
[1]
Set transfer information (MRA, MRB, SAR, DAR, CRA, CRB)
[2]
Set starts address of transfer information in DTC vector table
[3]
Set RRS bit in DTCCR to 1
Set corresponding bit in DTCER to 1
[5]
Set enable bit of interrupt request for activation source to 1
[6]
Interrupt request generated
DTC activated
Determine clearing method of activation source Clear corresponding bit in DTCER Corresponding bit in DTCER cleared or CPU interrupt requested
Transfer end
Figure 12.15 DTC with Interrupt Activation
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Section 12 Data Transfer Controller (DTC)
12.7
12.7.1
Examples of Use of the DTC
Normal Transfer Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. 1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal transfer mode (MD1 = MD0 = 0), and byte size (Sz1 = Sz0 = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the RDR address of the SCI in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. 2. Set the start address of the transfer information for an RXI interrupt at the DTC vector address. 3. Set the corresponding bit in DTCER to 1. 4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the receive end (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. 5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. 6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. 12.7.2 Chain Transfer
An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG's NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0).
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Section 12 Data Transfer Controller (DTC)
1. Perform settings for transfer to the PPG's NDR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz1 = 0, Sz0 = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain transfer mode (CHNE = 1, CHNS = 0, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. 2. Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz1 = 0, Sz0 = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. 3. Locate the TPU transfer information consecutively after the NDR transfer information. 4. Set the start address of the NDR transfer information to the DTC vector address. 5. Set the bit corresponding to the TGIA interrupt in DTCER to 1. 6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. 7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. 8. Set the CST bit in TSTR to 1, and start the TCNT count operation. 9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. 10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. 12.7.3 Chain Transfer when Counter = 0
By executing a second data transfer and performing re-setting of the first data transfer only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 12.16 shows the chain transfer when the counter value is 0.
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Section 12 Data Transfer Controller (DTC)
1. For the first transfer, set the normal transfer mode for input data. Set the fixed transfer source address, CRA = H'0000 (65,536 times), CHNE = 1, CHNS = 1, and DISEL = 0. 2. Prepare the upper 8-bit addresses of the start addresses for 65,536-transfer units for the first data transfer in a separate area (in ROM, etc.). For example, if the input buffer is configured at addresses H'200000 to H'21FFFF, prepare H'21 and H'20. 3. For the second transfer, set repeat transfer mode (with the source side as the repeat area) for resetting the transfer destination address for the first data transfer. Use the upper eight bits of DAR in the first transfer information area as the transfer destination. Set CHNE = DISEL = 0. If the above input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2. 4. Execute the first data transfer 65536 times by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 5. Next, execute the first data transfer the 65536 times specified for the first data transfer by means of interrupts. When the transfer counter for the first data transfer reaches 0, the second data transfer is started. Set the upper eight bits of the transfer source address for the first data transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer and the transfer counter are H'0000. 6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer, no interrupt request is sent to the CPU.
Input circuit
Transfer information located on the on-chip memory Input buffer
1st data transfer information 2nd data transfer information
Chain transfer (counter = 0)
Upper 8 bits of DAR
Figure 12.16 Chain Transfer when Counter = 0
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Section 12 Data Transfer Controller (DTC)
12.8
Interrupt Sources
An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and priority level control in the interrupt controller.
12.9
12.9.1
Usage Notes
Module Stop State Setting
Operation of the DTC can be disabled or enabled using the module stop control register. The initial setting is for operation of the DTC to be enabled. Register access is disabled by setting the module stop state. The module stop state cannot be set while the DTC is activated. For details, refer to section 27, Power-Down Modes. 12.9.2 On-Chip RAM
Transfer information can be located in on-chip RAM. In this case, the RAME bit in SYSCR must not be cleared to 0. 12.9.3 DMAC Transfer End Interrupt
When the DTC is activated by a DMAC transfer end interrupt, the DTE bit of DMDR is not controlled by the DTC but its value is modified with the write data regardless of the transfer counter value and DISEL bit setting. Accordingly, even if the DTC transfer counter value becomes 0, no interrupt request may be sent to the CPU in some cases. When the DTC is activated by a DMAC transfer end interrupt, even if DISEL=0, an automatic clearing of the relevant activation source flag is not automatically cleared by the DTC. Therefore, write 1 to the DTE bit by the DTC transfer and clear the activation source flag to 0. 12.9.4 DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are disabled, multiple activation sources can be set at one time (only at the initial setting) by writing data after executing a dummy read on the relevant register.
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Section 12 Data Transfer Controller (DTC)
12.9.5
Chain Transfer
When chain transfer is used, clearing of the activation source or DTCER is performed when the last of the chain of data transfers is executed. At this time, SCI and A/D converter interrupt/activation sources, are cleared when the DTC reads or writes to the relevant register. Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the relevant register is not included in the last chained data transfer, the interrupt or activation source will be retained. 12.9.6 Transfer Information Start Address, Source Address, and Destination Address
The transfer information start address to be specified in the vector table should be address 4n. If an address other than address 4n is specified, the lower 2 bits of the address are regarded as 0s. The source and destination addresses specified in SAR and DAR, respectively, will be transferred in the divided bus cycles depending on the address and data size. 12.9.7 Transfer Information Modification
When IBCCS = 1 and the DMAC is used, clear the IBCCS bit to 0 and then set to 1 again before modifying the DTC transfer information in the CPU exception handling routine initiated by a DTC transfer end interrupt. 12.9.8 Endian Format
The DTC supports big and little endian formats. The endian formats used when transfer information is written to and when transfer information is read from by the DTC must be the same.
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Section 12 Data Transfer Controller (DTC)
12.9.9
Points for Caution when Overwriting DTCER
When overwriting of the DTC-transfer enable register (DTCER) and the generation of an interrupt that is a source for DTC activation are in competition, activation of the DTC and interrupt exception processing by the CPU will both proceed at the same time. Depending on the conditions at this time, doubling of interrupts may occur. If there is a possibility of competition between overwriting of the DTCER and generation of an interrupt that is a source for DTC activation, proceed with overwriting of the DTCER according to the relevant procedure given below.
In the case of interrupt-control mode 0 In the case of interrupt-control mode 2
Back-up the value of the CCR.
Back-up the value of the EXR.
Set the interrupt-mask bit to 1 (corresponding bit = 1 in the CCR).
Set the interrupt-request masking level to 7 (in the EXR, I2, I1, I0 = b'111).
Overwrite the DTCER.
Overwrite the DTCER. Interrupts are masked
Dummy-read the DTCER.
Dummy-read the DTCER.
Restore the original value of the interrupt-mask bit.
Restore the original value of the interrupt-request masking level.
END
END
Figure 12.17 Example of Procedures for Overwriting the DTCER
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Section 13 I/O Ports
Section 13 I/O Ports
Table 13.1 summarizes the port functions. The pins of each port also have other functions such as input/output pins of on-chip peripheral modules or external interrupt input pins. Each I/O port includes a data direction register (DDR) that controls input/output, a data register (DR) that stores output data, a port register (PORT) used to read the pin states, and an input buffer control register (ICR) that controls input buffer on/off. Port 5 does not have a DR or a DDR register. Ports D to F, H to K, and I have internal input pull-up MOSs and a pull-up MOS control register (PCR) that controls the on/off state of the input pull-up MOSs. Ports 2 and F include an open-drain control register (ODR) that controls on/off of the output buffer PMOSs. All of the I/O ports can drive a single TTL load and capacitive loads up to 30 pF. Also, all of the I/O ports can drive Darlington transistors when functioning as output ports. Port 2, J, and K are Schmitt-trigger input. Schmitt-trigger inputs for other ports are enabled when used as the IRQ, TPU, TMR, or IIC2 input. Table 13.1 Port Functions
Function SchmittTrigger 1 Input* Input Pull-up MOS Function OpenDrain Output Function
Port
Description
Bit
I/O P17/SCL0
Input IRQ7-A/ TCLKD-B/ ADTRG1 IRQ6-A/ TCLKC-B IRQ5-A/ TCLKB-B/ RxD5/ IrRXD DREQ1 IRQ4-A/ TCLKA-B EDREQ1-A ADTRG0/ IRQ3-A
Output EDRAK1
Port 1 General I/O port 7 also functioning as interrupt inputs, SCI I/Os, DMAC 6 I/Os, EXDMAC I/Os, A/D converter inputs, 5 TPU inputs, and IIC2 I/Os
IRQ7-A, TCLKD-B, SCL0 IRQ6-A, TCLKC-B, SDA0 IRQ5-A, TCLKB-B, SCL1 IRQ4-A, TCLKA-B, SDA1 IRQ3-A
P16/SDA0
DACK1 EDACK1-A TEND1 ETEND1-A
P15/SCL1
4
P14/SDA1
TxD5/ IrTxD
3
P13
EDRAK0
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Section 13 I/O Ports
Function SchmittTrigger 1 Input * IRQ2-A IRQ1-A IRQ0-A
Port
Description
Bit
I/O P12/SCK2 P11 P10
Input IRQ2-A RxD2/ IRQ1-A DREQ0/ IRQ0-A/ EDREQ0-A
Output DACK0 EDACK0-A TEND0 ETEND0-A TxD2
Input Pull-up MOS Function
OpenDrain Output Function
2 Port 1 General I/O port also functioning as interrupt inputs, 1 SCI I/Os, DMAC I/Os, EXDMAC 0 I/Os, A/D converter inputs, TPU inputs, and IIC2 I/Os Port 2 General I/O port 7 also functioning as interrupt inputs, PPG outputs, TPU 6 I/Os, TMR I/Os, and SCI I/Os 5
P27/ TIOCB5 P26/ TIOCA5 P25/ TIOCA4 P24/ TIOCB4/ SCK1 P23/ TIOCD3 P22/ TIOCC3 P21/ TIOCA3
TIOCA5
PO7
P27, TIOCB5, TIOCA5
O
TMCI1/ RxD1 TIOCA4/ TMRI1
PO6/TMO1/ All input TxD1 functions PO5 P25, TIOCA4, TMCI1 P24, TIOCB4, TIOCA4, TMRI1 P23, TIOCD3, IRQ11-A
4
PO4
3
IRQ11-A/ TIOCC3 IRQ10-A TMCI0/ RxD0/ IRQ9-A TIOCA3/ TMRI0/ IRQ8-A
PO3
2 1
PO2/TMO0/ All input TxD0 functions PO1 P21, IRQ9-A, TIOCA3, TMCI0 P20, IRQ8-A, TIOCB3, TIOCA3, TMRI0
0
P20/ TIOCB3/ SCK0
PO0
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Section 13 I/O Ports
Function SchmittTrigger 1 Input * IRQ7-B IRQ6-B IRQ5-B IRQ4-B IRQ3-B IRQ2-B IRQ1-B IRQ0-B
Port
Description
Bit
I/O
Input P57/AN7/ IRQ7-B P56/AN6/ IRQ6-B P55/AN5/ IRQ5-B P54/AN4/ IRQ4-B P53/AN3/ IRQ3-B P52/AN2/ IRQ2-B P51/AN1/ IRQ1-B P50/AN0/ IRQ0-B
Output DA1 DA0
Input Pull-up MOS Function
OpenDrain Output Function
Port 5 General input port 7 also functioning as interrupt inputs, 6 A/D converter inputs, and D/A converter outputs 5 4 3 2 1 0
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Section 13 I/O Ports
Function SchmittTrigger 1 Input* TCK
Port
Description
Bit 7 6 5
I/O P65
Input TCK
Output TMO3/ DACK3 EDACK1-B TEND3 ETEND1-B
Input Pull-up MOS Function
OpenDrain Output Function
Port 6 General I/O port also functioning as SCI inputs, DMAC I/Os, EXDMAC I/Os, H-UDI inputs, and interrupt inputs
4 3
P64 P63
TMCI3/TDI TMRI3/ DREQ3/ IRQ11-B/ TMS EDREQ1-B IRQ10-B/ TRST TMCI2/ RxD4/ IRQ9-B TMRI2/ DREQ2/ IRQ8-B, EDREQ0-B PA7 BREQ/ WAIT
TMCI3, TDI TMRI3, IRQ11-B, TMS
2
P62/SCK4
TMO2/ DACK2 EDACK0-B TEND2 ETEND0-B TxD4
IRQ10-B, TRST TMCI2, IRQ9-B TMRI2, IRQ8-B
1
P61
0
P60
Port A General I/O port also functioning as system clock output and bus control I/Os
7 6 5 4 3 2 1 0
PA6 PA5 PA4 PA3 PA2 PA1 PA0
B AS/AH/ BS-B RD LHWR/LUB LLWR/LLB BACK/ (RD/WR) BREQO/ BS-A
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Section 13 I/O Ports
Function SchmittTrigger 1 Input*
Port
Description
Bit
I/O PB3 PB2 PB1
Input
Output CS3-A/ CS7-A CS2-A/ CS6-A CS1/ CS2-B/ CS5-A/ CS6-B/ CS7-B CS0/ CS4-A/ CS5-B A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A10 A9 A8
Input Pull-up MOS Function
OpenDrain Output Function
Port B General I/O port 3 also functioning as bus control 2 outputs 1
0
PB0
Port D General I/O port 7 3 * also functioning as 6 address outputs 5 4 3 2 1 0 Port E General I/O port 7 3 * also functioning as 6 address outputs 5 4 3 2 1 0
PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

O
O
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Section 13 I/O Ports
Function SchmittTrigger 1 Input*
Port Port F
Description
Bit I/O PF4 PF3 PF2 PF1 PF0 PH7/D7* PH6/D6* PH5/D5* PH4/D4* PH3/D3* PH2/D2* PH1/D1* PH0/D0*
2
Input TIOCA8/TCLKH
Output A20 A19 A18 A17 A16 PO23 PO22
Input Pull-up MOS Function O
OpenDrain Output Function O
General I/O port 4 also functioning 3 as address 2 outputs 1 0
Port H
General I/O port 7 also functioning 6 as bi-directional 5 data bus 4 3 2 1 0
O
2
2
2
2
2
2
2
Port I
General I/O port 7 also functioning 6 as bi-directional 5 data bus 4 3 2 1 0
PI7/D15* PI6/D14* PI5/D13* PI4/D12* PI3/D11* PI2/D10* PI1/D9*
2
2
O
2
2
2
2
2
PI0/D8*
2
Port J*
4
General I/O port 7 also functioning 6 PPG I/Os and 5 TPU I/Os 4 3 2 1 0
PJ7/TIOCB8 PJ6/TIOCA8 PJ5/TIOCB7 PJ4/TIOCA7 PJ3/TIOCD6 PJ2/TIOCC6 PJ1/TIOCB6 PJ0/TIOCA6
All input functions
O
TIOCA7/TCLKG PO21 TIOCC6/TCLKF TCLKE TIOCA6 PO20 PO19 PO18 PO17 PO16
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Section 13 I/O Ports
Function SchmittTrigger 1 Input* All input functions
Port
4
Description
Bit I/O
Input
Output PO31 PO30 PO29 PO28 PO27 PO26 PO25 PO24 TxD6
Input Pull-up MOS Function O
OpenDrain Output Function
Port K* General I/O port 7 also functioning 6 PPG I/Os and 5 TPU I/Os 4 3 2 1 0 Port M General I/O port 7 also functioning 6 as SCI I/Os 5 4 3 2 1 0
PK7/TIOCB11 TIOCA11 PK6/TIOCA11 PK5/TIOCB10 TIOCA10 PK4/TIOCA10 PK3/TIOCD9 PK2/TIOCC9 PK1/TIOCB9 PK0/TIOCA9 PM4 PM3 PM2 PM1 PM0 TIOCC9 TIOCA9 RxD6
Notes: 1. 2. 3. 4.
Pins without Schmitt-trigger input have CMOS input functions. Addresses are also output when accessing to the address/data multiplexed I/O space. Pins are disabled when PCJKE = 1. Pins are disabled when PCJKE = 0.
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Section 13 I/O Ports
13.1
Register Descriptions
Table 13.2 lists each port registers. Table 13.2 Register Configuration in Each Port
Number of Pins 8 8 8 6 8 4
1
Registers DDR O O O O O O O O O O O O O DR O O O O O O O O O O O O O PORT O O O O O O O O O O O O O O ICR O O O O O O O O O O O O O O PCR O O O O O O O ODR O O
Port Port 1 Port 2 Port 5 Port 6 Port A Port B Port D* Port E* Port F Port H Port I Port J*
2 2 1
8 8 5 8 8 8 8 5
Port K* Port M
[Legend] O: Register exists : No register exists Notes: 1. Do not access port D or E registers when PCJKE = 1. 2. Do not access port J or K registers when PCJKE = 0.
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Section 13 I/O Ports
13.1.1
Data Direction Register (PnDDR) (n = 1, 2, 6, A, B, D to F, H to K, and M)
DDR is an 8-bit write-only register that specifies the port input or output for each bit. A read from the DDR is invalid and DDR is always read as an undefined value. When the general I/O port function is selected, the corresponding pin functions as an output port by setting the corresponding DDR bit to 1; the corresponding pin functions as an input port by clearing the corresponding DDR bit to 0. The initial DDR values are shown in table 13.3.
Bit Bit Name Initial Value R/W Note: 7 Pn7DDR 0 W 6 Pn6DDR 0 W 5 Pn5DDR 0 W 4 Pn4DDR 0 W 3 Pn3DDR 0 W 2 Pn2DDR 0 W 1 Pn1DDR 0 W 0 Pn0DDR 0 W
The lower six bits are valid and the upper two bits are reserved for port 6 registers. The lower four bits are valid and the upper four bits are reserved for port B registers. The lower five bits are valid and the upper three bits are reserved for port F registers. The lower five bits are valid and the upper three bits are reserved for port M registers. Do not access port J or K registers when PCJKE = 0. Do not access port D or E registers when PCJKE = 1.
Table 13.3 Startup Mode and Initial Value
Startup Mode Port Port A Other ports External Extended Mode H'80 H'00 Single-Chip Mode H'00 H'00
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Section 13 I/O Ports
13.1.2
Data Register (PnDR) (n = 1, 2, 6, A, B, D to F, H to K, and M)
DR is an 8-bit readable/writable register that stores the output data of the pins to be used as the general output port. The initial value of DR is H'00.
Bit Bit Name Initial Value R/W Note: 7 Pn7DR 0 R/W 6 Pn6DR 0 R/W 5 Pn5DR 0 R/W 4 Pn4DR 0 R/W 3 Pn3DR 0 R/W 2 Pn2DR 0 R/W 1 Pn1DR 0 R/W 0 Pn0DR 0 R/W
The lower six bits are valid and the upper two bits are reserved for port 6 registers. The lower four bits are valid and the upper four bits are reserved for port B registers. The lower five bits are valid and the upper three bits are reserved for port F registers. The lower five bits are valid and the upper three bits are reserved for port M registers. Do not access port J or K registers when PCJKE = 0. Do not access port D or E registers when PCJKE = 1.
13.1.3
Port Register (PORTn) (n = 1, 2, 5, 6, A, B, D to F, H to K, and M)
PORT is an 8-bit read-only register that reflects the port pin state. A write to PORT is invalid. When PORT is read, the DR bits that correspond to the respective DDR bits set to 1 are read and the status of each pin whose corresponding DDR bit is cleared to 0 is also read regardless of the ICR value. The initial value of PORT is undefined and is determined based on the port pin state.
Bit Bit Name Initial Value R/W Note: 7 Pn7 Undefined R 6 Pn6 Undefined R 5 Pn5 Undefined R 4 Pn4 Undefined R 3 Pn3 Undefined R 2 Pn2 Undefined R 1 Pn1 Undefined R 0 Pn0 Undefined R
The lower six bits are valid and the upper two bits are reserved for port 6 registers. The lower four bits are valid and the upper four bits are reserved for port B registers. The lower five bits are valid and the upper three bits are reserved for port F registers. The lower five bits are valid and the upper three bits are reserved for port M registers. Do not access port J or K registers when PCJKE = 0. Do not access port D or E registers when PCJKE = 1.
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Section 13 I/O Ports
13.1.4
Input Buffer Control Register (PnICR) (n = 1, 2, 5, 6, A, B, D to F, H to K, and M)
ICR is an 8-bit readable/writable register that controls the port input buffers. For bits in ICR set to 1, the input buffers of the corresponding pins are valid. For bits in ICR cleared to 0, the input buffers of the corresponding pins are invalid and the input signals are fixed high. When the pin functions as an input for the peripheral modules, the corresponding bits should be set to 1. The initial value should be written to a bit whose corresponding pin is not used as an input or is used as an analog input/output pin. When PORT is read, the pin state is always read regardless of the ICR value. When the ICR value is cleared to 0 at this time, the read pin state is not reflected in a corresponding on-chip peripheral module. If ICR is modified, an internal edge may occur depending on the pin state. Accordingly, ICR should be modified when the corresponding input pins are not used. For example, an IRQ input, modify ICR while the corresponding interrupt is disabled, clear the IRQF flag in ISR of the interrupt controller to 0, and then enable the corresponding interrupt. If an edge occurs after the ICR setting, the edge should be cancelled. The initial value of ICR is H'00.
Bit Bit Name Initial Value R/W Note: 7 Pn7ICR 0 R/W 6 Pn6ICR 0 R/W 5 Pn5ICR 0 R/W 4 Pn4ICR 0 R/W 3 Pn3ICR 0 R/W 2 Pn2ICR 0 R/W 1 Pn1ICR 0 R/W 0 Pn0ICR 0 R/W
The lower six bits are valid and the upper two bits are reserved for port 6 registers. The lower four bits are valid and the upper four bits are reserved for port B registers. The lower five bits are valid and the upper three bits are reserved for port F registers. The lower five bits are valid and the upper three bits are reserved for port M registers. Do not access port J or K registers when PCJKE = 0. Do not access port D or E registers when PCJKE = 1.
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Section 13 I/O Ports
13.1.5
Pull-Up MOS Control Register (PnPCR) (n = D to F, and H to K)
PCR is an 8-bit readable/writable register that controls on/off of the port input pull-up MOS. If a bit in PCR is set to 1 while the pin is in input state, the input pull-up MOS corresponding to the bit in PCR is turned on. Table 13.4 shows the input pull-up MOS state. The initial value of PCR is H'00.
Bit Bit Name Initial Value R/W Note: 7 Pn7PCR 0 R/W 6 Pn6PCR 0 R/W 5 Pn5PCR 0 R/W 4 Pn4PCR 0 R/W 3 Pn3PCR 0 R/W 2 Pn2PCR 0 R/W 1 Pn1PCR 0 R/W 0 Pn0PCR 0 R/W
The lower five bits are valid and the upper three bits are reserved for port F registers.
Table 13.4 Input Pull-Up MOS State
Port Port D Pin State Address output Port output Port input Port E Address output Port output Port input Port F Address output Port output Port input Port H Data input/output Port output Port input Port I Data input/output Port output Port input OFF OFF OFF OFF ON/OFF OFF OFF OFF ON/OFF OFF OFF OFF ON/OFF OFF OFF OFF ON/OFF Reset Hardware Standby Mode Software Standby Mode OFF OFF ON/OFF Other Operation
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Section 13 I/O Ports
Port Port J
Pin State Peripheral module output Port output Port input
Reset
Hardware Standby Mode
Software Standby Mode OFF OFF
Other Operation
OFF OFF OFF OFF
ON/OFF
Port K
Peripheral module output Port output Port input
ON/OFF
[Legend] OFF: ON/OFF: The input pull-up MOS is always off. If PCR is set to 1, the input pull-up MOS is on; if PCR is cleared to 0, the input pull-up MOS is off.
13.1.6
Open-Drain Control Register (PnODR) (n = 2 and F)
ODR is an 8-bit readable/writable register that selects the open-drain output function. If a bit in ODR is set to 1, the pin corresponding to that bit in ODR functions as an NMOS opendrain output. If a bit in ODR is cleared to 0, the pin corresponding to that bit in ODR functions as a CMOS output. The initial value of ODR is H'00.
Bit Bit Name Initial Value R/W 7 Pn7ODR 0 R/W 6 Pn6ODR 0 R/W 5 Pn5ODR 0 R/W 4 Pn4ODR 0 R/W 3 Pn3ODR 0 R/W 2 Pn2ODR 0 R/W 1 Pn1ODR 0 R/W 0 Pn0ODR 0 R/W
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Section 13 I/O Ports
13.2
Output Buffer Control
This section describes the output priority of each pin. The name of each peripheral module pin is followed by "_OE". This (for example: TIOCA4_OE) indicates whether the output of the corresponding function is valid (1) or if another setting is specified (0). Table 13.5 lists each port output signal's valid setting. For details on the corresponding output signals, see the register description of each peripheral module. If the name of each peripheral module pin is followed by A or B, the pin function can be modified by the port function control register (PFCR). For details, see section 13.3, Port Function Controller. For a pin whose initial value changes according to the activation mode, "initial value E" indicates the initial value when the LSI is started up in external extended mode and "initial value S" indicates the initial value when the LSI is started in single-chip mode. 13.2.1 (1) Port 1
P17/IRQ7-A/TCLKD-B/SCL0/EDRAK1/ADTRG1
The pin function is switched as shown below according to the combination of the EXDMAC and IIC2 register settings and P17DDR bit setting.
Setting Module Name EXDMAC IIC2 I/O port EXDMAC Pin Function EDRAK1 output SCL0 input/output P17 output P17 input (initial value) EDRAK1_OE 1 0 0 0 IIC2 SCL0_OE 1 0 0 I/O Port P17DDR 1 0
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Section 13 I/O Ports
(2)
P16/DACK1/IRQ6-A/TCLKC-B/SDA0/EDACK1-A
The pin function is switched as shown below according to the combination of the EXDMAC, DMAC and IIC2 register settings and P16DDR bit setting.
Setting Module Name EXDMAC DMAC IIC2 I/O port EXDMAC Pin Function EDACK1-A output DACK1 output SDA0 input/output P16 output P16 input (initial value) EDACK1A_OE 1 0 0 0 0 DMAC DACK1_OE 1 0 0 0 IIC2 SDA0_OE 1 0 0 I/O Port P16DDR -- 1 0
(3)
P15/RxD5/IrRXD/TEND1/ETEND1-A/IRQ5-A/TCLKB-B/SCL1
The pin function is switched as shown below according to the combination of the EXDMAC, DMAC and IIC2 register settings and P15DDR bit setting.
Setting Module Name EXDMAC DMAC IIC2 I/O port EXDMAC Pin Function ETEND1-A output TEND1 output SCL1 input/output P15 output P15 input (initial value) ETEND1A_OE 1 0 0 0 0 DMAC TEND1_OE 1 0 0 0 IIC2 SCL1_OE 1 0 0 I/O Port P15DDR -- -- 1 0
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Section 13 I/O Ports
(4)
P14/TxD5/IrTXD/DREQ1/EDREQ1-A/IRQ4-A/TCLKA-B/SDA1
The pin function is switched as shown below according to the combination of the SCI, IrDA, and IIC2 register settings and P14DDR bit setting.
Setting SCI Module Name SCI IrDA IIC2 I/O port Pin Function TxD5 output IrTXD output SDA1 input/output P14 output P14 input (initial value) TxD5_OE 1 0 0 0 0 IrDA IrTXD_OE -- 1 0 0 0 IIC2 SDA1_OE -- -- 1 0 0 I/O Port P14DDR -- -- -- 1 0
(5)
P13/ADTRG0/IRQ3-A/EDRAK0
The pin function is switched as shown below according to the register setting of EXDMAC and the P13DDR bit setting.
Setting EXDMAC Module Name I/O port Pin Function EDRAK0 output P13 output P13 input (initial value) EDRAK0_OE 1 0 0 I/O Port P13DDR 1 0
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Section 13 I/O Ports
(6)
P12/SCK2/DACK0/IRQ2-A/EDACK0-A
The pin function is switched as shown below according to the combination of the EXDMAC, DMAC and SCI register settings and P12DDR bit setting.
Setting Module Name EXDMAC DMAC SCI I/O port EXDMAC Pin Function EDACK0-A output DACK0 output SCK2 output P12 output P12 input (initial value) EDACK0A_OE 1 0 0 0 0 DMAC DACK0_OE 1 0 0 0 SCI SCK2_OE 1 0 0 I/O Port P12DDR 1 0
(7)
P11/RxD2/TEND0/IRQ1-A/ETEND0-A
The pin function is switched as shown below according to the combination of the EXDMAC and DMAC register settings and P11DDR bit setting.
Setting Module Name EXDMAC DMAC I/O port EXDMAC Pin Function ETEND0-A output TEND0 output P11 output P11 input (initial value) ETEND0A_OE 1 0 0 0 DMAC TEND0_OE 1 0 0 I/O Port P11DDR 1 0
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Section 13 I/O Ports
(8)
P10/TxD2/DREQ0/IRQ0-A/EDREQ0-A
The pin function is switched as shown below according to the combination of the SCI register setting and P10DDR bit setting.
Setting SCI Module Name SCI I/O port Pin Function TxD2 output P10 output P10 input (initial value) TxD2_OE 1 0 0 I/O Port P10DDR 1 0
13.2.2 (1)
Port 2
P27/PO7/TIOCA5/TIOCB5
The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P27DDR bit setting.
Setting TPU Module Name TPU PPG I/O port Pin Function TIOCB5 output PO7 output P27 output P27 input (initial value) TIOCB5_OE 1 0 0 0 PPG PO7_OE -- 1 0 0 I/O Port P27DDR -- -- 1 0
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Section 13 I/O Ports
(2)
P26/PO6/TIOCA5/TMO1/TxD1/IRQ14-A
The pin function is switched as shown below according to the combination of the TPU, TMR, SCI, and PPG register settings and P26DDR bit setting.
Setting TPU Module Name TPU TMR SCI PPG I/O port Pin Function TIOCA5 output TMO1 output TxD1 output PO6 output P26 output P26 input (initial value) TMR 1 0 0 0 0 SCI
TxD1_OE
PPG
PO6_OE
I/O Port
P26DDR
TIOCA5_OE TMO1_OE
1 0 0 0 0 0
1 0 0 0
1 0 0
1 0
(3)
P25/PO5/TIOCA4/TMCI1/RxD1/IRQ13-A
The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P25DDR bit setting.
Setting TPU Module Name TPU PPG I/O port Pin Function TIOCA4 output PO5 output P25 output P25 input (initial value) TIOCA4_OE 1 0 0 0 PPG PO5_OE 1 0 0 I/O Port P25DDR 1 0
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Section 13 I/O Ports
(4)
P24/PO4/TIOCA4/TIOCB4/TMRI1/SCK1/IRQ12-A
The pin function is switched as shown below according to the combination of the TPU, SCI, and PPG register settings and P24DDR bit setting.
Setting TPU Module Name TPU SCI PPG I/O port Pin Function TIOCB4 output SCK1 output PO4 output P24 output P24 input (initial value) SCI 1 0 0 0 PPG PO4_OE 1 0 0 I/O Port P24DDR 1 0
TIOCB4_OE SCK1_OE 1 0 0 0 0
(5)
P23/PO3/TIOCC3/TIOCD3/IRQ11-A
The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P23DDR bit setting.
Setting TPU Module Name TPU PPG I/O port Pin Function TIOCD3 output PO3 output P23 output P23 input (initial value) TIOCD3_OE 1 0 0 0 PPG PO3_OE -- 1 0 0 I/O Port P23DDR -- -- 1 0
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Section 13 I/O Ports
(6)
P22 /PO2/TIOCC3/TMO0/TxD0/IRQ10-A
The pin function is switched as shown below according to the combination of the TPU, TMR, SCI, and PPG register settings and P22DDR bit setting.
Setting TPU Module Name TPU TMR SCI PPG I/O port Pin Function TIOCC3 output TMO0 output TxD0 output PO2 output P22 output P22 input (initial value)
TIOCC3_OE
TMR 1 0 0 0 0
SCI 1 0 0 0
PPG
PO2_OE
I/O Port
P22DDR
TMO0_OE TxD0_OE
1 0 0 0 0 0
1 0 0
1 0
(7)
P21/PO1/TIOCA3/TMCI0/RxD0/IRQ9-A
The pin function is switched as shown below according to the combination of the TPU and PPG register settings and P21DDR bit setting.
Setting TPU Module Name TPU PPG I/O port Pin Function TIOCA3 output PO1 output P21 output P21 input (initial value) TIOCA3_OE 1 0 0 0 PPG PO1_OE 1 0 0 I/O Port P21DDR 1 0
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Section 13 I/O Ports
(8)
P20/PO0/TIOCA3/TIOCB3/TMRI0/SCK0/IRQ8-A
The pin function is switched as shown below according to the combination of the TPU, PPG, and SCI register settings and P20DDR bit setting.
Setting TPU Module Name TPU SCI PPG I/O port Pin Function TIOCB3 output SCK0 output PO0 output P20 output P20 input (initial value) SCI 1 0 0 0 PPG PO0_OE 1 0 0 I/O Port P20DDR 1 0
TIOCB3_OE SCK0_OE 1 0 0 0 0
13.2.3 (1)
Port 5
P57/AN7/DA1/IRQ7-B
Pin Function DA1 output
Module Name D/A converter
(2)
P56/AN6/DA0/IRQ6-B
Pin Function DA0 output
Module Name D/A converter
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Section 13 I/O Ports
13.2.4 (1)
Port 6
P65/TMO3/DACK3/EDACK1-B/TCK
The pin function is switched as shown below according to the combination of the EXDMAC, DMAC and TMR register settings and P65DDR bit setting.
Setting MCU Operating Mode Except for boundary scan enabled mode* EXDMAC DMAC TMR TMO3_OE 1 0 0 I/O Port P65DDR 1 0
Module Name EXDMAC DMAC TMR I/O port
Pin Function EDACK1-B output DACK3 output TMO3 output P65 output P65 input (initial value)
EDACK1B_OE DACK3_OE 1 0 0 0 0 1 0 0 0
Note:
*
These pins are boundary scan dedicated input pins during boundary scan enabled mode.
(2)
P64/TMCI3/TEND3/ETEND1-B/TDI
The pin function is switched as shown below according to the combination of the EXDMAC and DMAC register settings and P64DDR bit setting.
Setting MCU Operating Mode EXDMAC DMAC I/O Port P64DDR 1 0
Module Name EXDMAC DMAC I/O port
Pin Function
ETEND1B_OE TEND3_OE 1 0 0 0 1 0 0
ETEND1-B output Except for boundary TEND3 output scan enabled P64 output mode* P64 input (initial value)
Note:
*
These pins are boundary scan dedicated input pins during boundary scan enabled mode.
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Section 13 I/O Ports
(3)
P63/TMRI3/DREQ3/EDREQ1-B/IRQ11-B/TMS
The pin function is switched as shown below according to the P63DDR bit setting.
Setting I/O Port Module Name I/O port Pin Function P63 output P63 input (initial value) Note: * MCU Operating Mode Except for boundary scan enabled mode* P63DDR 1 0
These pins are boundary scan dedicated input pins during boundary scan enabled mode.
(4)
P62/TMO2/SCK4/DACK2/EDACK0-B/IRQ10-B/TRST
The pin function is switched as shown below according to the combination of the EXDMAC, DMAC, TMR, and SCI register settings and P62DDR bit setting.
Setting Module Name MCU EXDMAC DMAC Operating Mode EDACK0B_OE DACK2_OE Except for boundary scan enabled mode* 1 0 0 0 0 0 1 0 0 0 0 TMR SCI I/O Port P62DDR 1 0
Pin Function
TMO2_OE SCK4_OE 1 0 0 0 1 0 0
EXDMAC EDACK0-B output DMAC TMR SCI I/O port DACK2 output TMO2 output SCK4 output P62 output P62 input (initial value)
Note:
*
These pins are boundary scan dedicated input pins during boundary scan enabled mode.
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Section 13 I/O Ports
(5)
P61/TMCI2/RxD4/TEND2/ETEND0-B/IRQ9-B
The pin function is switched as shown below according to the combination of the EXDMAC and DMAC register settings and P61DDR bit setting.
Setting Module Name EXDMAC DMAC I/O port EXDMAC Pin Function ETEND0-B output TEND2 output P61 output P61 input (initial value) ETEND0B_OE 1 0 0 0 DMAC TEND2_OE 1 0 0 I/O Port P61DDR 1 0
(6)
P60/TMRI2/TxD4/DREQ2/EDREQ0-B/IRQ8-B
The pin function is switched as shown below according to the combination of the SCI register setting and P60DDR bit setting.
Setting SCI Module Name SCI I/O port Pin Function TxD4 output P60 output P60 input (initial value) TxD4_OE 1 0 0 I/O Port P60DDR 1 0
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Section 13 I/O Ports
13.2.5 (1)
Port A
PA7/B
The pin function is switched as shown below according to the PA7DDR bit setting.
Setting I/O Port Module Name I/O port Pin Function B output* (initial value E) PA7 input (initial value S) PA7DDR 1 0
[Legend] Initial value E: Initial value S:
Initial value in external extended mode Initial value in single-chip mode
(2)
PA6/AS/AH/BS-B
The pin function is switched as shown below according to the combination of operating mode and the EXPE bit, the bus controller register, the port function control register (PFCR), and the PA6DDR bit settings.
Setting Bus Controller Module Name Bus controller Pin Function AH output* BS-B output* AS output* (initial value E) PA6 output PA6 input (initial value S) AH_OE 1 0 0 0 0 BS-B_OE 1 0 0 0 1 0 0 I/O Port AS_OE PA6DDR 1 0
I/O port
[Legend] Initial value E: Initial value in external extended mode Initial value S: Initial value in single-chip mode Note: * Valid in external extended mode (EXPE = 1)
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Section 13 I/O Ports
(3)
PA5/RD
The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, and the PA5DDR bit settings.
Setting MCU Operating Mode Module Name Bus controller I/O port Pin Function RD output* (Initial value E) PA5 output PA5 input (initial value S) EXPE 1 0 0 I/O Port PA5DDR 1 0
[Legend] Initial value E: Initial value in external extended mode Initial value S: Initial value in single-chip mode Note: * Valid in external extended mode (EXPE = 1)
(4)
PA4/LHWR/LUB
The pin function is switched as shown below according to the combination of operating mode and the EXPE bit, the bus controller register, the port function control register (PFCR), and the PA4DDR bit settings.
Setting Bus Controller Module Name Bus controller Pin Function LUB output*
1 1
I/O Port LHWR_OE* 1 0 0
2
LUB_OE* 1 0 0
2
PA4DDR 1 0
LHWR output* (initial value E) I/O port PA4 output PA4 input (initial value S)
[Legend] Initial value E: Initial value in external extended mode Initial value S: Initial value in single-chip mode Notes: 1. Valid in external extended mode (EXPE = 1) 2. When the byte control SRAM space is accessed while the byte control SRAM space is specified or while LHWROE = 1, this pin functions as the LUB output; otherwise, the LHWR output.
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Section 13 I/O Ports
(5)
PA3/LLWR/LLB
The pin function is switched as shown below according to the combination of operating mode and the EXPE bit, the bus controller register, and the PA3DDR bit settings.
Setting Bus Controller Module Name Bus controller Pin Function LLB output*
1 1
I/O Port LLWR_OE* 1 0 0
2
LLB_OE* 1 0 0
2
PA3DDR 1 0
LLWR output* (initial value E) I/O port PA3 output PA3 input (initial value S)
[Legend] Initial value E: Initial value in external extended mode Initial value S: Initial value in single-chip mode Notes: 1. Valid in external extended mode (EXPE = 1) 2. If the byte control SRAM space is accessed, this pin functions as the LLB output; otherwise, the LLWR.
(6)
PA2/BREQ/WAIT
The pin function is switched as shown below according to the combination of the bus controller register settings and the PA2DDR bit setting.
Setting Bus Controller Module Name Bus controller Pin Function BREQ input WAIT input I/O port PA2 output PA2 input (initial value) BCR_BRLE 1 0 0 0 BCR_WAITE 1 0 0 I/O Port PA2DDR 1 0
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Section 13 I/O Ports
(7)
PA1/BACK/(RD/WR)
The pin function is switched as shown below according to the combination of operating mode and the EXPE bit, the bus controller register, the port function control register (PFCR), and the PA1DDR bit settings.
Setting Bus Controller
Byte Control SRAM Selection
I/O Port
Module Name Bus controller
Pin Function BACK output * RD/WR output *
BACK_OE
(RD/WR)_OE
PA1DDR
1 0 0
1 0 0 0
1 0 0
1 0
I/O port
PA1 output PA1 input (initial value)
0 0
Note:
*
Valid in external extended mode (EXPE = 1)
(8)
PA0/BREQO/BS-A
The pin function is switched as shown below according to the combination of operating mode and the EXPE bit, the bus controller register, the port function control register (PFCR), and the PA0DDR bit settings.
Setting I/O Port Module Name Bus controller Pin Function BS-A output* BREQO output* I/O port PA0 output PA0 input (initial value) Note: * BS-A_OE 1 0 0 0 Bus Controller BREQO_OE 1 0 0 I/O Port PA0DDR 1 0
Valid in external extended mode (EXPE = 1)
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Section 13 I/O Ports
13.2.6 (1)
Port B
PB3/CS3/CS7-A
The pin function is switched as shown below according to the combination of operating mode and the EXPE bit, the port function control register (PFCR), and the PB3DDR bit settings.
Setting I/O Port Module Name Bus controller Pin Function CS3 output* CS7-A output* I/O port PB3 output PB3 input (initial value) Note: * CS3_OE 1 0 0 CS7A_OE 1 0 0 PB3DDR 1 0
Valid in external extended mode (EXPE = 1)
(2)
PB2/CS2-A/CS6-A
The pin function is switched as shown below according to the combination of operating mode and the EXPE bit, the port function control register (PFCR), and the PB2DDR bit settings.
Setting I/O Port Module Name Bus controller Pin Function CS2-A output* CS6-A output* I/O port PB2 output PB2 input (initial value) Note: * CS2A_OE 1 0 0 CS6A_OE 1 0 0 PB2DDR 1 0
Valid in external extended mode (EXPE = 1)
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Section 13 I/O Ports
(3)
PB1/CS1/CS2-B/CS5-A/CS6-B/CS7-B
The pin function is switched as shown below according to the combination of operating mode and the EXPE bit, the bus controller register, the port function control register (PFCR), and the PB1DDR bit settings.
Setting I/O Port Module Name Bus controller Pin Function CS1 output* CS2-B output* CS5-A output* CS6-B output* CS7-B output* I/O port PB1 output PB1 input (initial value) Note: *
CS1_OE CS2B_OE CS5A_OE CS6B_OE CS7B_OE PB1DDR
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0
Valid in external extended mode (EXPE = 1)
(4)
PB0/CS0/CS4/CS5-B
The pin function is switched as shown below according to the combination of operating mode and the EXPE bit, the bus controller register, the port function control register (PFCR), and the PB0DDR bit settings.
Setting I/O Port Module Name Bus controller Pin Function CS0 output (initial value E) CS4 output CS5-B output I/O port PB0 output PB0 input (initial value S) CS0_OE 1 0 0 CS4_OE 1 0 0 CS5B_OE 1 0 0 PB0DDR 1 0
[Legend] Initial value E: Initial value in on-chip ROM disabled external mode Initial value S: Initial value in other modes Note: * Valid in external extended mode (EXPE = 1)
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Section 13 I/O Ports
13.2.7
Port D
The pin function of port D can be switched with that of port J according to the combination of operating mode, the EXPE bit, and the PCJKE bit settings. The pin function of port D can be switched according to the PCJKE bit setting in the single-chip mode (EXPE = 0). However, do not change the setting of the PCJKE bit in external extended mode. For details, see section 13.3.12, Port Function Control Register D (PFCRD). (1) PD7/A7, PD6/A6, PD5/A5, PD4/A4, PD3/A3, PD2/A2, PD1/A1, PD0/A0
The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, and the PDnDDR bit settings.
Setting I/O Port Module Name Bus controller I/O port Pin Function Address output PDn output PDn input (initial value) MCU Operating Mode On-chip ROM disabled extended mode On-chip ROM enabled extended mode Single-chip mode* Modes other than on-chip ROM disabled extended mode PDnDDR 1 1 0
[Legend] n: 0 to 7 Note: * Address output is enabled by setting PDnDDR = 1 in external extended mode (EXPE = 1)
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Section 13 I/O Ports
13.2.8
Port E
The pin function of port E can be switched with that of port K according to the combination of operating mode, the EXPE bit, and the PCJKE bit settings. The pin function of port E can be switched according to the PCJKE bit setting in the single-chip mode (EXPE = 0). However, do not change the setting of the PCJKE bit in external extended mode. For details, see section 13.3.12, Port Function Control Register D (PFCRD). (1) PE7/A15, PE6/A14, PE5/A13, PE4/A12, PE3/A11, PE2/A10, PE1/A9, PE0/A8
The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, and the PEnDDR bit settings.
Setting I/O Port Module Name Bus controller I/O port Pin Function Address output PEn output PEn input (initial value) MCU Operating Mode On-chip ROM disabled extended mode On-chip ROM enabled extended mode Single-chip mode* Modes other than on-chip ROM disabled extended mode PEnDDR 1 1 0
[Legend] n: 0 to 7 Note: * Address output is enabled by setting PDnDDR = 1 in external extended mode (EXPE = 1)
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Section 13 I/O Ports
13.2.9 (1)
Port F
PF4/A20
The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, the port function control register (PFCR), and the PF4DDR bit settings.
Setting MCU Operating Mode On-chip ROM disabled extended mode Modes other than on-chip ROM disabled extended mode Note: * I/O Port Module Name Bus controller Pin Function A20 output A20_OE I/O Port PF4DDR
Bus controller I/O port
A20 output* PF4 output PF4 input (initial value)
1 0 0
1 0
Valid in external extended mode (EXPE = 1)
(2)
PF3/A19
The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, the port function control register (PFCR), and the PF3DDR bit settings.
Setting MCU Operating Mode On-chip ROM disabled extended mode Modes other than on-chip ROM disabled extended mode Note: * I/O Port Module Name Bus controller Pin Function A19 output A19_OE I/O Port PF3DDR
Bus controller I/O port
A19 output* PF3 output PF3 input (initial value)
1 0 0
1 0
Valid in external extended mode (EXPE = 1)
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Section 13 I/O Ports
(3)
PF2/A18
The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, the port function control register (PFCR), and the PF2DDR bit settings.
Setting MCU Operating Mode On-chip ROM disabled extended mode Modes other than on-chip ROM disabled extended mode Note: * I/O Port Module Name Bus controller Pin Function A18 output A18_OE I/O Port PF2DDR
Bus controller I/O port
A18 output* PF2 output PF2 input (initial value)
1 0 0
1 0
Valid in external extended mode (EXPE = 1)
(4)
PF1/A17
The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, the port function control register (PFCR), and the PF1DDR bit settings.
Setting MCU Operating Mode On-chip ROM disabled extended mode Modes other than on-chip ROM disabled extended mode Note: * I/O Port Module Name Bus controller Pin Function A17 output A17_OE I/O Port PF1DDR
Bus controller I/O port
A17 output* PF1 output PF1 input (initial value)
1 0 0
1 0
Valid in external extended mode (EXPE = 1)
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Section 13 I/O Ports
(5)
PF0/A16
The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, the port function control register (PFCR), and the PF0DDR bit settings.
Setting MCU Operating Mode On-chip ROM disabled extended mode Modes other than on-chip ROM disabled extended mode Note: * I/O Port Module Name Bus controller Pin Function A16 output A16_OE I/O Port PF0DDR
Bus controller I/O port
A16 output* PF0 output PF0 input (initial value)
1 0 0
1 0
Valid in external extended mode (EXPE = 1)
13.2.10 Port H (1) PH7/D7, PH6/D6, PH5/D5, PH4/D4, PH3/D3, PH2/D2, PH1/D1, PH0/D0
The pin function is switched as shown below according to the combination of operating mode, the EXPE bit, and the PHnDDR bit settings.
Setting MCU Operating Mode Module Name Bus controller I/O port Pin Function Data I/O* (initial value E) PHn output PHn input (initial value S) EXPE 1 0 0 I/O Port PHnDDR 1 0
[Legend] Initial value E: Initial value in external extended mode Initial value S: Initial value in single-chip mode n: 0 to 7 Note: * Valid in external extended mode (EXPE = 1)
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Section 13 I/O Ports
13.2.11 Port I (1) PI7/D15, PI6/D14, PI5/D13, PI4/D12, PI3/D11, PI2/D10, PI1/D9, PI0/D8
The pin function is switched as shown below according to the combination of operating mode, bus mode, the EXPE bit, and the PInDDR bit settings.
Setting Bus Controller Module Name Bus controller I/O port Pin Function Data I/O* (initial value E) PIn output PIn input (initial value S) 16-Bit Bus Mode 1 0 0 I/O Port PInDDR 1 0
[Legend] Initial value E: Initial value in external extended mode Initial value S: Initial value in single-chip mode n: 0 to 7 Note: * Valid in external extended mode (EXPE = 1)
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Section 13 I/O Ports
13.2.12 Port J The pin function of port J can be switched with that of port D according to the combination of operating mode, the EXPE bit, and the PCJKE bit settings. The pin function of port J can be switched according to the PCJKE bit setting in the single-chip mode (EXPE = 0). However, do not change the setting of the PCJKE bit in external extended mode. For details, see section 13.3.12, Port Function Control Register D (PFCRD). (1) PJ7/TIOCA8/TIOCB8/TCLKH/PO23
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PJ7DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO23 output* TIOCB8 output* PJ7 output* PJ7 input* Valid when PCJKE = 1. PO23_OE 1 0 0 0 TPU TIOCB8_OE 1 0 0 I/O Port PJ7DDR 1 0
(2)
PJ6/TIOCA8/PO22
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PJ6DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO22 output* TIOCA8 output* PJ6 output* PJ6 input* Valid when PCJKE = 1. PO22_OE 1 0 0 0 TPU TIOCA8_OE 1 0 0 I/O Port PJ6DDR 1 0
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Section 13 I/O Ports
(3)
PJ5/TIOCA7/TIOCB7/TCLKG/PO21
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PJ5DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO21 output* TIOCB7 output* PJ5 output* PJ5 input* Valid when PCJKE = 1. PO21_OE 1 0 0 0 TPU TIOCB7_OE 1 0 0 I/O Port PJ5DDR 1 0
(4)
PJ4/TIOCA7/PO20
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PJ4DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO20 output* TIOCA7 output* PJ4 output* PJ4 input* Valid when PCJKE = 1. PO20_OE 1 0 0 0 TPU TIOCA7_OE 1 0 0 I/O Port PJ4DDR 1 0
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Section 13 I/O Ports
(5)
PJ3/PO19/TIOCC6/TIOCD6/TCLKF
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PJ3DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO19 output* TIOCD6 output* PJ3 output* PJ3 input* Valid when PCJKE = 1. PO19_OE 1 0 0 0 TPU TIOCD6_OE 1 0 0 I/O Port PJ3DDR 1 0
(6)
PJ2/PO18/TIOCC6/TCLKE
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PJ2DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO18 output* TIOCC6 output* PJ2 output* PJ2 input* Valid when PCJKE = 1. PO18_OE 1 0 0 0 TPU TIOCC6_OE 1 0 0 I/O Port PJ2DDR 1 0
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Section 13 I/O Ports
(7)
PJ1/PO17/TIOCA6/TIOCB6
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PJ1DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO17 output* TIOCB6 output* PJ1 output* PJ1 input* Valid when PCJKE = 1. PO17_OE 1 0 0 0 TPU TIOCB6_OE 1 0 0 I/O Port PJ1DDR 1 0
(8)
PJ0/PO16/TIOCA6
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PJ0DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO16 output* TIOCA6 output* PJ0 output* PJ0 input* Valid when PCJKE = 1. PO16_OE 1 0 0 0 TPU TIOCA6_OE 1 0 0 I/O Port PJ0DDR 1 0
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Section 13 I/O Ports
13.2.13 Port K The pin function of port K can be switched with that of port E according to the combination of operating mode, the EXPE bit, and the PCJKE bit settings. The pin function of port K can be switched according to the PCJKE bit setting in the single-chip mode (EXPE = 0). However, do not change the setting of the PCJKE bit in external extended mode. For details, see section 13.3.12, Port Function Control Register D (PFCRD). (1) PK7/PO31/TIOCA11/TIOCB11
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PK7DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO31 output* TIOCB11 output* PK7 output* PK7 input* Valid when PCJKE = 1. PO31_OE 1 0 0 0 TPU TIOCB11_OE 1 0 0 I/O Port PK7DDR 1 0
(2)
PK6/PO30/TIOCA11
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PK6DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO30 output* TIOCA11 output* PK6 output* PK6 input* Valid when PCJKE = 1. PO30_OE 1 0 0 0 TPU TIOCA11_OE 1 0 0 I/O Port PK6DDR 1 0
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Section 13 I/O Ports
(3)
PK5/PO29/TIOCA10/TIOCB10
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PK5DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO29 output* TIOCB10 output* PK5 output* PK5 input* Valid when PCJKE = 1. PO29_OE 1 0 0 0 TPU TIOCB10_OE 1 0 0 I/O Port PK5DDR 1 0
(4)
PK4/PO28/TIOCA10
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PK4DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO28 output* TIOCA10 output* PK4 output* PK4 input* Valid when PCJKE = 1. PO28_OE 1 0 0 0 TPU TIOCA10_OE 1 0 0 I/O Port PK4DDR 1 0
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Section 13 I/O Ports
(5)
PK3/PO27/TIOCC9/TIOCD9
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PK3DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO27 output* TIOCD9 output* PK3 output* PK3 input* Valid when PCJKE = 1. PO27_OE 1 0 0 0 TPU TIOCD9_OE 1 0 0 I/O Port PK3DDR 1 0
(6)
PK2/PO26/TIOCC9
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PK2DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO26 output* TIOCC9 output* PK2 output* PK2 input* Valid when PCJKE = 1. PO26_OE 1 0 0 0 TPU TIOCC9_OE 1 0 0 I/O Port PK2DDR 1 0
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Section 13 I/O Ports
(7)
PK1/PO25/TIOCA9/TIOCB9
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PK1DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO25 output* TIOCB9 output* PK1 output* PK1 input* Valid when PCJKE = 1. PO25_OE 1 0 0 0 TPU TIOCB9_OE 1 0 0 I/O Port PK1DDR 1 0
(8)
PK0/PO24/TIOCA9
The pin function is switched as shown below according to the combination of register setting of PPG and TPU, setting of the port function control register (PFCR), and the PK0DDR bit settings.
Setting PPG Module Name PPG TPU I/O port Note: * Pin Function PO24 output* TIOCA9 output* PK0 output* PK0 input* Valid when PCJKE = 1. PO24_OE 1 0 0 0 TPU TIOCA9_OE 1 0 0 I/O Port PK0DDR 1 0
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Section 13 I/O Ports
13.2.14 Port M (1) PM4
The pin function is switched as shown below according to the combination of the USB register setting and the PM4DDR bit setting.
Setting USB Module Name USB I/O port Pin Function PM4 output PM4 input (initial value) PULLUP_E I/O Port PM4DDR -- 1 0
PULLUP control output 1 0 0
(2)
PM3
The pin function is switched as shown below according to the combination of the PM3DDR bit setting.
Setting I/O Port Module Name I/O port Pin Function PM3 output PM3 input (initial value) PM3DDR 1 0
(3)
PM2
The pin function is switched as shown below according to the combination of the PM2DDR bit setting.
Setting I/O Port Module Name I/O port Pin Function PM2 output PM2 input (initial value) PM2DDR 1 0
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Section 13 I/O Ports
(4)
PM1/RxD6
The pin function is switched as shown below according to the combination of the PM1DDR bit setting.
Setting I/O Port Module Name I/O port Pin Function PM1 output PM1 input (initial value) PM1DDR 1 0
(5)
PM0/TxD6
The pin function is switched as shown below according to the combination of the SCI register setting and PM0DDR bit setting.
Setting SCI Module Name SCI I/O port Pin Function TxD6 output PM0 output PM0 input (initial value) TxD6_OE 1 0 0 I/O Port PM0DDR -- 1 0
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Section 13 I/O Ports
Table 13.5 Available Output Signals and Settings in Each Port
Output Specification Signal Name 7 EDRAK1_OE SCL0_OE 6 EDACK1A_OE DACK1_OE Output Signal Name Signal Selection Register Settings
Port P1
Peripheral Module Settings SYSCR.EXPE = 1, EDMDR_1.EDRAKE = 1 ICCRA.ICE = 1 SYSCR.EXPE = 1, EDACR_1.AMS = 1, EDMDR_1.EDRAKE = 1 DMAC.DACR_1.AMS = 1, DMDR_1.DACKE = 1 ICCRA.ICE = 1 SYSCR.EXPE = 1, EDMDR_1.ETENDE = 1 DMDR_1.TENDE = 1 ICCRA.ICE = 1 SCR.TE = 1, IrCR.IrE = 0 SCR.TE = 1, IrCR.IrE = 1 ICCRA.ICE = 1 SYSCR.EXPE = 1, EDMDR_0.EDRAKE = 1 SYSCR.EXPE = 1, EDACR_0.AMS = 1, EDMDR_0.EDACKE = 1 DMAC.DACR_0.AMS = 1, DMDR_0.DACKE = 1 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE [1, 0] = 01 or while SMR.C/A = 1, SCR.CKE 1 = 0 SYSCR.EXPE = 1, EDMDR_0.ETENDE = 1 DMDR_0.TENDE = 1 SCR.TE = 1
EDRAK1 PFCR8.EDMAS1[A,B] = 00 SCL0 EDACK1 PFCR8.EDMAS1[A,B] = 00 DACK1
PFCR7.DMAS1[A,B] = 00
SDA0_OE 5 ETEND1A_OE TEND1_OE SCL1_OE 4 TxD5_OE IrTxD_OE SDA1_OE 3 2 EDRAK0_OE EDACK0A_OE DACK0_OE SCK2_OE
SDA0 ETEND1 PFCR8.EDMAS1[A,B] = 00 TEND1 SCL1 TxD5 IrTxD SDA1 EDRAK0 PFCR8.EDMAS0[A,B] = 00 EDACK0 PFCR8.EDMAS0[A,B] = 00 DACK0 SCK2 PFCR7.DMAS1[A,B] = 00
PFCR7.DMAS0[A,B] = 00
1
ETEND0A_OE TEND0_OE
ETEND0 PFCR8.EDMAS0[A,B] = 00 TEND0 TxD2 PFCR7.DMAS0[A,B] = 00
0
TxD2_OE
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Section 13 I/O Ports
Port P2 7
Output Specification Signal Name TIOCB5_OE
Output Signal Name TIOCB5
Signal Selection Register Settings
Peripheral Module Settings TPU.TIOR_5.IOB3 = 0, TPU.TIOR_5.IOB[1,0] = 01/10/11 NDERL.NDER7 = 1 TPU.TIOR_5.IOA3 = 0, TPU.TIOR_5.IOA[1,0] = 01/10/11 TMR.TCSR_1.TCSR.OS3,2 = 01/10/11 or TMR.TCSR_1.OS[1,0] = 01/10/11 SCR.TE = 1 NDERL.NDER6 = 1 TPU.TIOR_4.IOA3 = 0, TPU.TIOR_4.IOA[1,0] = 01/10/11 NDERL.NDER5 = 1 TPU.TIOR_4.IOB3 = 0, TPU.TIOR_4.IOB[1,0] = 01/10/11 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE [1, 0] = 01 or while SMR.C/A = 1, SCR.CKE 1 = 0 NDERL.NDER4 = 1 TPU.TMDR.BFB = 0, TPU.TIORL_3.IOD3 = 0, TPU.TIORL_3.IOD[1,0] = 01/10/11 NDERL.NDER3 = 1 TPU.TMDR.BFA = 0, TPU.TIORL_3.IOC3 = 0, TPU.TIORL_3.IOD[1,0] = 01/10/11 TMR.TCSR_0.OS[3,2] = 01/10/11 or TMR.TCSR_0.OS[1,0] = 01/10/11 SCR.TE = 1 NDERL.NDER2 = 1
PO7_OE 6 TIOCA5_OE
PO7 TIOCA5
TMO1_OE
TMO1
TxD1_OE PO6_OE 5 TIOCA4_OE
TxD1 PO6 TIOCA4
PO5_OE 4 TIOCB4_OE
PO5 TIOCB4
SCK1_OE
SCK1
PO4_OE 3 TIOCD3_OE
PO4 TIOCD3
PO3_OE 2 TIOCC3_OE
PO3 TIOCC3
TMO0_OE
TMO0
TxD0_OE PO2_OE
TxD0 PO2
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Section 13 I/O Ports
Port P2 1
Output Specification Signal Name TIOCA3_OE
Output Signal Name TIOCA3
Signal Selection Register Settings
Peripheral Module Settings TPU.TIORH_3.IOA3 = 0, TPU.TIORH_3.IOA[1,0] = 01/10/11 NDERL.NDER1 = 1 TPU.TIORH_3.IOB3=0, TPU.TIORH_3.IOB[1,0] = 01/10/11 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE [1, 0] = 01 or while SMR.C/A = 1, SCR.CKE 1 = 0 NDERL.NDER0 = 1 SYSCR.EXPE = 1, EDACR_1.AMS = 1, EDMDR_1.EDACKE = 1 DMAC.DACR_3.AMS = 1, DMDR_3.DACKE = 1 TMR.TCSR_3.OS[3,2] = 01/10/11 or TMR.TCSR_3.OS[1,0] = 01/10/11 SYSCR.EXPE = 1, EDMDR_1.ETENDE = 1 DMDR_3.TENDE = 1 SYSCR.EXPE = 1, EDACR_0.AMS = 1, EDMDR_0.EDACKE = 1 DMAC.DACR_2.AMS = 1, DMDR_2.DACKE = 1 TMR.TCSR_2.OS[3,2] = 01/10/11 or TMR.TCSR_2.OS[1,0] = 01/10/11 When SCMR.SMIF = 1: SCR.TE = 1 or SCR.RE = 1 while SMR.GM = 0, SCR.CKE [1, 0] = 01 or while SMR.GM = 1 When SCMR.SMIF = 0: SCR.TE = 1 or SCR.RE = 1 while SMR.C/A = 0, SCR.CKE [1, 0] = 01 or while SMR.C/A = 1, SCR.CKE 1 = 0
PO1_OE 0 TIOCB3_OE
PO1 TIOCB3
SCK0_OE
SCK0
PO0_OE P6 5 EDACK1B_OE DACK3_OE
PO0 EDACK1 PFCR8.EDMAS1[A,B] = 01 DACK3
PFCR7.DMAS3[A,B] = 01
TMO3_OE ETEND1B_OE TEND3_OE 2 EDACK0B_OE DACK2_OE
TMO3 ETEND1 PFCR8.EDMAS1[A,B] = 01 TEND3 PFCR7.DMAS3[A,B] = 01
4
EDACK0 PFCR8.EDMAS0[A,B] = 01 DACK2
PFCR7.DMAS2[A,B] = 01
TMO2_OE
TMO2
SCK4_OE
SCK4
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Section 13 I/O Ports
Port P6 1
Output Specification Signal Name ETEND0B_OE TEND2_OE 0 TxD4_OE B_OE AH_OE BSB_OE AS_OE 5 4 RD_OE LUB_OE LHWR_OE 3 LLB_OE LLWR_OE 1 BACK_OE (RD/WR)_OE BSA_OE BREQO_OE CS3_OE CS7A_OE 2 CS2A_OE CS6A_OE 1 CS1_OE CS2B_OE CS5A_OE CS6B_OE CS7B_OE 0 CS0_OE CS4_OE CS5B_OE
Output Signal Name
Signal Selection Register Settings
Peripheral Module Settings SYSCR.EXPE = 1, EDMDR_0.ETENDE = 1 DMDR_2.TENDE = 1 SCR.TE = 1 PADDR.PA7DDR = 1, SCKCR.PSTOP1 = 0 SYSCR.EXPE = 1, MPXCR.MPXEn (n = 7 to 3) = 1
ETEND0 PFCR8.EDMAS0[A,B] = 01 TEND2 TxD4 B AH BS AS RD LUB LHWR LLB LLWR BACK RD/WR BS BREQO CS3 CS7 CS2 CS6 CS1 CS2 CS5 CS6 CS7 CS0 CS4 CS5 PFCR1.CS5S[A,B] = 01 PFCR2.CS2S = 1 PFCR1.CS5S[A,B] = 00 PFCR1.CS6S[A,B] = 01 PFCR1.CS7S[A,B] = 01 PFCR1.CS7S[A,B] = 00 PFCR2.CS2S = 0 PFCR1.CS6S[A,B] = 00 PFCR7.DMAS2[A,B] = 01
PA
7 6
PFCR2.BSS = 1
SYSCR.EXPE = 1, PFCR2.BSE = 1 SYSCR.EXPE = 1, PFCR2.ASOE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1, PFCR6.LHWROE = 1 or SRAMCR.BCSELn = 1 SYSCR.EXPE = 1, PFCR6.LHWROE = 1 SYSCR.EXPE = 1, SRAMCR.BCSELn = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1,BCR1.BRLE = 1 SYSCR.EXPE = 1, PFCR2.RDWRE = 1 or SRAMCR.BCSELn = 1
0
PFCR2.BSS = 0
SYSCR.EXPE = 1, PFCR2.BSE = 1 SYSCR.EXPE = 1, BCR1.BRLE = 1, BCR1.BREQOE = 1 SYSCR.EXPE = 1, PFCR0.CS3E = 1 SYSCR.EXPE = 1, PFCR0.CS7E = 1 SYSCR.EXPE = 1, PFCR0.CS2E = 1 SYSCR.EXPE = 1, PFCR0.CS6E = 1 SYSCR.EXPE = 1, PFCR0.CS1E = 1 SYSCR.EXPE = 1, PFCR0.CS2E = 1 SYSCR.EXPE = 1, PFCR0.CS5E = 1 SYSCR.EXPE = 1, PFCR0.CS6E = 1 SYSCR.EXPE = 1, PFCR0.CS7E = 1 SYSCR.EXPE = 1, PFCR0.CS0E = 1 SYSCR.EXPE = 1, PFCR0.CS4E = 1 SYSCR.EXPE = 1, PFCR0.CS5E = 1
PB
3
Rev. 2.00 Sep. 25, 2008 Page 553 of 1340 REJ09B0413-0200
Section 13 I/O Ports
Port PD 7 6 5 4 3 2 1 0 PE 7 6 5 4 3 2 1 0 PF 4 3 2 1 0 PH 7 6 5 4 3 2 1 0
Output Specification Signal Name A7_OE A6_OE A5_OE A4_OE A3_OE A2_OE A1_OE A0_OE A15_OE A14_OE A13_OE A12_OE A11_OE A10_OE A9_OE A8_OE A20_OE A19_OE A18_OE A17_OE A16_OE D7_E D6_E D5_E D4_E D3_E D2_E D1_E D0_E
Output Signal Name A7 A6 A5 A4 A3 A2 A1 A0 A15 A14 A13 A12 A11 A10 A9 A8 A20 A19 A18 A17 A16 D7 D6 D5 D4 D3 D2 D1 D0
Signal Selection Register Settings
Peripheral Module Settings SYSCR.EXPE = 1, PDDDR.PD7DDR = 1 SYSCR.EXPE = 1, PDDDR.PD6DDR = 1 SYSCR.EXPE = 1, PDDDR.PD5DDR = 1 SYSCR.EXPE = 1, PDDDR.PD4DDR = 1 SYSCR.EXPE = 1, PDDDR.PD3DDR = 1 SYSCR.EXPE = 1, PDDDR.PD2DDR = 1 SYSCR.EXPE = 1, PDDDR.PD1DDR = 1 SYSCR.EXPE = 1, PDDDR.PD0DDR = 1 SYSCR.EXPE = 1, PEDDR.PE7DDR = 1 SYSCR.EXPE = 1, PEDDR.PE6DDR = 1 SYSCR.EXPE = 1, PEDR.PE5DDR = 1 SYSCR.EXPE = 1, PEDDR.PE4DDR = 1 SYSCR.EXPE = 1, PEDDR.PE3DDR = 1 SYSCR.EXPE = 1, PEDDR.PE2DDR = 1 SYSCR.EXPE = 1, PEDDR.PE1DDR = 1 SYSCR.EXPE = 1, PEDDR.PE0DDR = 1 SYSCR.EXPE = 1, PFCR4.A20E = 1 SYSCR.EXPE = 1, PFCR4.A19E = 1 SYSCR.EXPE = 1, PFCR4.A18E = 1 SYSCR.EXPE = 1, PFCR4.A17E = 1 SYSCR.EXPE = 1, PFCR4.A16E = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1 SYSCR.EXPE = 1
Rev. 2.00 Sep. 25, 2008 Page 554 of 1340 REJ09B0413-0200
Section 13 I/O Ports
Port PI 7 6 5 4 3 2 1 0 PJ 7
Output Specification Signal Name D15_E D14_E D13_E D12_E D11_E D10_E D9_E D8_E TIOCB8_OE
Output Signal Name D15 D14 D13 D12 D11 D10 D9 D8 TIOCB8
Signal Selection Register Settings
Peripheral Module Settings SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 SYSCR.EXPE = 1, ABWCR.ABW[H,L]n = 01 TPU.TIOR_8.IOB3 = 0, TPU.TIOR_8.IOB[1,0] = 01/10/11 NDERL_1.NDER23 = 1 TPU.TIOR_8.IOA3 = 0, TPU.TIOR_8.IOA[1,0] = 01/10/11 NDERL_1.NDER22 = 1 TPU.TIOR_7.IOB3 = 0, TPU.TIOR_7.IOB[1,0] = 01/10/11 NDERL_1.NDER21 = 1 TPU.TIOR_7.IOA3 = 0, TPU.TIOR_7.IOA[1,0] = 01/10/11 NDERL_1.NDER20 = 1 TPU.TMDR_6.BFB = 0, TPU.TIORL_6.IOD3 =0, TPU.TIORL_6.IOD[1,0] = 01/10/11 NDERL_1.NDER19 = 1 TPU.TMDR_6.BFA = 0, TPU.TIORL_6.IOC3 = 0, TPU.TIORL_6.IOC[1,0] = 01/10/11 NDERL_1.NDER18 = 1 TPU.TIORH_6.IOB3 = 0, TPU.TIORH_6.IOB[1,0] = 01/10/11 NDERL_1.NDER17 = 1 TPU.TIORH_6.IOA3 = 0, TPU.TIORH_6.IOA[1,0] = 01/10/11 NDERL_1.NDER16 = 1
PO 23_OE 6 TIOCA8_OE
PO23 TIOCA8
PO 22_OE 5 TIOCB7_OE
PO22 TIOCB7
PO 21_OE 4 TIOCA7_OE
PO21 TIOCA7
PO 20_OE 3 TIOCD6_OE
PO20 TIOCD6
PO 19_OE 2 TIOCC6_OE
PO19 TIOCC6
PO 18_OE 1 TIOCB6_OE
PO18 TIOCB6
PO 17_OE 0 TIOCA6_OE
PO17 TIOCA6
PO 16_OE
PO16
Rev. 2.00 Sep. 25, 2008 Page 555 of 1340 REJ09B0413-0200
Section 13 I/O Ports
Port PK 7
Output Specification Signal Name TIOCB11_OE
Output Signal Name TIOCB11
Signal Selection Register Settings
Peripheral Module Settings TPU.TIOR_11.IOB3 = 0, TPU.TIOR_11.IOB[1,0] = 01/10/11 NDERH_1.NDER31 = 1 TPU.TIOR_11.IOA3 = 0, TPU.TIOR_11.IOA[1,0] = 01/10/11 NDERH_1.NDER30 = 1 TPU.TIOR_10.IOB3 = 0, TPU.TIOR_10.IOB[1,0] = 01/10/11 NDERH_1.NDER29 = 1 TPU.TIOR_10.IOA3 = 0, TPU.TIOR_10.IOA[1,0] = 01/10/11 NDERH_1.NDER28 = 1 TPU.TMDR_9.BFB = 0, TPU.TIORL_9.IOD3 = 0, TPU.TIORL_9.IOD[1,0] = 01/10/11 NDERH_1.NDER27 = 1 TPU.TMDR_9.BFA = 0, TPU.TIORL_9.IOC3 = 0, TPU.TIORL_9.IOC[1,0] = 01/10/11 NDERH_1.NDER26 = 1 TPU.TIORH_9.IOB3 = 0, TPU.TIORH_9.IOB[1,0] = 01/10/11 NDERH_1.NDER25 = 1 TPU.TIORH_9.IOA3 = 0, TPU.TIORH_9.IOA[1,0] = 01/10/11 NDERH_1.NDER24 = 1
PO31_OE 6 TIOCA11_OE
PO31 TIOCA11
PO30_OE 5 TIOCB10_OE
PO30 TIOCB10
PO29_OE 4 TIOCA10_OE
PO29 TIOCA10
PO28_OE 3 TIOCD9_OE
PO28 TIOCD9
PO27_OE 2 TIOCC9_OE
PO27 TIOCC9
PO26_OE 1 TIOCB9_OE
PO26 TIOCB9
PO25_OE 0 TIOCA9_OE
PO25 TIOCA9
PO24_OE
PO24
Rev. 2.00 Sep. 25, 2008 Page 556 of 1340 REJ09B0413-0200
Section 13 I/O Ports
13.3
Port Function Controller
The port function controller controls the I/O ports. The port function controller incorporates the following registers. * * * * * * * * * * * * Port function control register 0 (PFCR0) Port function control register 1 (PFCR1) Port function control register 2 (PFCR2) Port function control register 4 (PFCR4) Port function control register 6 (PFCR6) Port function control register 7 (PFCR7) Port function control register 8 (PFCR8) Port function control register 9 (PFCR9) Port function control register A (PFCRA) Port function control register B (PFCRB) Port function control register C (PFCRC) Port function control register D (PFCRD)
Rev. 2.00 Sep. 25, 2008 Page 557 of 1340 REJ09B0413-0200
Section 13 I/O Ports
13.3.1
Port Function Control Register 0 (PFCR0)
PFCR0 enables/disables the CS output.
Bit Bit Name Initial Value R/W 7 CS7E 0 R/W 6 CS6E 0 R/W 5 CS5E 0 R/W 4 CS4E 0 R/W 3 CS3E 0 R/W 2 CS2E 0 R/W 1 CS1E 0 R/W 0 CS0E Undefined* R/W
Note: * 1 in external extended mode; 0 in other modes.
Bit 7 6 5 4 3 2 1 0 Note: *
Bit Name CS7E CS6E CS5E CS4E CS3E CS2E CS1E CS0E
Initial Value 0 0 0 0 0 0 0 Undefined*
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description CS7 to CS0 Enable These bits enable/disable the corresponding CSn output. 0: Pin functions as I/O port 1: Pin functions as CSn output pin (n = 7 to 0)
1 in external extended mode, 0 in other modes.
Rev. 2.00 Sep. 25, 2008 Page 558 of 1340 REJ09B0413-0200
Section 13 I/O Ports
13.3.2
Port Function Control Register 1 (PFCR1)
PFCR1 selects the CS output pins.
Bit Bit Name Initial Value R/W 7 CS7SA 0 R/W 6 CS7SB 0 R/W 5 CS6SA 0 R/W 4 CS6SB 0 R/W 3 CS5SA 0 R/W 2 CS5SB 0 R/W 1 CS4SA 0 R/W 0 CS4SB 0 R/W
Bit 7 6
Bit Name CS7SA* CS7SB*
Initial Value 0 0
R/W R/W R/W
Description CS7 Output Pin Select Selects the output pin for CS7 when CS7 output is enabled (CS7E = 1) 00: Specifies pin PB3 as CS7-A output 01: Specifies pin PB1 as CS7-B output 10: Setting prohibited 11: Setting prohibited
5 4
CS6SA* CS6SB*
0 0
R/W R/W
CS6 Output Pin Select Selects the output pin for CS6 when CS6 output is enabled (CS6E = 1) 00: Specifies pin PB2 as CS6-A output 01: Specifies pin PB1 as CS6-B output 10: Setting prohibited 11: Setting prohibited
3 2
CS5SA* CS5SB*
0 0
R/W R/W
CS5 Output Pin Select Selects the output pin for CS5 when CS5 output is enabled (CS5E = 1) 00: Specifies pin PB1 as CS5-A output 01: Specifies pin PB0 as CS5-B output 10: Setting prohibited 11: Setting prohibited
Rev. 2.00 Sep. 25, 2008 Page 559 of 1340 REJ09B0413-0200
Section 13 I/O Ports
Bit 1 0
Bit Name CS4SA* CS4SB*
Initial Value 0 0
R/W R/W R/W
Description CS4 Output Pin Select Selects the output pin for CS4 when CS4 output is enabled (CS4E = 1) 00: Specifies pin PB0 as CS4-A output 01: Setting prohibited 10: Setting prohibited 11: Setting prohibited
Note:
*
If multiple CS outputs are specified to a single pin according to the CSn output pin select bits (n = 4 to 7), multiple CS signals are output from the pin. For details, see section 9.5.3, Chip Select Signals.
13.3.3
Port Function Control Register 2 (PFCR2)
PFCR2 selects the CS output pin, enables/disables bus control I/O, and selects the bus control I/O pins.
Bit Bit Name Initial Value R/W 7 0 R 6 CS2S 0 R/W 5 BSS 0 R/W 4 BSE 0 R/W 3 0 R 2 RDWRE 0 R/W 1 ASOE 1 R/W 0 0 R
Bit 7
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
6
CS2S*1
0
R/W
CS2 Output Pin Select Selects the output pin for CS2 when CS2 output is enabled (CS2E = 1) 0: Specifies pin PB2 as CS2-A output pin 1: Specifies pin PB1 as CS2-B output pin
Rev. 2.00 Sep. 25, 2008 Page 560 of 1340 REJ09B0413-0200
Section 13 I/O Ports
Bit 5
Bit Name BSS
Initial Value 0
R/W R/W
Description BS Output Pin Select Selects the BS output pin 0: Specifies pin PA0 as BS-A output pin 1: Specifies pin PA6 as BS-B output pin
4
BSE
0
R/W
BS Output Enable Enables/disables the BS output 0: Disables the BS output 1: Enables the BS output
3
0
R
Reserved This bit is always read as 0. The write value should always be 0.
2
RDWRE*2
0
R/W
RD/WR Output Enable Enables/disables the RD/WR output 0: Disables the RD/WR output 1: Enables the RD/WR output
1
ASOE
1
R/W
AS Output Enable Enables/disables the AS output 0: Specifies pin PA6 as I/O port 1: Specifies pin PA6 as AS output pin
0
0
R
Reserved This bit is always read as 0. The write value should always be 0.
Notes: 1. If multiple CS outputs are specified to a single pin according to the CSn output pin select bit (n = 2), multiple CS signals are output from the pin. For details, see section 9.5.3, Chip Select Signals. 2. If an area is specified as a byte control SDRAM space, the pin functions as RD/WR output regardless of the RDWRE bit value.
Rev. 2.00 Sep. 25, 2008 Page 561 of 1340 REJ09B0413-0200
Section 13 I/O Ports
13.3.4
Port Function Control Register 4 (PFCR4)
PFCR4 enables/disables the address output.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 A20E 0/1* R/W 3 A19E 0/1* R/W 2 A18E 0/1* R/W 1 A17E 0/1* R/W 0 A16E 0/1* R/W
Bit 7 to 5
Bit Name
Initial Value 0
R/W R
Description Reserved This bit is always read as 0. The write value should always be 0.
4
A20E
0/1*
R/W
Address A20 Enable Enables/disables the address output (A20) 0: Disables the A20 output 1: Enables the A20 output
3
A19E
0/1*
R/W
Address A19 Enable Enables/disables the address output (A19) 0: Disables the A19 output 1: Enables the A19 output
2
A18E
0/1*
R/W
Address A18 Enable Enables/disables the address output (A18) 0: Disables the A18 output 1: Enables the A18 output
1
A17E
0/1*
R/W
Address A17 Enable Enables/disables the address output (A17) 0: Disables the A17 output 1: Enables the A17 output
0
A16E
0/1*
R/W
Address A16 Enable Enables/disables the address output (A16) 0: Disables the A16 output 1: Enables the A16 output
Note:
*
Initial value is switched according to operating mode. 1 when on-chip ROM disabled, 0 when enabled.
Rev. 2.00 Sep. 25, 2008 Page 562 of 1340 REJ09B0413-0200
Section 13 I/O Ports
13.3.5
Port Function Control Register 6 (PFCR6)
PFCR6 selects the TPU clock input pin.
Bit Bit Name Initial Value R/W 7 1 R/W 6 LHWROE 1 R/W 5 1 R/W 4 0 R 3 TCLKS 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Bit 7
Bit Name
Initial Value 1
R/W R/W
Description Reserved This bit is always read as 1. The write value should always be 1.
6
LHWROE
1
R/W
LHWR Output Enable Enables/disables LHWR output (valid in external extended mode). 0: Specifies pin PA4 as I/O port 1: Specifies pin PA4 as LHWR output pin
5
1
R/W
Reserved This bit is always read as 1. The write value should always be 1.
4 3
TCLKS
0 0
R R/W
Reserved This is a read-only bit and cannot be modified. TPU External Clock Input Pin Select Selects the TPU external clock input pins. 0: The TPU external clock input pins cannot be used. 1: Specifies pins P14 to P17 as external clock input pins.
2 to 0
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 25, 2008 Page 563 of 1340 REJ09B0413-0200
Section 13 I/O Ports
13.3.6
Port Function Control Register 7 (PFCR7)
PFCR7 selects the DMAC I/O pins (DREQ, DACK, and TEND).
Bit Bit Name Initial Value R/W 7 DMAS3A 0 R/W 6 DMAS3B 0 R/W 5 DMAS2A 0 R/W 4 DMAS2B 0 R/W 3 DMAS1A 0 R/W 2 DMAS1B 0 R/W 1 DMAS0A 0 R/W 0 DMAS0B 0 R/W
Bit 7 6
Bit Name DMAS3A DMAS3B
Initial Value 0 0
R/W R/W R/W
Description DMAC Control Pin Select Selects the I/O port to control DMAC_3. 00: Setting prohibited 01: Specifies pins P63 to P65 as DMAC control pins 10: Setting prohibited 11: Setting prohibited
5 4
DMAS2A DMAS2B
0 0
R/W R/W
DMAC Control Pin Select Selects the I/O port to control DMAC_2. 00: Setting prohibited 01: Specifies pins P60 to P62 as DMAC control pins 10: Setting prohibited 11: Setting prohibited
3 2
DMAS1A DMAS1B
0 0
R/W R/W
DMAC Control Pin Select Selects the I/O port to control DMAC_1. 00: Specifies pins P14 to P16 as DMAC control pins 01: Setting prohibited 10: Setting prohibited 11: Setting prohibited
1 0
DMAS0A DMAS0B
0 0
R/W R/W
DMAC Control Pin Select Selects the I/O port to control DMAC_0. 00: Specifies pins P10 to P12 as DMAC control pins 01: Setting prohibited 10: Setting prohibited 11: Setting prohibited
Rev. 2.00 Sep. 25, 2008 Page 564 of 1340 REJ09B0413-0200
Section 13 I/O Ports
13.3.7
Port Function Control Register 8 (PFCR8)
PFCR8 selects the EXDMAC I/O pins (EDREQ, EDACK, ETEND, and EDRAK).
Bit Bit Name Initial Value R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 EDMAS1A 0 R/W 2 EDMAS1B 0 R/W 1 EDMAS0A 0 R/W 0 EDMAS0B 0 R/W
Bit 7 to 4 3 2
Bit Name
Initial Value 0
R/W R/W R/W R/W
Description Reserved bit The write value should always be 0. EXDMAC Control Pin Select Selects the I/O port to control EXDMAC_1. 00: Specifies pins P14 to P17 as EXDMAC control pins 01: Specifies pins P63 to P65 as EXDMAC control pins 10: Setting prohibited 11: Setting prohibited
EDMAS1A 0 EDMAS1B 0
1 0
EDMAS0A 0 EDMAS0B 0
R/W R/W
EXDMAC Control Pin Select Selects the I/O port to control EXDMAC_0. 00: Specifies pins P10 to P13 as EXDMAC control pins 01: Specifies pins P60 to P62 as EXDMAC control pins 10: Setting prohibited 11: Setting prohibited
Rev. 2.00 Sep. 25, 2008 Page 565 of 1340 REJ09B0413-0200
Section 13 I/O Ports
13.3.8
Port Function Control Register 9 (PFCR9)
PFCR9 selects the multiple functions for the TPU I/O pins.
Bit Bit Name Initial Value R/W 7 TPUMS5 0 R/W 6 TPUMS4 0 R/W 5 TPUMS3A 0 R/W 4 TPUMS3B 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Bit 7
Bit Name TPUMS5
Initial Value 0
R/W R/W
Description TPU I/O Pin Multiplex Function Select Selects TIOCA5 function. 0: Specifies pin P26 as output compare output and input capture 1: Specifies P27 as input capture input and P26 as output compare
6
TPUMS4
0
R/W
TPU I/O Pin Multiplex Function Select Selects TIOCA4 function. 0: Specifies P25 as output compare output and input capture 1: Specifies P24 as input capture input and P25 as output compare
5
TPUMS3A 0
R/W
TPU I/O Pin Multiplex Function Select Selects TIOCA3 function. 0: Specifies P21 as output compare output and input capture 1: Specifies P20 as input capture input and P21 as output compare
4
TPUMS3B 0
R/W
TPU I/O Pin Multiplex Function Select Selects TIOCC3 function. 0: Specifies P22 as output compare output and input capture 1: Specifies P23 as input capture input and P22 as output compare
3 to 0
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
Rev. 2.00 Sep. 25, 2008 Page 566 of 1340 REJ09B0413-0200
Section 13 I/O Ports
13.3.9
Port Function Control Register A (PFCRA)
PFCRA selects the multiple functions for the TPU I/O pins.
Bit Bit Name Initial Value R/W 7 TPUMS11 0 R/W 6 TPUMS10 0 R/W 5 TPUMS9A 0 R/W 4 TPUMS9B 0 R/W 3 TPUMS8 0 R/W 2 TPUMS7 0 R/W 1 TPUMS6A 0 R/W 0 TPUM6B 0 R/W
Bit 7
Bit Name TPUMS11
Initial Value 0
R/W R/W
Description TPU I/O Pin Multiplex Function Select Selects TIOCA11 function. 0: Specifies pin PK6 as output compare output and input capture 1: Specifies PK7 as input capture input and PK6 as output compare
6
TPUMS10
0
R/W
TPU I/O Pin Multiplex Function Select Selects TIOCA10 function. 0: Specifies PK4 as output compare output and input capture 1: Specifies PK5 as input capture input and PK4 as output compare
5
TPUMS9A
0
R/W
TPU I/O Pin Multiplex Function Select Selects TIOCA9 function. 0: Specifies PK0 as output compare output and input capture 1: Specifies PK1 as input capture input and PK0 as output compare
4
TPUMS9B
0
R/W
TPU I/O Pin Multiplex Function Select Selects TIOCC9 function. 0: Specifies PK2 as output compare output and input capture 1: Specifies PK3 as input capture input and PK2 as output compare
Rev. 2.00 Sep. 25, 2008 Page 567 of 1340 REJ09B0413-0200
Section 13 I/O Ports
Bit 3
Bit Name TPUMS8
Initial Value 0
R/W R/W
Description TPU I/O Pin Multiplex Function Select Selects TIOCA8 function. 0: Specifies PK6 as output compare output and input capture 1: Specifies PK7 as input capture input and PK6 as output compare
2
TPUMS7
0
R/W
TPU I/O Pin Multiplex Function Select Selects TIOCA7 function. 0: Specifies PJ4 as output compare output and input capture 1: Specifies PJ5 as input capture input and PJ4 as output compare
1
TPUMS6A 0
R/W
TPU I/O Pin Multiplex Function Select Selects TIOCA6 function. 0: Specifies PJ0 as output compare output and input capture 1: Specifies PJ1 as input capture input and PJ0 as output compare
0
TPUMS6B 0
R/W
TPU I/O Pin Multiplex Function Select Selects TIOCC6 function. 0: Specifies PJ2 as output compare output and input capture 1: Specifies PJ3 as input capture input and PJ2 as output compare
Rev. 2.00 Sep. 25, 2008 Page 568 of 1340 REJ09B0413-0200
Section 13 I/O Ports
13.3.10 Port Function Control Register B (PFCRB) PFCRB selects LVD interrupt* and the input pins for IRQ11 to IRQ8.
Bit Bit Name Initial Value R/W 7 0 R/W 6 ITS14* 0 R/W 5 0 R/W 4 0 R/W 3 ITS11 0 R/W 2 ITS10 0 R/W 1 ITS9 0 R/W 0 ITS8 0 R/W
Note: * Supported only by the H8SX/1658M Group.
* H8SX/1658R Group
Bit 7 to 4 Bit Name Initial Value All 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0.
* H8SX/1658M Group
Bit 7 Bit Name Initial Value 0 R/W R/W Description Reserved These bits are always read as 0. The write value should always be 0. 6 ITS14 0 R/W LVD Interrupt Select Enables/Disables the LVD interrupt select. 0: Disables the LVD interrupt 1: Enables the LVD interrupt 5 to 4 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 3 ITS11 0 R/W IRQ11 Pin Select Selects an input pin for IRQ11. 0: Selects pin P23 as IRQ11-A input 1: Selects pin P63 as IRQ11-B input
Rev. 2.00 Sep. 25, 2008 Page 569 of 1340 REJ09B0413-0200
Section 13 I/O Ports
Bit 2
Bit Name ITS10
Initial Value 0
R/W R/W
Description IRQ10 Pin Select Selects an input pin for IRQ10. 0: Selects pin P22 as IRQ10-A input 1: Selects pin P62 as IRQ10-B input
1
ITS9
0
R/W
IRQ9 Pin Select Selects an input pin for IRQ9. 0: Selects pin P21 as IRQ9-A input 1: Selects pin P61 as IRQ9-B input
0
ITS8
0
R/W
IRQ8 Pin Select Selects an input pin for IRQ8. 0: Selects pin P20 as IRQ8-A input 1: Selects pin P60 as IRQ8-B input
Rev. 2.00 Sep. 25, 2008 Page 570 of 1340 REJ09B0413-0200
Section 13 I/O Ports
13.3.11 Port Function Control Register C (PFCRC) PFCRC selects input pins for IRQ7 to IRQ0.
Bit Bit Name Initial Value R/W 7 ITS7 0 R/W 6 ITS6 0 R/W 5 ITS5 0 R/W 4 ITS4 0 R/W 3 ITS3 0 R/W 2 ITS2 0 R/W 1 ITS1 0 R/W 0 ITS0 0 R/W
Bit 7
Bit Name ITS7
Initial Value 0
R/W R/W
Description IRQ7 Pin Select Selects an input pin for IRQ7. 0: Selects pin P17 as IRQ7-A input 1: Selects pin P57 as IRQ7-B input
6
ITS6
0
R/W
IRQ6 Pin Select Selects an input pin for IRQ6. 0: Selects pin P16 as IRQ6-A input 1: Selects pin P56 as IRQ6-B input
5
ITS5
0
R/W
IRQ5 Pin Select Selects an input pin for IRQ5. 0: Selects pin P15 as IRQ5-A input 1: Selects pin P55 as IRQ5-B input
4
ITS4
0
R/W
IRQ4 Pin Select Selects an input pin for IRQ4. 0: Selects pin P14 as IRQ4-A input 1: Selects pin P54 as IRQ4-B input
3
ITS3
0
R/W
IRQ3 Pin Select Selects an input pin for IRQ3. 0: Selects pin P13 as IRQ3-A input 1: Selects pin P53 as IRQ3-B input
Rev. 2.00 Sep. 25, 2008 Page 571 of 1340 REJ09B0413-0200
Section 13 I/O Ports
Bit 2
Bit Name ITS2
Initial Value 0
R/W R/W
Description IRQ2 Pin Select Selects an input pin for IRQ2. 0: Selects pin P12 as IRQ2-A input 1: Selects pin P52 as IRQ2-B input
1
ITS1
0
R/W
IRQ1 Pin Select Selects an input pin for IRQ1. 0: Selects pin P11 as IRQ1-A input 1: Selects pin P51 as IRQ1-B input
0
ITS0
0
R/W
IRQ0 Pin Select Selects an input pin for IRQ0. 0: Selects pin P10 as IRQ0-A input 1: Selects pin P50 as IRQ0-B input
13.3.12 Port Function Control Register D (PFCRD) PFCRD enables/disables the pin functions of ports J and K.
Bit Bit Name Initial Value R/W 7 PCJKE* 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W
Bit 7
Bit Name PCJKE*
Initial Value 0
R/W R/W
Description Ports J and K Enable Enables/disables ports J and K. 0: Ports J and K are disabled 1: Ports J and K are enabled
6 to 0
0
R/W
Reserved These bits are always read as 0 and cannot be modified. The initial values should not be changed.
Note:
*
This bit is valid during single-chip mode. The initial value should not be changed except for the single-chip mode.
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Section 13 I/O Ports
13.4
13.4.1
Usage Notes
Notes on Input Buffer Control Register (ICR) Setting
1. When the ICR setting is changed, the LSI may malfunction due to an edge occurred internally according to the pin state. Before changing the ICR setting, fix the pin state high or disable the input function corresponding to the pin by the on-chip peripheral module settings. 2. If an input is enabled by setting ICR while multiple input functions are assigned to the pin, the pin state is reflected in all the inputs. Care must be taken for each module settings for unused input functions. 3. When a pin is used as an output, data to be output from the pin will be latched as the pin state if the input function corresponding to the pin is enabled. To use the pin as an output, disable the input function for the pin by setting ICR. 13.4.2 Notes on Port Function Control Register (PFCR) Settings
1. Port function controller controls the I/O port. Before enabling a port function, select the input/output destination. 2. When changing input pins, this LSI may malfunction due to the internal edge generated by the pin level difference before and after the change. * To change input pins, the following procedure must be performed. A. Disable the input function by the corresponding on-chip peripheral module settings B. Select another input pin by PFCR C. Enable its input function by the corresponding on-chip peripheral module settings 3. If a pin function has both a select bit that modifies the input/output destination and an enable bit that enables the pin function, first specify the input/output destination by the selection bit and then enable the pin function by the enable bit. 4. Modifying the PCJKE bit should be done in the initial setting right after activation. Set other bits after setting the PCJKE bit. 5. Do not change the PCJKE bit setting once it is set.
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Section 13 I/O Ports
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Section 14 16-Bit Timer Pulse Unit (TPU)
Section 14 16-Bit Timer Pulse Unit (TPU)
This LSI has two on-chip 16-bit timer pulse units (TPU), unit 0 and unit 1, and each comprises six channels. Therefore, this LSI includes twelve channels. Functions of unit 0 and unit 1 are shown in table 14.1 and table 14.2 respectively. Block diagrams of unit 0 and unit 1 are shown in figure 14.1 and figure 14.2 respectively. This section explains unit 0. This explanation is common to unit 1.
14.1
Features
* Maximum 16-pulse input/output * Selection of eight counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match Input capture function Counter clear operation Synchronous operations: * Multiple timer counters (TCNT) can be written to simultaneously * Simultaneous clearing by compare match and input capture possible * Simultaneous input/output for registers possible by counter synchronous operation * Maximum of 15-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channels 0 and 3 * Phase counting mode settable independently for each of channels 1, 2, 4, and 5 * Cascaded operation * Fast access via internal 16-bit bus * 26 interrupt sources * Automatic transfer of register data * Programmable pulse generator (PPG) output trigger can be generated (unit 0 only) * Conversion start trigger for the A/D converter can be generated (unit 0 only) * Module stop state can be set
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.1 TPU (Unit 0) Functions
Item Count clock Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 P/1 P/4 P/16 P/64 TCLKA TCLKB TCLKC TCLKD TGRA_0 TGRB_0 TGRC_0 TGRD_0 P/1 P/4 P/16 P/64 P/256 TCLKA TCLKB TGRA_1 TGRB_1 P/1 P/4 P/16 P/64 P/1024 TCLKA TCLKB TCLKC TGRA_2 TGRB_2 P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 TCLKA TGRA_3 TGRB_3 TGRC_3 TGRD_3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TGR compare match or input capture O O O O O O O TGR compare match or input capture P/1 P/4 P/16 P/64 P/1024 TCLKA TCLKC TGRA_4 TGRB_4 TIOCA4 TIOCB4 P/1 P/4 P/16 P/64 P/256 TCLKA TCLKC TCLKD TGRA_5 TGRB_5 TIOCA5 TIOCB5
General registers (TGR) General registers/ buffer registers I/O pins
Counter clear function TGR compare match or input capture Compare 0 output match 1 output output Toggle output
TGR compare match or input capture O O O O TGR compare match or input capture
TGR compare match
TGR compare match or input capture O O O O O O O TGR compare match or input capture
TGR compare match or input capture O O O O O O O TGR compare match or input capture
O O O TGR compare match
Input capture function O Synchronous operation PWM mode O O
Phase counting mode Buffer operation DTC activation O TGR compare match or input capture
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Section 14 16-Bit Timer Pulse Unit (TPU)
Item DMAC activation
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 TGRA_0 compare match or input capture TGRA_0 compare match or input capture TGRA_0/ TGRB_0 compare match or input capture 5 sources Compare match or input capture 0A Compare match or input capture 0B TGRA_1 compare match or input capture TGRA_1 compare match or input capture TGRA_1/ TGRB_1 compare match or input capture 4 sources Compare match or input capture 1A TGRA_2 compare match TGRA_3 compare match or input capture TGRA_3 compare match or input capture TGRA_3/ TGRB_3 compare match or input capture 5 sources Compare match or input capture 3A Compare match or input capture 3B TGRA_4 compare match or input capture TGRA_4 compare match or input capture TGRA_5 compare match or input capture TGRA_5 compare match or input capture
A/D conversion start trigger
TGRA_2 compare match
PPG trigger
TGRA_2/ TGRB_2 compare match
Interrupt sources
4 sources Compare match Compare match
4 sources Compare match or input capture 4A Compare match or input capture 4B
4 sources Compare match or input capture 5A Compare match or input capture 5B Overflow Underflow
Compare Overflow match or Underflow input capture 1B
Compare Overflow match or Underflow input capture 0C Compare match or input capture 0D Overflow [Legend] O: Possible : Not possible
Compare Overflow match or Underflow input capture 3C Compare match or input capture 3D Overflow
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.2 TPU (Unit 1) Functions
Item Count clock Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 P/1 P/4 P/16 P/64 TCLKE TCLKF TCLKG TCLKH TGRA_6 TGRB_6 TGRC_6 TGRD_6 TIOCA6 TIOCB6 TIOCC6 TIOCD6 P/1 P/4 P/16 P/64 P/256 TCLKE TCLKF TGRA_7 TGRB_7 TIOCA7 TIOCB7 P/1 P/4 P/16 P/64 P/1024 TCLKE TCLKF TCLKG TGRA_8 TGRB_8 TIOCA8 TIOCB8 P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 TCLKE TGRA_9 TGRB_9 TGRC_9 TGRD_9 TIOCA9 TIOCB9 TIOCC9 TIOCD9 TGR compare match or input capture O O O O O O O TGR compare match or input capture P/1 P/4 P/16 P/64 P/1024 TCLKE TCLKG TGRA_10 TGRB_10 TIOCA10 TIOCB10 P/1 P/4 P/16 P/64 P/256 TCLKE TCLKG TCLKH TGRA_11 TGRB_11 TIOCA11 TIOCB11
General registers (TGR) General registers/ buffer registers I/O pins
Counter clear function TGR compare match or input capture Compare 0 output match 1 output output Toggle output O O O
TGR compare match or input capture O O O O O O O TGR compare match or input capture
TGR compare match or input capture O O O O O O O TGR compare match or input capture
TGR compare match or input capture O O O O O O O TGR compare match or input capture
TGR compare match or input capture O O O O O O O TGR compare match or input capture
Input capture function O Synchronous operation PWM mode O O
Phase counting mode Buffer operation DTC activation O TGR compare match or input capture
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Section 14 16-Bit Timer Pulse Unit (TPU)
Item DMAC activation
Channel 6 Channel 7 Channel 8 Channel 9 Channel 10 Channel 11 TGRA_6 compare match or input capture TGRA_0/ TGRB_0 compare match 5 sources Compare match or input capture 6A Compare match or input capture 6B TGRA_7 compare match or input capture TGRA_1/ TGRB_1 compare match 4 sources Compare match or input capture 7A Compare match or input capture 7B TGRA_8 compare match or input capture TGRA_2/ TGRB_2 compare match 4 sources Compare match or input capture 8A Compare match or input capture 8B Overflow Underflow TGRA_9 compare match or input capture TGRA_3/ TGRB_3 compare match 5 sources Compare match or input capture 9A TGRA_10 compare match or input capture TGRA_11 compare match or input capture
A/D conversion start trigger PPG trigger
Interrupt sources
4 sources Compare match or input capture 10A
4 sources Compare match or input capture 11A Compare match or input capture 11B Overflow Underflow
Compare Overflow match or Underflow input capture 6C Compare match or input capture 6D Overflow [Legend] O: Possible : Not possible
Compare match or Compare input match or capture 9B input Compare capture 10B match or input Overflow capture 9C Underflow Compare match or input capture 9D Overflow
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Section 14 16-Bit Timer Pulse Unit (TPU)
TIORH TIORL
TMDR
Channel 3
TSR
TGRC
TGRD
TGRA
TGRB
TCNT
Control logic for channels 3 to 5
Input/output pins TIOCA3 Channel 3: TIOCB3 TIOCC3 TIOCD3 TIOCA4 Channel 4: TIOCB4 TIOCA5 Channel 5: TIOCB5
Channel 5
TIOR
TMDR
Channel 2
TSR
Clock input Internal clock: P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 External clock: TCLKA TCLKB TCLKC TCLKD
TIER
TCR
Module data bus
TSTR TSYR
TGRA
Bus interface
TGRB
TCNT
Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U
TMDR
Channel 4
TSR
TIER
TCR
TGRA
TIOR
TMDR
TSR
TIER
TCR
TGRB
TCNT
Common
Control logic
Internal data bus
A/D conversion start request signal PPG output trigger signal
TIOR
TIER
TCR
TGRA
TGRB
TCNT
TIORH TIORL
Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U
TMDR
Control logic for channels 0 to 2
Channel 1
TSR
TIOR
TMDR
Channel 0
TSR
TIER
TCR
TGRA
TGRB TGRC TGRD TGRB
TCNT TCNT
[Legend] TSTR: TSYR: TCR: TMDR: TIOR (H, L):
Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control registers (H, L)
TIER: TSR: TGR (A, B, C, D): TCNT:
TIER
TCR
Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter
Figure 14.1 Block Diagram of TPU (Unit 0)
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TGRA
Section 14 16-Bit Timer Pulse Unit (TPU)
TIORH TIORL
TMDR
Channel 9
TSR
TGRC
TGRD
TGRA
TGRB
TCNT
Control logic for channels 9 to 11
Input/output pins TIOCA9 Channel 9: TIOCB9 TIOCC9 TIOCD9 Channel 10: TIOCA10 TIOCB10 Channel 11: TIOCA11 TIOCB11
Channel 11
TIOR
TMDR
Channel 8
TSR
Clock input Internal clock: P/1 P/4 P/16 P/64 P/256 P/1024 P/4096 External clock: TCLKE TCLKF TCLKG TCLKH
TIER
TCR
Module data bus
TSTRB TSYRB
TGRA
Bus interface
TGRB
TCNT
Interrupt request signals Channel 9: TGI9A TGI9B TGI9C TGI9D TCI9V Channel 10: TGI10A TGI10B TCI10V TCI10U Channel 11: TGI11A TGI11B TCI11V TCI11U
TMDR
Channel 10
TSR
TIER
TCR
TGRA
TIOR
TMDR
TSR
TIER
TCR
TGRB
TCNT
Common
Control logic
Internal data bus
PPG output trigger signal
TIOR
TIER
TCR
TGRA
TGRB
TCNT
Control logic for channels 6 to 8
TIORH TIORL
TMDR
Input/output pins TIOCA6 Channel 6: TIOCB6 TIOCC6 TIOCD6 TIOCA7 Channel 7: TIOCB7 TIOCA8 Channel 8: TIOCB8
Interrupt request signals Channel 6: TGI6A TGI6B TGI6C TGI6D TCI6V Channel 7: TGI7A TGI7B TCI7V TCI7U Channel 8: TGI8A TGI8B TCI8V TCI8U
TMDR
Channel 7
TSR
TIOR
Channel 6
TSR
TIER
TCR
TGRA
TGRB TGRC TGRD TGRB
TCNT TCNT
[Legend] TSTRB: TSYRB: TCR: TMDR: TIOR (H, L):
Timer start register Timer synchronous register Timer control register Timer mode register Timer I/O control registers (H, L)
TIER: TSR: TGR (A, B, C, D): TCNT:
TIER
TCR
Timer interrupt enable register Timer status register Timer general registers (A, B, C, D) Timer counter
Figure 14.2 Block Diagram of TPU (Unit 1)
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TGRA
Section 14 16-Bit Timer Pulse Unit (TPU)
14.2
Input/Output Pins
Table 14.3 shows TPU pin configurations. Table 14.3 Pin Configuration
Unit 0 Channel All Symbol TCLKA I/O Input Function External clock A input pin (Phase counting mode A phase input for channels 1 and 5) TCLKB Input External clock B input pin (Phase counting mode B phase input for channels 1 and 5) TCLKC Input External clock C input pin (Phase counting mode A phase input for channels 2 and 4) TCLKD Input External clock D input pin (Phase counting mode B phase input for channels 2 and 4) 3 TIOCA3 TIOCB3 TIOCC3 TIOCD3 4 TIOCA4 TIOCB4 5 TIOCA5 TIOCB5 I/O I/O I/O I/O I/O I/O I/O I/O TGRA_3 input capture input/output compare output/PWM output pin TGRB_3 input capture input/output compare output/PWM output pin TGRC_3 input capture input/output compare output/PWM output pin TGRD_3 input capture input/output compare output/PWM output pin TGRA_4 input capture input/output compare output/PWM output pin TGRB_4 input capture input/output compare output/PWM output pin TGRA_5 input capture input/output compare output/PWM output pin TGRB_5 input capture input/output compare output/PWM output pin
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Section 14 16-Bit Timer Pulse Unit (TPU)
Unit 1
Channel All
Symbol TCLKE
I/O Input
Function External clock E input pin (Phase counting mode A phase input for channels 7 and 11)
TCLKF
Input
External clock F input pin (Phase counting mode B phase input for channels 7 and 11)
TCLKG
Input
External clock G input pin (Phase counting mode A phase input for channels 8 and 10)
TCLKH
Input
External clock H input pin (Phase counting mode B phase input for channels 8 and 10)
6
TIOCA6 TIOCB6 TIOCC6 TIOCD6
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
TGRA_6 input capture input/output compare output/PWM output pin TGRB_6 input capture input/output compare output/PWM output pin TGRC_6 input capture input/output compare output/PWM output pin TGRD_6 input capture input/output compare output/PWM output pin TGRA_7 input capture input/output compare output/PWM output pin TGRB_7 input capture input/output compare output/PWM output pin TGRA_8 input capture input/output compare output/PWM output pin TGRB_8 input capture input/output compare output/PWM output pin TGRA_9 input capture input/output compare output/PWM output pin TGRB_9 input capture input/output compare output/PWM output pin TGRC_9 input capture input/output compare output/PWM output pin TGRD_9 input capture input/output compare output/PWM output pin TGRA_10 input capture input/output compare output/PWM output pin TGRB_10 input capture input/output compare output/PWM output pin TGRA_11 input capture input/output compare output/PWM output pin TGRB_11 input capture input/output compare output/PWM output pin
7
TIOCA7 TIOCB7
8
TIOCA8 TIOCB8
9
TIOCA9 TIOCB9 TIOCC9 TIOCD9
10
TIOCA10 TIOCB10
11
TIOCA11 TIOCB11
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3
Register Descriptions
The TPU has the following registers in each channel. Registers in the unit 0 and unit 1 have the same functions except for the bit 7 in TIER and TIOR, namely, the TTGE bit in unit 0 and a reserved bit in unit 1. This section gives explanations regarding unit 0 except TIOR. Unit 0: * Channel 0: Timer control register_0 (TCR_0) Timer mode register_0 (TMDR_0) Timer I/O control register H_0 (TIORH_0) Timer I/O control register L_0 (TIORL_0) Timer interrupt enable register_0 (TIER_0) Timer status register_0 (TSR_0) Timer counter_0 (TCNT_0) Timer general register A_0 (TGRA_0) Timer general register B_0 (TGRB_0) Timer general register C_0 (TGRC_0) Timer general register D_0 (TGRD_0) * Channel 1: Timer control register_1 (TCR_1) Timer mode register_1 (TMDR_1) Timer I/O control register _1 (TIOR_1) Timer interrupt enable register_1 (TIER_1) Timer status register_1 (TSR_1) Timer counter_1 (TCNT_1) Timer general register A_1 (TGRA_1) Timer general register B_1 (TGRB_1)
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Section 14 16-Bit Timer Pulse Unit (TPU)
* Channel 2: Timer control register_2 (TCR_2) Timer mode register_2 (TMDR_2) Timer I/O control register_2 (TIOR_2) Timer interrupt enable register_2 (TIER_2) Timer status register_2 (TSR_2) Timer counter_2 (TCNT_2) Timer general register A_2 (TGRA_2) Timer general register B_2 (TGRB_2) * Channel 3: Timer control register_3 (TCR_3) Timer mode register_3 (TMDR_3) Timer I/O control register H_3 (TIORH_3) Timer I/O control register L_3 (TIORL_3) Timer interrupt enable register_3 (TIER_3) Timer status register_3 (TSR_3) Timer counter_3 (TCNT_3) Timer general register A_3 (TGRA_3) Timer general register B_3 (TGRB_3) Timer general register C_3 (TGRC_3) Timer general register D_3 (TGRD_3) * Channel 4: Timer control register_4 (TCR_4) Timer mode register_4 (TMDR_4) Timer I/O control register _4 (TIOR_4) Timer interrupt enable register_4 (TIER_4) Timer status register_4 (TSR_4) Timer counter_4 (TCNT_4) Timer general register A_4 (TGRA_4) Timer general register B_4 (TGRB_4)
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Section 14 16-Bit Timer Pulse Unit (TPU)
* Channel 5: Timer control register_5 (TCR_5) Timer mode register_5 (TMDR_5) Timer I/O control register_5 (TIOR_5) Timer interrupt enable register_5 (TIER_5) Timer status register_5 (TSR_5) Timer counter_5 (TCNT_5) Timer general register A_5 (TGRA_5) Timer general register B_5 (TGRB_5) * Common Registers: Timer start register (TSTR) Timer synchronous register (TSYR) Unit 1: * Channel 6: Timer control register_6 (TCR_6) Timer mode register_6 (TMDR_6) Timer I/O control register H_6 (TIORH_6) Timer I/O control register L_6 (TIORL_6) Timer interrupt enable register_6 (TIER_6) Timer status register_6 (TSR_6) Timer counter_6 (TCNT_6) Timer general register A_6 (TGRA_6) Timer general register B_6 (TGRB_6) Timer general register C_6 (TGRC_6) Timer general register D_6 (TGRD_6)
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Section 14 16-Bit Timer Pulse Unit (TPU)
* Channel 7: Timer control register_7 (TCR_7) Timer mode register_7 (TMDR_7) Timer I/O control register _7 (TIOR_7) Timer interrupt enable register_7 (TIER_7) Timer status register_7 (TSR_7) Timer counter_7 (TCNT_7) Timer general register A_7 (TGRA_7) Timer general register B_7 (TGRB_7) * Channel 8: Timer control register_8 (TCR_8) Timer mode register_8 (TMDR_8) Timer I/O control register_8 (TIOR_8) Timer interrupt enable register_8 (TIER_8) Timer status register_8 (TSR_8) Timer counter_8 (TCNT_8) Timer general register A_8 (TGRA_8) Timer general register B_8 (TGRB_8) * Channel 9: Timer control register_9 (TCR_9) Timer mode register_9 (TMDR_9) Timer I/O control register H_9 (TIORH_9) Timer I/O control register L_9 (TIORL_9) Timer interrupt enable register_9 (TIER_9) Timer status register_9 (TSR_9) Timer counter_9 (TCNT_9) Timer general register A_9 (TGRA_9) Timer general register B_9 (TGRB_9) Timer general register C_9 (TGRC_9) Timer general register D_9 (TGRD_9)
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Section 14 16-Bit Timer Pulse Unit (TPU)
* Channel 10: Timer control register_10 (TCR_10) Timer mode register_10 (TMDR_10) Timer I/O control register _10 (TIOR_10) Timer interrupt enable register_10 (TIER_10) Timer status register_10 (TSR_10) Timer counter_10 (TCNT_10) Timer general register A_10 (TGRA_10) Timer general register B_10 (TGRB_10) * Channel 11: Timer control register_11 (TCR_11) Timer mode register_11 (TMDR_11) Timer I/O control register_11 (TIOR_11) Timer interrupt enable register_11 (TIER_11) Timer status register_11 (TSR_11) Timer counter_11 (TCNT_11) Timer general register A_11 (TGRA_11) Timer general register B_11 (TGRB_11) * Common Registers: Timer start register (TSTRB) Timer synchronous register (TSYRB)
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.1
Timer Control Register (TCR)
TCR controls the TCNT operation for each channel. The TPU has a total of six TCR registers, one for each channel. TCR register settings should be made only while TCNT operation is stopped.
Bit Bit Name Initial Value R/W 7 CCLR2 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 CKEG1 0 R/W 3 CKEG0 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W
Bit 7 6 5 4 3
Bit Name CCLR2 CCLR1 CCLR0 CKEG1 CKEG0
Initial Value 0 0 0 0 0
R/W R/W R/W R/W R/W R/W
Description Counter Clear 2 to 0 These bits select the TCNT counter clearing source. For details, see tables 14.4 and 14.5. Clock Edge 1 and 0 These bits select the input clock edge. For details, see table 14.6. When the input clock is counted using both edges, the input clock period is halved (e.g. P/4 both edges = P/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Internal clock edge selection is valid when the input clock is P/4 or slower. This setting is ignored if the input clock is P/1, or when overflow/underflow of another channel is selected. Timer Prescaler 2 to 0 These bits select the TCNT counter clock. The clock source can be selected independently for each channel. See tables 14.7 to 14.12 for details. To select the external clock as the clock source, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 13, I/O Ports.
2 1 0
TPSC2 TPSC1 TPSC0
0 0 0
R/W R/W R/W
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.4 CCLR2 to CCLR0 (Channels 0 and 3)
Channel 0, 3 Bit 7 CCLR2 0 0 0 0 Bit 6 CCLR1 0 0 1 1 Bit 5 CCLR0 0 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ 1 synchronous operation* TCNT clearing disabled TCNT cleared by TGRC compare match/input capture*2 TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1
1 1 1 1
0 0 1 1
0 1 0 1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur.
Table 14.5 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
Channel 1, 2, 4, 5 Bit 7 Bit 6 Reserved*2 CCLR1 0 0 0 0 0 0 1 1 Bit 5 CCLR0 0 1 0 1 Description TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation*1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1. 2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.6 Input Clock Edge Selection
Clock Edge Selection CKEG1 0 0 1 CKEG0 0 1 x Internal Clock Counted at falling edge Counted at rising edge Counted at both edges Input Clock External Clock Counted at rising edge Counted at falling edge Counted at both edges
[Legend] x: Don't care
Table 14.7 TPSC2 to TPSC0 (Channel 0)
Channel 0 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input
Table 14.8 TPSC2 to TPSC0 (Channel 1)
Channel 1 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on P/256 Counts on TCNT2 overflow/underflow
Note: This setting is ignored when channel 1 is in phase counting mode.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.9 TPSC2 to TPSC0 (Channel 2)
Channel 2 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on P/1024
Note: This setting is ignored when channel 2 is in phase counting mode.
Table 14.10 TPSC2 to TPSC0 (Channel 3)
Channel 3 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input Internal clock: counts on P/1024 Internal clock: counts on P/256 Internal clock: counts on P/4096
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.11 TPSC2 to TPSC0 (Channel 4)
Channel 4 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on P/1024 Counts on TCNT5 overflow/underflow
Note: This setting is ignored when channel 4 is in phase counting mode.
Table 14.12 TPSC2 to TPSC0 (Channel 5)
Channel 5 Bit 2 TPSC2 0 0 0 0 1 1 1 1 Bit 1 TPSC1 0 0 1 1 0 0 1 1 Bit 0 TPSC0 0 1 0 1 0 1 0 1 Description Internal clock: counts on P/1 Internal clock: counts on P/4 Internal clock: counts on P/16 Internal clock: counts on P/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on P/256 External clock: counts on TCLKD pin input
Note: This setting is ignored when channel 5 is in phase counting mode.
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.2
Timer Mode Register (TMDR)
TMDR sets the operating mode for each channel. The TPU has six TMDR registers, one for each channel. TMDR register settings should be made only while TCNT operation is stopped.
Bit Bit Name Initial Value R/W 7 1 6 1 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W
Bit 7, 6 5
Bit Name BFB
Initial Value All 1 0
R/W R/W
Description Reserved These bits are always read as 1 and cannot be modified. Buffer Operation B This bit specifies whether TGRB is to normally operate, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: TGRB operates normally 1: TGRB and TGRD used together for buffer operation
4
BFA
0
R/W
Buffer Operation A This bit specifies whether TGRA is to normally operate, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. 0: TGRA operates normally 1: TGRA and TGRC used together for buffer operation
3 2 1 0
MD3 MD2 MD1 MD0
0 0 0 0
R/W R/W R/W R/W
Modes 3 to 0 These bits set the timer operating mode. MD3 is a reserved bit. The write value should always be 0. For details, see table 14.13.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.13 MD3 to MD0
Bit 3 1 MD3* 0 0 0 0 0 0 0 0 1 Bit 2 MD2*2 0 0 0 0 1 1 1 1 x Bit 1 MD1 0 0 1 1 0 0 1 1 x Bit 0 MD0 0 1 0 1 0 1 0 1 x Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4
[Legend] x: Don't care Notes: 1. MD3 is a reserved bit. The write value should always be 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2.
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.3
Timer I/O Control Register (TIOR)
TIOR controls TGR. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. To designate the input capture pin in TIOR, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 13, I/O Ports. * TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5
Bit Bit Name Initial Value R/W 7 IOB3 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W
* TIORL_0, TORL_3
Bit Bit Name Initial Value R/W 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W
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Section 14 16-Bit Timer Pulse Unit (TPU)
* TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 (Unit 0) * TIORH_6, TIOR_7, TIOR_8, TIORH_9, TIOR_10, TIOR_11 (Unit 1)
Bit 7 6 5 4 3 2 1 0 Bit Name IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description I/O Control B3 to B0 These bits specify the function of TGRB. For details, see tables 14.14, 14.15, 14.18 to 14.22, 14.24, and 14.26 to 14.29. I/O Control A3 to A0 These bits specify the function of TGRA. For details, see tables 14.30, 14.31, 14.34 to 14.38, 14.40, and 14.42 to 14.45.
* TIORL_0, TIORL_3 (Unit 0) * TIORL_6, TIORL_9 (Unit 1)
Bit 7 6 5 4 3 2 1 0 Bit Name IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W I/O Control C3 to C0 These bits specify the function of TGRC. For details, see tables 14.32, 14.33, 14.39, and 14.41. Description I/O Control D3 to D0 These bits specify the function of TGRD. For details, see tables 14.16, 14.17, 14.23, and 14.25.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.14 TIORH_6 (Unit 1)
Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 Input capture register TGRB_6 Function Output compare register TIOCB6 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCB6 pin. Input capture at rising edge Capture input source is TIOCB6 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCB6 pin. Input capture at both edges 1 1 x x Capture input source is channel 7/count clock. Input capture at TCNT_7 count-up/count-down* [Legend] x: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_7 are set to B'000 and P/1 is used as the TCNT_7 count clock, this setting is invalid and input capture is not generated.
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.15 TIORH_0 (Unit 0)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 TGRB_0 Function Output compare register TIOCB0 Pin Function Output disabled
0 0 0 0 0 0 0 1 1 1 1
0 0 0 1 1 1 1 0 0 0 1
0 1 1 0 0 1 1 0 0 1 x
1 0 1 0 1 0 1 0 1 x x
Setting prohibited
Input capture register
Capture input source is channel 1/count clock. Input capture at TCNT_1 count-up/count-down*
[Legend] x: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.16 TIORL_6 (Unit 1)
Description Bit 7 IOD3 0 0 0 0 0 0 0 0 1 Bit 6 IOD2 0 0 0 0 1 1 1 1 0 Bit 5 IOD1 0 0 1 1 0 0 1 1 0 Bit 4 IOD0 0 1 0 1 0 1 0 1 0 Input capture register*2 TGRD_6 Function Output compare register*2 TIOCD6 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCD6 pin. Input capture at rising edge Capture input source is TIOCD6 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCD6 pin. Input capture at both edges 1 1 x x Capture input source is channel 7/count clock. Input capture at TCNT_7 count-up/count-down*
1
1
0
0
1
[Legend] x: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_7 are set to B'000 and P/1 is used as the TCNT_7 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_6 is set to 1 and TGRD_6 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.17 TIORL_0 (Unit 0)
Description Bit 7 IOD3 0 Bit 6 IOD2 0 Bit 5 IOD1 0 Bit 4 IOD0 0 TGRD_0 Function Output compare 2 register* TIOCD0 Pin Function Output disabled
0 0 0 0 0 0 0 1 1 1 1
0 0 0 1 1 1 1 0 0 0 1
0 1 1 0 0 1 1 0 0 1 x
1 0 1 0 1 0 1 0 1 x x
Setting prohibited
Input capture register*2
Capture input source is channel 1/count clock. Input capture at TCNT_1 count-up/count-down*
1
[Legend] x: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the TCNT_1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.18 TIOR_7 (Unit 1)
Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 Input capture register TGRB_7 Function Output compare register TIOCB7 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCB7 pin. Input capture at rising edge Capture input source is TIOCB7 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCB7 pin. Input capture at both edges 1 1 x x TGRC_0 compare match/input capture Input capture at generation of TGRC_0 compare match/input capture [Legend] x: Don't care
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.19 TIOR_1 (Unit 0)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 TGRB_1 Function Output compare register TIOCB1 Pin Function Output disabled
0 0 0 0 0 0 0 1 1 1 1
0 0 0 1 1 1 1 0 0 0 1
0 1 1 0 0 1 1 0 0 1 x
1 0 1 0 1 0 1 0 1 x x
Setting prohibited
Input capture register
TGRC_0 compare match/input capture Input capture at generation of TGRC_0 compare match/input capture
[Legend] x: Don't care
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.20 TIOR_8 (Unit 1)
Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 x Bit 5 IOB1 0 0 1 1 0 0 1 1 0 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 Input capture register TGRB_8 Function Output compare register TIOCB8 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCB8 pin. Input capture at rising edge Capture input source is TIOCB8 pin. Input capture at falling edge 1 x 1 x Capture input source is TIOCB8 pin. Input capture at both edges [Legend] x: Don't care
1
x
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.21 TIOR_2 (Unit 0)
Description Bit 7 IOB3 0 Bit 6 IOB2 0 Bit 5 IOB1 0 Bit 4 IOB0 0 TGRB_2 Function Output compare register TIOCB2 Pin Function Output disabled
0 0 0 0 0 0 0 1 1 1
0 0 0 1 1 1 1 x x x
0 1 1 0 0 1 1 0 0 1
1 0 1 0 1 0 1 0 1 x
Setting prohibited
Input capture register
Capture input source is TIOCB2 pin. Input capture at both edges
[Legend] x: Don't care
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.22 TIORH_3 (Unit 0)
Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 Input capture register TGRB_3 Function Output compare register TIOCB3 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCB3 pin. Input capture at rising edge Capture input source is TIOCB3 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCB3 pin. Input capture at both edges 1 1 x x Capture input source is channel 4/count clock. Input capture at TCNT_4 count-up/count-down* [Legend] x: Don't care Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated.
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.23 TIORL_3 (Unit 0)
Description Bit 7 IOD3 0 0 0 0 0 0 0 0 1 Bit 6 IOD2 0 0 0 0 1 1 1 1 0 Bit 5 IOD1 0 0 1 1 0 0 1 1 0 Bit 4 IOD0 0 1 0 1 0 1 0 1 0 Input capture register*2 TGRD_3 Function Output compare register*2 TIOCD3 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCD3 pin. Input capture at rising edge Capture input source is TIOCD3 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCD3 pin. Input capture at both edges 1 1 x x Capture input source is channel 4/count clock. Input capture at TCNT_4 count-up/count-down*
1
1
0
0
1
[Legend] x: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the TCNT_4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.24 TIORH_9 (Unit 1)
Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 Input capture register TGRB_9 Function Output compare register TIOCB9 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCB9 pin. Input capture at rising edge Capture input source is TIOCB9 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCB9 pin. Input capture at both edges 1 1 x x Capture input source is channel 10/count clock. Input capture at TCNT_10 count-up/count-down* [Legend] x: Don't care Notes: * When bits TPSC2 to TPSC0 in TCR_10 are set to B'000 and P/1 is used as the TCNT_10 count clock, this setting is invalid and input capture is not generated.
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.25 TIORL_9 (Unit 1)
Description Bit 7 IOD3 0 0 0 0 0 0 0 0 1 Bit 6 IOD2 0 0 0 0 1 1 1 1 0 Bit 5 IOD1 0 0 1 1 0 0 1 1 0 Bit 4 IOD0 0 1 0 1 0 1 0 1 0 Input capture register*2 TGRD_9 Function Output compare register*2 TIOCD9 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCD9 pin. Input capture at rising edge Capture input source is TIOCD9 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCD9 pin. Input capture at both edges 1 1 x x Capture input source is channel 10/count clock. Input capture at TCNT_10 count-up/count-down* [Legend] x: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR_10 are set to B'000 and P/1 is used as the TCNT_10 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR_9 is set to 1 and TGRD_9 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
1
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.26 TIOR_4 (Unit 0)
Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 Input capture register TGRB_4 Function Output compare register TIOCB4 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCB4 pin. Input capture at rising edge Capture input source is TIOCB4 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCB4 pin. Input capture at both edges 1 1 x x Capture input source is TGRC_3 compare match/input capture. Input capture at generation of TGRC_3 compare match/input capture [Legend] x: Don't care
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.27 TIOR_5 (Unit 0)
Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 x Bit 5 IOB1 0 0 1 1 0 0 1 1 0 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 Input capture register TGRB_5 Function Output compare register TIOCB5 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCB5 pin. Input capture at rising edge Capture input source is TIOCB5 pin. Input capture at falling edge 1 x 1 x Capture input source is TIOCB5 pin. Input capture at both edges [Legend] x: Don't care
1
x
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.28 TIOR_10 (Unit 1)
Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 0 Bit 5 IOB1 0 0 1 1 0 0 1 1 0 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 Input capture register TGRB_10 Function Output compare register TIOCB10 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCB10 pin. Input capture at rising edge Capture input source is TIOCB10 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCB10 pin. Input capture at both edges 1 1 x x Capture input source is TGRC_9 compare match/input capture. Input capture at generation of TGRC_9 compare match/input capture [Legend] x: Don't care
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.29 TIOR_11 (Unit 1)
Description Bit 7 IOB3 0 0 0 0 0 0 0 0 1 Bit 6 IOB2 0 0 0 0 1 1 1 1 x Bit 5 IOB1 0 0 1 1 0 0 1 1 0 Bit 4 IOB0 0 1 0 1 0 1 0 1 0 Input capture register TGRB_11 Function Output compare register TIOCB11 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCB11 pin. Input capture at rising edge Capture input source is TIOCB11 pin. Input capture at falling edge 1 x 1 x Capture input source is TIOCB11 pin. Input capture at both edges [Legend] x: Don't care
1
x
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.30 TIORH_6 (Unit 1)
Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 Input capture register TGRA_6 Function Output compare register TIOCA6 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCA6 pin. Input capture at rising edge Capture input source is TIOCA6 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCA6 pin. Input capture at both edges 1 1 x x Capture input source is channel 7/count clock. Input capture at TCNT_7 count-up/count-down* [Legend] x: Don't care Note: * When the bits TPSC2 to TPSC0 in TCR_7 are set to B'000 and P/1 is used as the count clock of TCNT_7, this setting is invalid and input capture is not generated.
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.31 TIORH_0 (Unit 0)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 TGRA_0 Function Output compare register TIOCA0 Pin Function Output disabled
0 0 0 0 0 0 0 1 1 1 1
0 0 0 1 1 1 1 0 0 0 1
0 1 1 0 0 1 1 0 0 1 x
1 0 1 0 1 0 1 1 0 x x
Setting prohibited
Input capture register
Capture input source is channel 1/count clock. Input capture at TCNT_1 count-up/count-down*
[Legend] x: Don't care Note: * When the bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the count clock of TCNT_1, this setting is invalid and input capture is not generated.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.32 TIORL_6 (Unit 1)
Description Bit 3 IOC3 0 0 0 0 0 0 0 0 1 Bit 2 IOC2 0 0 0 0 1 1 1 1 0 Bit 1 IOC1 0 0 1 1 0 0 1 1 0 Bit 0 IOC0 0 1 0 1 0 1 0 1 0 Input capture register*2 TGRC_6 Function Output compare register*2 TIOCC6 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCC6 pin. Input capture at rising edge Capture input source is TIOCC6 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCC6 pin. Input capture at both edges 1 1 x x Capture input source is channel 1/count clock. Input capture at TCNT_7 count-up/count-down*
1
1
0
0
1
[Legend] x: Don't care Note: 1. When the bits TPSC2 to TPSC0 in TCR_7 are set to B'000 and P/1 is used as the count clock of TCNT_7, this setting is invalid and input capture is not generated. 2. When the BFA bit in TMDR_6 is set to 1 and TGRC_6 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.33 TIORL_0 (Unit 0)
Description Bit 3 IOC3 0 Bit 2 IOC2 0 Bit 1 IOC1 0 Bit 0 IOC0 0 TGRC_0 Function Output compare 2 register* TIOCC0 Pin Function Output disabled
0 0 0 0 0 0 0 1 1 1 1
0 0 0 1 1 1 1 0 0 0 1
0 1 1 0 0 1 1 0 0 1 x
1 0 1 0 1 0 1 0 1 x x
Setting prohibited
Input capture register*2
Capture input source is channel 1/count clock Input capture at TCNT_1 count-up/count-down*
1
[Legend] x: Don't care Note: 1. When the bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and P/1 is used as the count clock of TCNT_1, this setting is invalid and input capture is not generated. 2. When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.34 TIOR_7 (Unit 1)
Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 Input capture register TGRA_7 Function Output compare register TIOCA7 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCA7 pin. Input capture at rising edge Capture input source is TIOCA7 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCA7 pin. Input capture at both edges 1 1 x x Capture input source is TGRA_6 compare match/input capture. Input capture at generation of channel 6/TGRA_6 compare match/input capture [Legend] x: Don't care
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.35 TIOR_1 (Unit 0)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 TGRA_1 Function Output compare register TIOCA1 Pin Function Output disabled
0 0 0 0 0 0 0 1 1 1 1
0 0 0 1 1 1 1 0 0 0 1
0 1 1 0 0 1 1 0 0 1 x
1 0 1 0 1 0 1 0 1 x x
Setting prohibited
Input capture register
Capture input source is TGRA_0 compare match/input capture. Input capture at generation of channel 0/TGRA_0 compare match/input capture
[Legend] x: Don't care
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.36 TIOR_8 (Unit 1)
Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 x Bit 1 IOA1 0 0 1 1 0 0 1 1 0 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 Input capture register TGRA_8 Function Output compare register TIOCA8 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCA8 pin. Input capture at rising edge Capture input source is TIOCA8 pin. Input capture at falling edge 1 x 1 x Capture input source is TIOCA8 pin. Input capture at both edges [Legend] x: Don't care
1
x
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.37 TIOR_2 (Unit 0)
Description Bit 3 IOA3 0 Bit 2 IOA2 0 Bit 1 IOA1 0 Bit 0 IOA0 0 TGRA_2 Function Output compare register TIOCA2 Pin Function Output disabled
0 0 0 0 0 0 0 1 1 1
0 0 0 1 1 1 1 x x x
0 1 1 0 0 1 1 0 0 1
1 0 1 0 1 0 1 0 1 x
Setting prohibited
[Legend] x: Don't care
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.38 TIORH_3 (Unit 0)
Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 Input capture register TGRA_3 Function Output compare register TIOCA3 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCA3 pin. Input capture at rising edge Capture input source is TIOCA3 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCA3 pin. Input capture at both edges 1 1 x x Capture input source is channel 4/count clock. Input capture at TCNT_4 count-up/count-down* [Legend] x: Don't care Note: * When the bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the count clock of TCNT_4, this setting is invalid and input capture is not generated.
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.39 TIORL_3 (Unit 0)
Description Bit 3 IOC3 0 0 0 0 0 0 0 0 1 Bit 2 IOC2 0 0 0 0 1 1 1 1 0 Bit 1 IOC1 0 0 1 1 0 0 1 1 0 Bit 0 IOC0 0 1 0 1 0 1 0 1 0 Input capture register*2 TGRC_3 Function Output compare register*2 TIOCC3 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCC3 pin. Input capture at rising edge Capture input source is TIOCC3 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCC3 pin. Input capture at both edges 1 1 x x Capture input source is channel 4/count clock. Input capture at TCNT_4 count-up/count-down*
1
1
0
0
1
[Legend] x: Don't care Note: 1. When the bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and P/1 is used as the count clock of TCNT_4, this setting is invalid and input capture is not generated. 2. When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.40 TIORH_9 (Unit 1)
Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 Input capture register TGRA_9 Function Output compare register TIOCA9 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCA9 pin. Input capture at rising edge Capture input source is TIOCA9 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCA9 pin. Input capture at both edges 1 1 x x Capture input source is channel 10/count clock. Input capture at TCNT_10 count-up/count-down* [Legend] x: Don't care Note: * When the bits TPSC2 to TPSC0 in TCR_10 are set to B'000 and P/1 is used as the count clock of TCNT_10, this setting is invalid and input capture is not generated.
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.41 TIORL_9 (Unit 1)
Description Bit 3 IOC3 0 0 0 0 0 0 0 0 1 Bit 2 IOC2 0 0 0 0 1 1 1 1 0 Bit 1 IOC1 0 0 1 1 0 0 1 1 0 Bit 0 IOC0 0 1 0 1 0 1 0 1 0 Input capture register*2 TGRC_9 Function Output compare register*2 TIOCC9 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCC9 pin. Input capture at rising edge Capture input source is TIOCC9 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCC9 pin. Input capture at both edges 1 1 x x Capture input source is channel 10/count clock. Input capture at TCNT_10 count-up/count-down* [Legend] x: Don't care Note: 1. When the bits TPSC2 to TPSC0 in TCR_10 are set to B'000 and P/1 is used as the count clock of TCNT_10, this setting is invalid and input capture is not generated. 2. When the BFA bit in TMDR_9 is set to 1 and TGRC_9 is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
1
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.42 TIOR_4 (Unit 0)
Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 Input capture register TGRA_4 Function Output compare register TIOCA4 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCA4 pin. Input capture at rising edge Capture input source is TIOCA4 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCA4 pin. Input capture at both edges 1 1 x x Capture input source is TGRA_3 compare match/input capture. Input capture at generation of TGRA_3 compare match/input capture [Legend] x: Don't care
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.43 TIOR_5 (Unit 0)
Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 x Bit 1 IOA1 0 0 1 1 0 0 1 1 0 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 Input capture register TGRA_5 Function Output compare register TIOCA5 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Input capture source is TIOCA5 pin. Input capture at rising edge Input capture source is TIOCA5 pin. Input capture at falling edge 1 x 1 x Input capture source is TIOCA5 pin. Input capture at both edges [Legend] x: Don't care
1
x
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.44 TIOR_10 (Unit 1)
Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 0 Bit 1 IOA1 0 0 1 1 0 0 1 1 0 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 Input capture register TGRA_10 Function Output compare register TIOCA10 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Capture input source is TIOCA10 pin. Input capture at rising edge Capture input source is TIOCA10 pin. Input capture at falling edge 1 0 1 x Capture input source is TIOCA10 pin. Input capture at both edges 1 1 x x Capture input source is TGRA_9 compare match/input capture. Input capture at generation of TGRA_9 compare match/input capture [Legend] x: Don't care
1
0
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
Table 14.45 TIOR_11 (Unit 1)
Description Bit 3 IOA3 0 0 0 0 0 0 0 0 1 Bit 2 IOA2 0 0 0 0 1 1 1 1 x Bit 1 IOA1 0 0 1 1 0 0 1 1 0 Bit 0 IOA0 0 1 0 1 0 1 0 1 0 Input capture register TGRA_11 Function Output compare register TIOCA11 Pin Function Output disabled Initial output is 0 output. 0 output at compare match Initial output is 0 output. 1 output at compare match Initial output is 0 output. Toggle output at compare match Output disabled Initial output is 1 output. 0 output at compare match Initial output is 1 output. 1 output at compare match Initial output is 1 output. Toggle output at compare match Input capture source is TIOCA11 pin. Input capture at rising edge Input capture source is TIOCA11 pin. Input capture at falling edge 1 x 1 x Input capture source is TIOCA11 pin. Input capture at both edges [Legend] x: Don't care
1
x
0
1
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.4
Timer Interrupt Enable Register (TIER)
TIER controls enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel.
Bit Bit Name Initial Value R/W Note: * 7 TTGE* 0 R/W 6 1 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TCIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W
Bit 7 in TIER of unit 1 is a reserved bit. This bit is always read as 0 and the initial value should not be changed.
Bit 7
Bit Name TTGE*
Initial value 0
R/W R/W
Description A/D Conversion Start Request Enable Enables/disables generation of A/D conversion start requests by TGRA input capture/compare match. 0: A/D conversion start request generation disabled 1: A/D conversion start request generation enabled
6 5
TCIEU
1 0
R/W
Reserved This bit is always read as 1 and cannot be modified. Underflow Interrupt Enable Enables/disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1, 2, 4, and 5. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TCIU) by TCFU disabled 1: Interrupt requests (TCIU) by TCFU enabled
4
TCIEV
0
R/W
Overflow Interrupt Enable Enables/disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. 0: Interrupt requests (TCIV) by TCFV disabled 1: Interrupt requests (TCIV) by TCFV enabled
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Section 14 16-Bit Timer Pulse Unit (TPU)
Bit 3
Bit Name TGIED
Initial value 0
R/W R/W
Description TGR Interrupt Enable D Enables/disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGID) by TGFD bit disabled 1: Interrupt requests (TGID) by TGFD bit enabled
2
TGIEC
0
R/W
TGR Interrupt Enable C Enables/disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. 0: Interrupt requests (TGIC) by TGFC bit disabled 1: Interrupt requests (TGIC) by TGFC bit enabled
1
TGIEB
0
R/W
TGR Interrupt Enable B Enables/disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. 0: Interrupt requests (TGIB) by TGFB bit disabled 1: Interrupt requests (TGIB) by TGFB bit enabled
0
TGIEA
0
R/W
TGR Interrupt Enable A Enables/disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. 0: Interrupt requests (TGIA) by TGFA bit disabled 1: Interrupt requests (TGIA) by TGFA bit enabled
Note:
*
The bit 7 in TIER of unit 1 is a reserved bit. This bit is always read as 0 and the initial value should not be changed.
14.3.5
Timer Status Register (TSR)
TSR indicates the status of each channel. The TPU has six TSR registers, one for each channel.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Bit Bit Name Initial Value R/W 7 TCFD 1 R 6 1 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)*
Note: * Only 0 can be written to bits 5 to 0, to clear flags.
Bit 7
Bit Name TCFD
Initial value 1
R/W R
Description Count Direction Flag Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. 0: TCNT counts down. 1: TCNT counts up.
6 5
TCFU
1 0
Reserved This bit is always read as 1 and cannot be modified.
R/(W)* Underflow Flag Status flag that indicates that a TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When a 0 is written to TCFU after reading TCFU = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
4
TCFV
0
R/(W)* Overflow Flag Status flag that indicates that a TCNT overflow has occurred. [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000) [Clearing condition] When a 0 is written to TCFV after reading TCFV = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
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Section 14 16-Bit Timer Pulse Unit (TPU)
Bit 3
Bit Name TGFD
Initial value 0
R/W
Description
R/(W)* Input Capture/Output Compare Flag D Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register When DTC is activated by a TGID interrupt while the DISEL bit in MRB of DTC is 0 When 0 is written to TGFD after reading TGFD = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
[Clearing conditions] * *
2
TGFC
0
R/(W)* Input Capture/Output Compare Flag C Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. [Setting conditions] * * When TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register When DTC is activated by a TGIC interrupt while the DISEL bit in MRB of DTC is 0 When 0 is written to TGFC after reading TGFC = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
[Clearing conditions] * *
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Section 14 16-Bit Timer Pulse Unit (TPU)
Bit 1
Bit Name TGFB
Initial value 0
R/W
Description
R/(W)* Input Capture/Output Compare Flag B Status flag that indicates the occurrence of TGRB input capture or compare match. [Setting conditions] * * When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register When DTC is activated by a TGIB interrupt while the DISEL bit in MRB of DTC is 0 When 0 is written to TGFB after reading TGFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
[Clearing conditions] * *
0
TGFA
0
R/(W)* Input Capture/Output Compare Flag A Status flag that indicates the occurrence of TGRA input capture or compare match. [Setting conditions] * * When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register When DTC is activated by a TGIA interrupt while the DISEL bit in MRB of DTC is 0 When DMAC is activated by a TGIA interrupt while the DTA bit in DMDR of DMAC is 1 When 0 is written to TGFA after reading TGFA = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
[Clearing conditions] * * *
Note:
*
Only 0 can be written to clear the flag.
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.6
Timer Counter (TCNT)
TCNT is a 16-bit readable/writable counter. The TPU has six TCNT counters, one for each channel. TCNT is initialized to H'0000 by a reset or in hardware standby mode. TCNT cannot be accessed in 8-bit units. TCNT must always be accessed in 16-bit units.
Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
14.3.7
Timer General Register (TGR)
TGR is a 16-bit readable/writable register with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must always be accessed in 16-bit units. TGR and buffer register combinations during buffer operations are TGRA-TGRC and TGRB-TGRD.
Bit Bit Name Initial Value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.8
Timer Start Register (TSTR)
TSTR starts or stops operation for channels 0 to 5. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Bit Bit Name Initial Value R/W 7 0 6 0 5 CST5 0 R/W 4 CST4 0 R/W 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W
Bit 7, 6 5 4 3 2 1 0
Bit Name CST5 CST4 CST3 CST2 CST1 CST0
Initial value All 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W
Description Reserved The write value should always be 0. Counter Start 5 to 0 These bits select operation or stoppage for TCNT. If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 0: TCNT_5 to TCNT_0 count operation is stopped. 1: TCNT_5 to TCNT_0 performs count operation.
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.3.9
Timer Synchronous Register (TSYR)
TSYR selects independent operation or synchronous operation for the TCNT counters of channels 0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit Bit Name Initial Value R/W 7 0 R/W 6 0 R/W 5 SYNC5 0 R/W 4 SYNC4 0 R/W 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W
Bit 7, 6 5 4 3 2 1 0
Bit Name SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0
Initial value All 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W
Description Reserved The write value should always be 0. Timer Synchronization 5 to 0 These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels, and synchronous clearing through counter clearing on another channel are possible. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. To set synchronous clearing, in addition to the SYNC bit, the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 0: TCNT_5 to TCNT_0 operate independently. (TCNT presetting/clearing is unrelated to other channels.) 1: TCNT_5 to TCNT_0 perform synchronous operation. (TCNT synchronous presetting/synchronous clearing is possible.)
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.4
14.4.1
Operation
Basic Operation
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, periodic counting, and external event counting. Each TGR can be used as an input capture register or output compare register. (1) Counter Operation
When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. (a) Example of Setting Procedure for Count Operation
Figure 14.3 shows an example of the count operation setting procedure.
Operation selection
Select counter clock
[1]
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2].
Periodic counter
Free-running counter
Select counter clearing source
[2]
Select output compare register
[3]
[5] Set the CST bit in TSTR to 1 to start the counter operation.
Set period
[4]
Start count
[5]
Start count
[5]
Figure 14.3 Example of Counter Operation Setting Procedure
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Section 14 16-Bit Timer Pulse Unit (TPU)
(b)
Free-Running Count Operation and Periodic Count Operation
Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count operation as a free-running counter. When TCNT overflows (changes from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 14.4 illustrates free-running counter operation.
TCNT value H'FFFF
H'0000
Time
CST bit
TCFV
Figure 14.4 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts count-up operation as a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000.
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Section 14 16-Bit Timer Pulse Unit (TPU)
Figure 14.5 illustrates periodic counter operation.
TCNT value TGR
Counter cleared by TGR compare match
H'0000
Time
CST bit Flag cleared by software or DTC activation TGF
Figure 14.5 Periodic Counter Operation (2) Waveform Output by Compare Match
The TPU can perform 0, 1, or toggle output from the corresponding output pin using a compare match. (a) Example of Setting Procedure for Waveform Output by Compare Match
Figure 14.6 shows an example of the setting procedure for waveform output by a compare match.
Output selection
Select waveform output mode
[1]
[1] Select initial value from 0-output or 1-output, and compare match output value from 0-output, 1-output, or toggle-output, by means of TIOR. The set initial value is output on the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. [3] Set the CST bit in TSTR to 1 to start the count operation.
Set output timing
[2]
Start count
[3]

Figure 14.6 Example of Setting Procedure for Waveform Output by Compare Match
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Section 14 16-Bit Timer Pulse Unit (TPU)
(b)
Examples of Waveform Output Operation
Figure 14.7 shows an example of 0 output/1 output . In this example, TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level match, the pin level does not change.
TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1-output 0-output Time
Figure 14.7 Example of 0-Output/1-Output Operation Figure 14.8 shows an example of toggle output. In this example, TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B.
TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 TIOCB TIOCA Time Toggle-output Toggle-output
Figure 14.8 Example of Toggle Output Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
(3)
Input Capture Function
The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 3, P/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if P/1 is selected. (a) Example of Setting Procedure for Input Capture Operation
Figure 14.9 shows an example of the setting procedure for input capture operation.
Input selection
Select input capture input
[1]
[1] Designate TGR as an input capture register by means of TIOR, and select the input capture source and input signal edge (rising edge, falling edge, or both edges). [2] Set the CST bit in TSTR to 1 to start the count operation.
Start count
[2]

Figure 14.9 Example of Setting Procedure for Input Capture Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
(b)
Example of Input Capture Operation
Figure 14.10 shows an example of input capture operation. In this example, both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Counter cleared by TIOCB input (falling edge)
TCNT value H'0180 H'0160
H'0010 H'0005 H'0000 Time
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB
TGRB
H'0180
Figure 14.10 Example of Input Capture Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.4.2
Synchronous Operation
In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously (synchronous presetting). Also, multiple TCNT counters can be cleared simultaneously (synchronous clearing) by making the appropriate setting in TCR. Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. (1) Example of Setting Procedure for Synchronous Operation
Figure 14.11 shows an example of the synchronous operation setting procedure.
Synchronous operation selection Set synchronous operation
[1]
Synchronous presetting
Synchronous clearing
Set TCNT
[2]
Clearing source generation channel? Yes Select counter clearing source Start count
No
[3] [5]
Set synchronous counter clearing Start count
[4] [5]

[1] Set the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation to 1. [2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. [3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. [4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. [5] Set the CST bits in TSTR for the relevant channels to 1, to start the count operation.
Figure 14.11 Example of Synchronous Operation Setting Procedure
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Section 14 16-Bit Timer Pulse Unit (TPU)
(2)
Example of Synchronous Operation
Figure 14.12 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this time, synchronous presetting and synchronous clearing by TGRB_0 compare match are performed for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle. For details on PWM modes, see section 14.4.5, PWM Modes.
Synchronous clearing by TGRB_0 compare match TCNT_0 to TCNT_2 values TGRB_0 TGRB_1 TGRA_0 TGRB_2 TGRA_1 TGRA_2 H'0000 TIOCA_0 TIOCA_1 TIOCA_2 Time
Figure 14.12 Example of Synchronous Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.4.3
Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or a compare match register. Table 14.46 shows the register combinations used in buffer operation. Table 14.46 Register Combinations in Buffer Operation
Channel 0 Timer General Register TGRA_0 TGRB_0 3 TGRA_3 TGRB_3 Buffer Register TGRC_0 TGRD_0 TGRC_3 TGRD_3
* When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 14.13.
Compare match signal
Buffer register
Timer general register
Comparator
TCNT
Figure 14.13 Compare Match Buffer Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
* When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in TGR is transferred to the buffer register. This operation is illustrated in figure 14.14.
Input capture signal
Buffer register
Timer general register
TCNT
Figure 14.14 Input Capture Buffer Operation (1) Example of Buffer Operation Setting Procedure
Figure 14.15 shows an example of the buffer operation setting procedure.
Buffer operation
Select TGR function
[1]
[1] Designate TGR as an input capture register or output compare register by means of TIOR. [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation.
Set buffer operation
[2]
Start count
[3]

Figure 14.15 Example of Buffer Operation Setting Procedure
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Section 14 16-Bit Timer Pulse Unit (TPU)
(2) (a)
Examples of Buffer Operation When TGR is an output compare register
Figure 14.16 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs, the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details on PWM modes, see section 14.4.5, PWM Modes.
TCNT value TGRB_0 H'0200 TGRA_0 H'0000 TGRC_0 H'0200 Transfer TGRA_0 H'0200 H'0450 H'0450 H'0520 Time
H'0450
H'0520
TIOCA
Figure 14.16 Example of Buffer Operation (1)
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Section 14 16-Bit Timer Pulse Unit (TPU)
(b)
When TGR is an input capture register
Figure 14.17 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
TCNT value
H'0F07 H'09FB H'0532 H'0000 Time
TIOCA
TGRA
H'0532
H'0F07
H'09FB
TGRC
H'0532
H'0F07
Figure 14.17 Example of Buffer Operation (2)
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.4.4
Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 14.47 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 14.47 Cascaded Combinations
Combination Channels 1 and 2 Channels 4 and 5 Upper 16 Bits TCNT_1 TCNT_4 Lower 16 Bits TCNT_2 TCNT_5
(1)
Example of Cascaded Operation Setting Procedure
Figure 14.18 shows an example of the setting procedure for cascaded operation.
Cascaded operation
[1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'1111 to select TCNT_2 (TCNT_5) overflow/underflow counting. [1] [2] Set the CST bit in TSTR for the upper and lower channels to 1 to start the count operation.
Set cascading
Start count
[2]

Figure 14.18 Cascaded Operation Setting Procedure
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Section 14 16-Bit Timer Pulse Unit (TPU)
(2)
Examples of Cascaded Operation
Figure 14.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been designated as input capture registers, and the TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
TCNT_1 clock TCNT_1 TCNT_2 clock TCNT_2 TIOCA1, TIOCA2 TGRA_1 H'03A2 H'FFFF H'0000 H'0001 H'03A1 H'03A2
TGRA_2
H'0000
Figure 14.19 Example of Cascaded Operation (1) Figure 14.20 illustrates the operation when counting upon TCNT_2 overflow/underflow has been set for TCNT_1, and phase counting mode has been designated for channel 2. TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD
TCNT_2
FFFD
FFFE
FFFF
0000
0001
0002
0001
0000
FFFF
TCNT_1
0000
0001
0000
Figure 14.20 Example of Cascaded Operation (2)
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.4.5
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0-, 1-, or toggle-output can be selected as the output level in response to compare match of each TGR. Settings of TGR registers can output a PWM waveform in the range of 0% to 100% duty cycle. Designating TGR compare match as the counter clearing source enables the cycle to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. 1. PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. 2. PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty cycle registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronous register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation.
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Section 14 16-Bit Timer Pulse Unit (TPU)
The correspondence between PWM output pins and registers is shown in table 14.48. Table 14.48 PWM Output Registers and Output Pins
Output Pins Channel 0 Registers TGRA_0 TGRB_0 TGRC_0 TGRD_0 1 TGRA_1 TGRB_1 2 TGRA_2 TGRB_2 3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 4 TGRA_4 TGRB_4 5 TGRA_5 TGRB_5 TIOCA5 TIOCA4 TIOCC3 TIOCA3 TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set.
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Section 14 16-Bit Timer Pulse Unit (TPU)
(1)
Example of PWM Mode Setting Procedure
Figure 14.21 shows an example of the PWM mode setting procedure.
[1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in Select counter clock [1] TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. [3] Use TIOR to designate TGR as an output Select waveform output level [3] compare register, and select the initial value and output value. Set TGR [4] [4] Set the cycle in TGR selected in [2], and set the duty in the other TGRs. Set PWM mode [5] [5] Select the PWM mode with bits MD3 to MD0 in TMDR. [6] Set the CST bit in TSTR to 1 to start the count operation.
PWM mode
Select counter clearing source
[2]
Start count
[6]

Figure 14.21 Example of PWM Mode Setting Procedure
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Section 14 16-Bit Timer Pulse Unit (TPU)
(2)
Examples of PWM Mode Operation
Figure 14.22 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the cycle, and the value set in TGRB register as the duty cycle.
TCNT value TGRA Counter cleared by TGRA compare match
TGRB H'0000 TIOCA Time
Figure 14.22 Example of PWM Mode Operation (1) Figure 14.23 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase PWM waveform. In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as the duty cycle.
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Section 14 16-Bit Timer Pulse Unit (TPU)
TCNT value TGRB_1 TGRA_1 TGRD_0 TGRC_0 TGRB_0 TGRA_0 H'0000 TIOCA0
Counter cleared by TGRB_1 compare match
Time
TIOCB0
TIOCC0 TIOCD0 TIOCA1
Figure 14.23 Example of PWM Mode Operation (2)
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Section 14 16-Bit Timer Pulse Unit (TPU)
Figure 14.24 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle in PWM mode.
TCNT value TGRB changed TGRA
TGRB H'0000
TGRB changed
TGRB changed Time
TIOCA
0% duty
TCNT value TGRB changed TGRA
Output does not change when compare matches in cycle register and duty register occur simultaneously
TGRB changed TGRB H'0000 100% duty TGRB changed Time
TIOCA
TCNT value TGRB changed TGRA
Output does not change when compare matches in cycle register and duty register occur simultaneously
TGRB changed
TGRB H'0000 100% duty 0% duty
TGRB changed Time
TIOCA
Figure 14.24 Example of PWM Mode Operation (3)
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.4.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 14.49 shows the correspondence between external clock pins and channels. Table 14.49 Clock Input Pins in Phase Counting Mode
External Clock Pins Channels When channel 1 or 5 is set to phase counting mode When channel 2 or 4 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD
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Section 14 16-Bit Timer Pulse Unit (TPU)
(1)
Example of Phase Counting Mode Setting Procedure
Figure 14.25 shows an example of the phase counting mode setting procedure.
Phase counting mode
Select phase counting mode
[1]
Start count
[2]
[1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation.

Figure 14.25 Example of Phase Counting Mode Setting Procedure
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Section 14 16-Bit Timer Pulse Unit (TPU)
(2)
Examples of Phase Counting Mode Operation
In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. (a) Phase Counting Mode 1
Figure 14.26 shows an example of phase counting mode 1 operation, and table 14.50 summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value
Up-count
Down-count
Time
Figure 14.26 Example of Phase Counting Mode 1 Operation Table 14.50 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Down-count TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count
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Section 14 16-Bit Timer Pulse Unit (TPU)
(b)
Phase Counting Mode 2
Figure 14.27 shows an example of phase counting mode 2 operation, and table 14.51 summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count
Time
Figure 14.27 Example of Phase Counting Mode 2 Operation Table 14.51 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count
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Section 14 16-Bit Timer Pulse Unit (TPU)
(c)
Phase Counting Mode 3
Figure 14.28 shows an example of phase counting mode 3 operation, and table 14.52 summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value
Up-count
Down-count
Time
Figure 14.28 Example of Phase Counting Mode 3 Operation Table 14.52 Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care
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Section 14 16-Bit Timer Pulse Unit (TPU)
(d)
Phase Counting Mode 4
Figure 14.29 shows an example of phase counting mode 4 operation, and table 14.53 summarizes the TCNT up/down-count conditions.
TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value
Up-count
Down-count
Time
Figure 14.29 Example of Phase Counting Mode 4 Operation Table 14.53 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level [Legend] : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count
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Section 14 16-Bit Timer Pulse Unit (TPU)
(3)
Phase Counting Mode Application Example
Figure 14.30 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and TGRC_0 are used for the compare match function and are set with the speed control cycle and position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture source, and the pulse width of 2-phase encoder 4-multiplication pulses is detected. TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and TGRC_0 compare matches are selected as the input capture source, and the up/down-counter values for the control cycles are stored. This procedure enables accurate position/speed detection to be achieved.
Channel 1 TCLKA TCLKB Edge detection circuit TCNT_1 TGRA_1 (speed cycle capture) TGRB_1 (position cycle capture)
TCNT_0 TGRA_0 (speed control cycle) TGRC_0 (position control cycle) TGRB_0 (pulse width capture) TGRD_0 (buffer operation) Channel 0 + + -
Figure 14.30 Phase Counting Mode Application Example
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.5
Interrupt Sources
There are three kinds of TPU interrupt sources: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priority levels can be changed by the interrupt controller, but the priority within a channel is fixed. For details, see section 7, Interrupt Controller. Table 14.54 lists the TPU interrupt sources. Table 14.54 TPU Interrupts
Channel 0 Name TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U Interrupt Source TGRA_0 input capture/compare match TGRB_0 input capture/compare match TGRC_0 input capture/compare match TGRD_0 input capture/compare match TCNT_0 overflow TGRA_1 input capture/compare match TGRB_1 input capture/compare match TCNT_1 overflow TCNT_1 underflow TGRA_2 input capture/compare match TGRB_2 input capture/compare match TCNT_2 overflow TCNT_2 underflow Interrupt Flag TGFA_0 TGFB_0 TGFC_0 TGFD_0 TCFV_0 TGFA_1 TGFB_1 TCFV_1 TCFU_1 TGFA_2 TGFB_2 TCFV_2 TCFU_2 DTC Activation Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible DMAC Activation Possible Not possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Possible Not possible Not possible Not possible
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Section 14 16-Bit Timer Pulse Unit (TPU)
Channel 3
Name TGI3A TGI3B TGI3C TGI3D TCI3V
Interrupt Source TGRA_3 input capture/compare match TGRB_3 input capture/compare match TGRC_3 input capture/compare match TGRD_3 input capture/compare match TCNT_3 overflow TGRA_4 input capture/compare match TGRB_4 input capture/compare match TCNT_4 overflow TCNT_4 underflow TGRA_5 input capture/compare match TGRB_5 input capture/compare match TCNT_5 overflow TCNT_5 underflow
Interrupt Flag TGFA_3 TGFB_3 TGFC_3 TGFD_3 TCFV_3 TGFA_4 TGFB_4 TCFV_4 TCFU_4 TGFA_5 TGFB_5 TCFV_5 TCFU_5
DTC Activation Possible Possible Possible Possible Not possible Possible Possible Not possible Not possible Possible Possible Not possible Not possible
DMAC Activation Possible Not possible Not possible Not possible Not possible Possible Not possible Not possible Not possible Possible Not possible Not possible Not possible
4
TGI4A TGI4B TCI4V TCI4U
5
TGI5A TGI5B TCI5V TCI5U
Note: This table shows the initial state immediately after a reset. The relative channel priority levels can be changed by the interrupt controller.
(1)
Input Capture/Compare Match Interrupt
An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. (2) Overflow Interrupt
An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of a TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. (3) Underflow Interrupt
An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of a TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5.
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.6
DTC Activation
The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 12, Data Transfer Controller (DTC). A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
14.7
DMAC Activation
The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel. For details, see section 10, DMA Controller (DMAC). In TPU, one in each channel, totally six TGRA input capture/compare match interrupts can be used as DMAC activation sources.
14.8
A/D Converter Activation
Concerning the unit 0 in TPU, the TGRA input capture/compare match for each channel can activate the A/D converter. (However, the A/D converter cannot be activated in unit 1.) If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel.
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.9
14.9.1 (1)
Operation Timing
Input/Output Timing
TCNT Count Timing
Figure 14.31 shows TCNT count timing in internal clock operation, and figure 14.32 shows TCNT count timing in external clock operation.
P
Internal clock
Falling edge
Rising edge
Falling edge
TCNT input clock TCNT N-1 N N+1 N+2
Figure 14.31 Count Timing in Internal Clock Operation
P
External clock
Falling edge
Rising edge
Falling edge
TCNT input clock TCNT N-1 N N+1 N+2
Figure 14.32 Count Timing in External Clock Operation
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Section 14 16-Bit Timer Pulse Unit (TPU)
(2)
Output Compare Output Timing
A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin (TIOC pin). After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 14.33 shows output compare output timing.
P TCNT input clock TCNT TGR Compare match signal TIOC pin N N N+1
Figure 14.33 Output Compare Output Timing (3) Input Capture Signal Timing
Figure 14.34 shows input capture signal timing.
P Input capture input Input capture signal TCNT N N+1 N N+2 N+2
TGR
Figure 14.34 Input Capture Input Signal Timing
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Section 14 16-Bit Timer Pulse Unit (TPU)
(4)
Timing for Counter Clearing by Compare Match/Input Capture
Figure 14.35 shows the timing when counter clearing by compare match occurrence is specified, and figure 14.36 shows the timing when counter clearing by input capture occurrence is specified.
P Compare match signal Counter clear signal TCNT TGR N N H'0000
Figure 14.35 Counter Clear Timing (Compare Match)
P Input capture signal Counter clear signal TCNT N H'0000
TGR
N
Figure 14.36 Counter Clear Timing (Input Capture)
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Section 14 16-Bit Timer Pulse Unit (TPU)
(5)
Buffer Operation Timing
Figures 14.37 and 14.38 show the timings in buffer operation.
P TCNT Compare match signal TGRA, TGRB n N n+1
n
TGRC, TGRD
N
Figure 14.37 Buffer Operation Timing (Compare Match)
P Input capture signal TCNT N N+1
TGRA, TGRB
n
N
N+1
TGRC, TGRD
n
N
Figure 14.38 Buffer Operation Timing (Input Capture)
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.9.2 (1)
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match
Figure 14.39 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing.
P TCNT input clock TCNT N N+1
TGR Compare match signal TGF flag
N
TGI interrupt
Figure 14.39 TGI Interrupt Timing (Compare Match) (2) TGF Flag Setting Timing in Case of Input Capture
Figure 14.40 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing.
P Input capture signal TCNT N
TGR
N
TGF flag TGI interrupt
Figure 14.40 TGI Interrupt Timing (Input Capture)
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Section 14 16-Bit Timer Pulse Unit (TPU)
(3)
TCFV Flag/TCFU Flag Setting Timing
Figure 14.41 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing. Figure 14.42 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and the TCIU interrupt request signal timing.
P TCNT input clock TCNT (overflow) Overflow signal TCFV flag TCIV interrupt H'FFFF H'0000
Figure 14.41 TCIV Interrupt Setting Timing
P TCNT input clock TCNT (underflow) Underflow signal TCFU flag TCIU interrupt H'0000 H'FFFF
Figure 14.42 TCIU Interrupt Setting Timing
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Section 14 16-Bit Timer Pulse Unit (TPU)
(4)
Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 14.43 shows the timing for status flag clearing by the CPU, and figures 14.44 and 14.45 show the timing for status flag clearing by the DTC or DMAC.
TSR write cycle T1 T2 P Address TSR address
Write Status flag Interrupt request signal
Figure 14.43 Timing for Status Flag Clearing by CPU The status flag and interrupt request signal are cleared in synchronization with P after the DTC or DMAC transfer has started, as shown in figure 14.44. If conflict occurs for clearing the status flag and interrupt request signal due to activation of multiple DTC or DMAC transfers, it will take up to five clock cycles (P) for clearing them, as shown in figure 14.45. The next transfer request is masked for a longer period of either a period until the current transfer ends or a period for five clock cycles (P) from the beginning of the transfer. Note that in the DTC transfer, the status flag may be cleared during outputting the destination address.
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Section 14 16-Bit Timer Pulse Unit (TPU)
DTC/DMAC read cycle T2 T1 P Source address
DTC/DMAC write cycle T1 T2
Address
Destination address
Status flag Period in which the next transfer request is masked Interrupt request signal
Figure 14.44 Timing for Status Flag Clearing by DTC/DMAC Activation (1)
DTC/DMAC read cycle P Address Source address Period in which the next transfer request is masked Status flag Interrupt request signal Period of flag clearing Destination address DTC/DMAC write cycle
Period of interrupt request signal clearing
Figure 14.45 Timing for Status Flag Clearing by DTC/DMAC Activation (2)
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.10
Usage Notes
14.10.1 Module Stop Function Setting Operation of the TPU can be disabled or enabled using the module stop control register. The initial setting is for operation of the TPU to be halted. Register access is enabled by clearing the module stop state. For details, see section 27, Power-Down Modes. 14.10.2 Input Clock Restrictions The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 14.46 shows the input clock conditions in phase counting mode.
Phase Phase difference difference Overlap Overlap TCLKA (TCLKC) TCLKB (TCLKD) Pulse width Note: Phase difference, Overlap 1.5 states Pulse width 2.5 states Pulse width
Pulse width
Pulse width
Figure 14.46 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.10.3 Caution on Cycle Setting When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula:
f=
f:
P (N + 1)
Counter frequency
P: Operating frequency N: TGR set value
14.10.4 Conflict between TCNT Write and Clear Operations If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 14.47 shows the timing in this case.
TCNT write cycle T1 T2 P Address Write Counter clear signal TCNT N H'0000 TCNT address
Figure 14.47 Conflict between TCNT Write and Clear Operations
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.10.5 Conflict between TCNT Write and Increment Operations If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 14.48 shows the timing in this case.
TCNT write cycle T1 T2 P Address Write TCNT input clock TCNT N TCNT write data M TCNT address
Figure 14.48 Conflict between TCNT Write and Increment Operations 14.10.6 Conflict between TGR Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is disabled. A compare match also does not occur when the same value as before is written. Figure 14.49 shows the timing in this case.
TGR write cycle T2 T1 P Address Write Compare match signal TCNT TGR N N TGR write data Disabled N+1 M TGR address
Figure 14.49 Conflict between TGR Write and Compare Match
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.10.7 Conflict between Buffer Register Write and Compare Match If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the write data. Figure 14.50 shows the timing in this case.
TGR write cycle T1 T2 P Address Write Compare match signal Buffer register TGR N Data written to buffer register
Buffer register address
M M
Figure 14.50 Conflict between Buffer Register Write and Compare Match 14.10.8 Conflict between TGR Read and Input Capture If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 14.51 shows the timing in this case.
TGR read cycle T2 T1 P Address Read Input capture signal TGR Internal data bus X M M TGR address
Figure 14.51 Conflict between TGR Read and Input Capture
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.10.9 Conflict between TGR Write and Input Capture If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 14.52 shows the timing in this case.
TGR write cycle T2 T1 P Address Write Input capture signal TCNT M TGR address
TGR
M
Figure 14.52 Conflict between TGR Write and Input Capture
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.10.10 Conflict between Buffer Register Write and Input Capture If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 14.53 shows the timing in this case.
Buffer register write cycle T1 T2 P Address Write Input capture signal TCNT TGR Buffer register M N N M
Buffer register address
Figure 14.53 Conflict between Buffer Register Write and Input Capture
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.10.11 Conflict between Overflow/Underflow and Counter Clearing If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 14.54 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR.
P TCNT input clock TCNT Counter clear signal TGF flag TCFV flag Disabled H'FFFF H'0000
Figure 14.54 Conflict between Overflow and Counter Clearing 14.10.12 Conflict between TCNT Write and Overflow/Underflow If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 14.55 shows the operation timing when there is conflict between TCNT write and overflow.
TGR write cycle T2 T1 P Address Write signal TCNT TCFV flag H'FFFF M TCNT address TCNT write data
Figure 14.55 Conflict between TCNT Write and Overflow
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Section 14 16-Bit Timer Pulse Unit (TPU)
14.10.13 Multiplexing of I/O Pins In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. 14.10.14 Interrupts in the Module Stop State If the module stop state is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source, or the DTC or DMAC activation source. Interrupts should therefore be disabled before entering the module stop state.
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Section 14 16-Bit Timer Pulse Unit (TPU)
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Section 15 Programmable Pulse Generator (PPG)
Section 15 Programmable Pulse Generator (PPG)
The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 7 to 4 and 1 to 0) that can operate both simultaneously and independently. Figures 15.1 and 15.2 show a block diagram of the PPG.
15.1
* * * * * * *
Features
28-bit output data Four output groups Selectable output trigger signals Non-overlapping mode Can operate together with the data transfer controller (DTC) and DMA controller (DMAC) Inverted output can be set Module stop state specifiable
Table 15.1 List of PPG Functions
Function PPG output trigger TPU0 Compare match Input capture TPU1 Compare match Input capture Non-overlapping mode Output data transfer DTC DMAC Inverted output PPG0 Possible Possible Not possible Not possible Possible Possible Possible Possible PPG1 Not possible Not possible Possible Not possible Possible Possible Possible Possible
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Section 15 Programmable Pulse Generator (PPG)
Compare match signals
NDERH Control logic PMR
NDERL PCR
PODRH
NDRH
Internal data bus
PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 [Legend] PMR: PCR: NDERH: NDERL:
Pulse output pins, group 1 PODRL Pulse output pins, group 0 NDRL
PPG output mode register PPG output control register Next data enable register H Next data enable register L
NDRH: NDRL: PODRH: PODRL:
Next data register H Next data register L Output data register H Output data register L
Figure 15.1 Block Diagram of PPG (Unit 0)
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Section 15 Programmable Pulse Generator (PPG)
Compare match signals
NDERH_1 Control logic PMR_1
NDERL_1 PCR_1
PO31 PO30 PO29 PO28 PO27 PO26 PO25 PO24 PO23 PO22 PO21 PO20 PO19 PO18 PO17 PO16 [Legend] PMR_1: PCR_1: NDERH_1: NDERL_1:
Pulse output pins, group 7 PODRH_1 Pulse output pins, group 6 Pulse output pins, group 5 PODRL_1 Pulse output pins, group 4 NDRL_1 NDRH_1
Internal data bus
PPG output mode register_1 PPG output control register_1 Next data enable register H_1 Next data enable register L_1
NDRH_1: NDRL_1: PODRH_1: PODRL_1:
Next data register H_1 Next data register L_1 Output data register H_1 Output data register L_1
Figure 15.2 Block Diagram of PPG (Unit 1)
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Section 15 Programmable Pulse Generator (PPG)
15.2
Input/Output Pins
Table 15.2 shows the PPG pin configuration. Table 15.2 Pin Configuration
Unit 0 Pin Name PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7 1 PO16 PO17 PO18 PO19 PO20 PO21 PO22 PO23 PO24 PO25 PO26 PO27 PO28 PO29 PO30 PO31 I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Group 7 pulse output Group 6 pulse output Group 5 pulse output Group 4 pulse output Group 1 pulse output Function Group 0 pulse output
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Section 15 Programmable Pulse Generator (PPG)
15.3
Register Descriptions
The PPG has the following registers. Unit 0: * * * * * * * * Next data enable register H (NDERH) Next data enable register L (NDERL) Output data register H (PODRH) Output data register L (PODRL) Next data register H (NDRH) Next data register L (NDRL) PPG output control register (PCR) PPG output mode register (PMR)
Unit 1: * * * * * * * * Next data enable register H_1 (NDERH_1) Next data enable register L_1 (NDERL_1) Output data register H_1 (PODRH_1) Output data register L_1 (PODRL_1) Next data register H_1 (NDRH_1) Next data register L_1 (NDRL_1) PPG output control register_1 (PCR_1) PPG output mode register_1 (PMR_1)
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Section 15 Programmable Pulse Generator (PPG)
15.3.1
Next Data Enable Registers H, L (NDERH, NDERL)
NDERH and NDERL enable/disable pulse output on a bit-by-bit basis. * NDERH
Bit Bit Name Initial Value R/W 7 NDER15 0 R/W 6 NDER14 0 R/W 5 NDER13 0 R/W 4 NDER12 0 R/W 3 NDER11 0 R/W 2 NDER10 0 R/W 1 NDER9 0 R/W 0 NDER8 0 R/W
* NDERL
Bit Bit Name Initial Value R/W 7 NDER7 0 R/W 6 NDER6 0 R/W 5 NDER5 0 R/W 4 NDER4 0 R/W 3 NDER3 0 R/W 2 NDER2 0 R/W 1 NDER1 0 R/W 0 NDER0 0 R/W
* NDERH
Bit 7 6 5 4 3 2 1 0 Bit Name NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 15 to 8 These are read-only bits and cannot be modified.
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Section 15 Programmable Pulse Generator (PPG)
* NDERL
Bit 7 6 5 4 3 2 1 0 Bit Name NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 7 to 0 When a bit is set to 1, the value in the corresponding NDRL bit is transferred to the PODRL bit by the selected output trigger. Values are not transferred from NDRL to PODRL for cleared bits.
* NDERH_1
Bit 7 6 5 4 3 2 1 0 Bit Name NDER31 NDER30 NDER29 NDER28 NDER27 NDER26 NDER25 NDER24 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 31 to 24 When a bit is set to 1, the value in the corresponding NDRH_1 bit is transferred to the PODRH_1 bit by the selected output trigger. Values are not transferred from NDRH_1 to PODRH_1 for cleared bits.
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Section 15 Programmable Pulse Generator (PPG)
* NDERL_1
Bit 7 6 5 4 3 2 1 0 Bit Name NDER23 NDER22 NDER21 NDER20 NDER19 NDER18 NDER17 NDER16 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Enable 23 to 16 When a bit is set to 1, the value in the corresponding NDRL_1 bit is transferred to the PODRL_1 bit by the selected output trigger. Values are not transferred from NDRL_1 to PODRL_1 for cleared bits.
15.3.2
Output Data Registers H, L (PODRH, PODRL)
PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse output by NDER is read-only and cannot be modified. * PODRH
Bit Bit Name Initial Value R/W 7 POD15 0 R/W 6 POD14 0 R/W 5 POD13 0 R/W 4 POD12 0 R/W 3 POD11 0 R/W 2 POD10 0 R/W 1 POD9 0 R/W 0 POD8 0 R/W
* PODRL
Bit Bit Name Initial Value R/W 7 POD7 0 R/W 6 POD6 0 R/W 5 POD5 0 R/W 4 POD4 0 R/W 3 POD3 0 R/W 2 POD2 0 R/W 1 POD1 0 R/W 0 POD0 0 R/W
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Section 15 Programmable Pulse Generator (PPG)
* PODRH
Bit 7 6 5 4 3 2 1 0 Bit Name POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 15 to 8 These are read-only bits and cannot be modified.
* PODRL
Bit 7 6 5 4 3 2 1 0 Bit Name POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 7 to 0 For bits which have been set to pulse output by NDERL, the output trigger transfers NDRL values to this register during PPG operation. While NDERL is set to 1, the CPU cannot write to this register. While NDERL is cleared, the initial output value of the pulse can be set.
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Section 15 Programmable Pulse Generator (PPG)
* PODRH_1
Bit 7 6 5 4 3 2 1 0 Bit Name POD31 POD30 POD29 POD28 POD27 POD26 POD25 POD24 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 31 to 24 For bits which have been set to pulse output by NDERH_1, the output trigger transfers NDRH_1 values to this register during PPG operation. While NDERH_1 is set to 1, the CPU cannot write to this register. While NDERH_1 is cleared, the initial output value of the pulse can be set.
* PODRL_1
Bit 7 6 5 4 3 2 1 0 Bit Name POD23 POD22 POD21 POD20 POD19 POD18 POD17 POD16 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Output Data Register 23 to 16 For bits which have been set to pulse output by NDERL_1, the output trigger transfers NDRL_1 values to this register during PPG operation. While NDERL_1 is set to 1, the CPU cannot write to this register. While NDERL_1 is cleared, the initial output value of the pulse can be set.
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Section 15 Programmable Pulse Generator (PPG)
15.3.3
Next Data Registers H, L (NDRH, NDRL)
NDRH and NDRL store the next data for pulse output. The NDR addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. * NDRH
Bit Bit Name Initial Value R/W 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W
* NDRL
Bit Bit Name Initial Value R/W 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W
* NDRH If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below.
Bit 7 6 5 4 3 2 1 0 Bit Name NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 15 to 8 These are read-only bits and cannot be modified.
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Section 15 Programmable Pulse Generator (PPG)
* NDRL If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below.
Bit 7 6 5 4 3 2 1 0 Bit Name NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 7 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR.
If pulse output groups 0 and 1 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below.
Bit 7 6 5 4 3 to 0 Bit Name NDR7 NDR6 NDR5 NDR4 Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W Description Next Data Register 7 to 4 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR. Reserved These bits are always read as 1 and cannot be modified.
Bit 7 to 4 3 2 1 0
Bit Name NDR3 NDR2 NDR1 NDR0
Initial Value All 1 0 0 0 0
R/W R/W R/W R/W R/W
Description Reserved These bits are always read as 1 and cannot be modified. Next Data Register 3 to 0 The register contents are transferred to the corresponding PODRL bits by the output trigger specified with PCR.
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Section 15 Programmable Pulse Generator (PPG)
* NDRH_1 If pulse output groups 6 and 7 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below.
Bit 7 6 5 4 3 2 1 0 Bit Name NDR31 NDR30 NDR29 NDR28 NDR27 NDR26 NDR25 NDR24 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 31 to 24 The register contents are transferred to the corresponding PODRH_1 bits by the output trigger specified with PCR_1.
If pulse output groups 6 and 7 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below.
Bit 7 6 5 4 3 to 0 Bit Name NDR31 NDR30 NDR29 NDR28 Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W Description Next Data Register 31 to 28 The register contents are transferred to the corresponding PODRH_1 bits by the output trigger specified with PCR_1. Reserved These bits are always read as 1 and cannot be modified.
Bit 7 to 4 3 2 1 0
Bit Name NDR27 NDR26 NDR25 NDR24
Initial Value All 1 0 0 0 0
R/W R/W R/W R/W R/W
Description Reserved These bits are always read as 1 and cannot be modified. Next Data Register 27 to 24 The register contents are transferred to the corresponding PODRH_1 bits by the output trigger specified with PCR_1.
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Section 15 Programmable Pulse Generator (PPG)
* NDRL_1 If pulse output groups 4 and 5 have the same output trigger, all eight bits are mapped to the same address and can be accessed at one time, as shown below.
Bit 7 6 5 4 3 2 1 0 Bit Name NDR23 NDR22 NDR21 NDR20 NDR19 NDR18 NDR17 NDR16 Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Next Data Register 23 to 16 The register contents are transferred to the corresponding PODRL_1 bits by the output trigger specified with PCR_1.
If pulse output groups 4 and 5 have different output triggers, the upper four bits and lower four bits are mapped to different addresses as shown below.
Bit 7 6 5 4 3 to 0 Bit Name NDR23 NDR22 NDR21 NDR20 Initial Value 0 0 0 0 All 1 R/W R/W R/W R/W R/W Description Next Data Register 23 to 20 The register contents are transferred to the corresponding PODRL_1 bits by the output trigger specified with PCR_1. Reserved These bits are always read as 1 and cannot be modified.
Bit 7 to 4 3 2 1 0
Bit Name NDR19 NDR18 NDR17 NDR16
Initial Value All 1 0 0 0 0
R/W R/W R/W R/W R/W
Description Reserved These bits are always read as 1 and cannot be modified. Next Data Register 19 to 16 The register contents are transferred to the corresponding PODRL_1 bits by the output trigger specified with PCR_1.
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Section 15 Programmable Pulse Generator (PPG)
15.3.4
PPG Output Control Register (PCR)
PCR selects output trigger signals on a group-by-group basis. For details on output trigger selection, refer to section 15.3.5, PPG Output Mode Register (PMR).
Bit Bit Name Initial Value R/W 7 G3CMS1 1 R/W 6 G3CMS0 1 R/W 5 G2CMS1 1 R/W 4 G2CMS0 1 R/W 3 G1CMS1 1 R/W 2 G1CMS0 1 R/W 1 G0CMS1 1 R/W 0 G0CMS0 1 R/W
Bit 7 6 5 4 3 2
Bit Name G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0
Initial Value 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W
Description Group 3 Compare Match Select 1 and 0 These are read-only bits and cannot be modified. Group 2 Compare Match Select 1 and 0 These are read-only bits and cannot be modified. Group 1 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 1. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3
1 0
G0CMS1 G0CMS0
1 1
R/W R/W
Group 0 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 0. 00: Compare match in TPU channel 0 01: Compare match in TPU channel 1 10: Compare match in TPU channel 2 11: Compare match in TPU channel 3
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Section 15 Programmable Pulse Generator (PPG)
* PCR_1
Bit 7 6 Bit Name G3CMS1 G3CMS0 Initial Value 1 1 R/W R/W R/W Description Group 7 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 7. 00: Compare match in TPU channel 6 01: Compare match in TPU channel 7 10: Compare match in TPU channel 8 11: Compare match in TPU channel 9 5 4 G2CMS1 G2CMS0 1 1 R/W R/W Group 6 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 6. 00: Compare match in TPU channel 6 01: Compare match in TPU channel 7 10: Compare match in TPU channel 8 11: Compare match in TPU channel 9 3 2 G1CMS1 G1CMS0 1 1 R/W R/W Group 5 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 5. 00: Compare match in TPU channel 6 01: Compare match in TPU channel 7 10: Compare match in TPU channel 8 11: Compare match in TPU channel 9 1 0 G0CMS1 G0CMS0 1 1 R/W R/W Group 4 Compare Match Select 1 and 0 These bits select output trigger of pulse output group 4. 00: Compare match in TPU channel 6 01: Compare match in TPU channel 7 10: Compare match in TPU channel 8 11: Compare match in TPU channel 9
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Section 15 Programmable Pulse Generator (PPG)
15.3.5
PPG Output Mode Register (PMR)
PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If non-overlapping operation is selected, PPG updates its output values at compare match A or B of the TPU that becomes the output trigger. For details, refer to section 15.4.4, Non-Overlapping Pulse Output.
Bit Bit Name Initial Value R/W 7 G3INV 1 R/W 6 G2INV 1 R/W 5 G1INV 1 R/W 4 G0INV 1 R/W 3 G3NOV 0 R/W 2 G2NOV 0 R/W 1 G1NOV 0 R/W 0 G0NOV 0 R/W
Bit 7 6 5
Bit Name G3INV G2INV G1INV
Initial Value 1 1 1
R/W R/W R/W R/W
Description Group 3 Inversion These are read-only bits and cannot be modified. Group 2 Inversion These are read-only bits and cannot be modified. Group 1 Inversion Selects direct output or inverted output for pulse output group 1. 0: Inverted output 1: Direct output
4
G0INV
1
R/W
Group 0 Inversion Selects direct output or inverted output for pulse output group 0. 0: Inverted output 1: Direct output
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Section 15 Programmable Pulse Generator (PPG)
Bit 3 2 1
Bit Name G3NOV G2NOV G1NOV
Initial Value 0 0 0
R/W R/W R/W R/W
Description Group 3 Non-Overlap These are read-only bits and cannot be modified. Group 2 Non-Overlap These are read-only bits and cannot be modified. Group 1 Non-Overlap Selects normal or non-overlapping operation for pulse output group 1. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel)
0
G0NOV
0
R/W
Group 0 Non-Overlap Selects normal or non-overlapping operation for pulse output group 0. 0: Normal operation (output values updated at compare match A in the selected TPU channel) 1: Non-overlapping operation (output values updated at compare match A or B in the selected TPU channel)
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Section 15 Programmable Pulse Generator (PPG)
* PMR_1
Bit 7 Bit Name G3INV Initial Value 1 R/W R/W Description Group 7 Inversion Selects direct output or inverted output for pulse output group 7.. 0: Inverted output 1: Direct output 6 G2INV 1 R/W Group 6 Inversion Selects direct output or inverted output for pulse output group 6. 0: Inverted output 1: Direct output 5 G1INV 1 R/W Group 5 Inversion Selects direct output or inverted output for pulse output group 5. 0: Inverted output 1: Direct output 4 G0INV 1 R/W Group 4 Inversion Selects direct output or inverted output for pulse output group 4. 0: Inverted output 1: Direct output
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Section 15 Programmable Pulse Generator (PPG)
Bit 3
Bit Name G3NOV
Initial Value 0
R/W R/W
Description Group 7 Non-Overlap Selects normal or non-overlapping operation for pulse output group 7. 0: Normal operation (output values updated by compare match A on the selected TPU channel) 1: Non-overlapping operation (output values updated by compare match A or B on the selected TPU channel)
2
G2NOV
0
R/W
Group 6 Non-Overlap Selects normal or non-overlapping operation for pulse output group 6. 0: Normal operation (output values updated by compare match A on the selected TPU channel) 1: Non-overlapping operation (output values updated by compare match A or B on the selected TPU channel)
1
G1NOV
0
R/W
Group 5 Non-Overlap Selects normal or non-overlapping operation for pulse output group 5. 0: Normal operation (output values updated by compare match A on the selected TPU channel) 1: Non-overlapping operation (output values updated by compare match A or B on the selected TPU channel)
0
G0NOV
0
R/W
Group 4 Non-Overlap Selects normal or non-overlapping operation for pulse output group 4. 0: Normal operation (output values updated by compare match A on the selected TPU channel) 1: Non-overlapping operation (output values updated by compare match A or B on the selected TPU channel)
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Section 15 Programmable Pulse Generator (PPG)
15.4
Operation
Figure 15.3 shows a schematic diagram of the PPG. PPG pulse output is enabled when the corresponding bits in NDER are set to 1. An initial output value is determined by its corresponding PODR initial setting. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Sequential output of data of up to 8 bits from unit 0 or 16 bits from unit 1 is possible by writing new output data to NDR before the next compare match.
NDER Q Output trigger signal
C Q PODR D Pulse output pin Normal output/inverted output Q NDR D Internal data bus
Figure 15.3 Schematic Diagram of PPG 15.4.1 Output Timing
If pulse output is enabled, the NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 15.4 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A.
P TCNT TGRA Compare match A signal NDRH PODRH PO8 to PO15 m m n n n N N N+1
Figure 15.4 Timing of Transfer and Output of NDR Contents (Example)
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Section 15 Programmable Pulse Generator (PPG)
15.4.2
Sample Setup Procedure for Normal Pulse Output
Figures 15.5 and 15.6 show a sample procedure for setting up normal pulse output. * Sample Setup Procedure for PPG0
Normal PPG output Select TGR functions Set TGRA value TPU0 setup Set counting operation Select interrupt request Set initial output data Enable pulse output PPG0 setup Select output trigger Set next pulse output data TPU0 setup Start counter Compare match? Yes Set next pulse output data [10] [7] [7] [8] [9] [9] No [3] [4] [5] [5] [6] [6] [4] [1] [2] [1] Set TIOR in TPU0 to make TGRA an output compare register (with output disabled). Set the PPG output trigger cycle. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. Set the initial output values in PODR. Set the bits in NDER for the pins to be used for pulse output to 1. Select the TPU compare match event to be used as the output trigger in PCR. Set the next pulse output values in NDR. Set the CST bit in TSTR to 1 to start the TCNT counter.
[2] [3]
[8]
[10] At each TGIA interrupt, set the next
Figure 15.5 Setup Procedure for Normal Pulse Output (PPG0)
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Section 15 Programmable Pulse Generator (PPG)
* Sample Setup Procedure for PPG1
Normal PPG output Select TGR functions Set TGRA value TPU1 setup Set counting operation Select interrupt request Set initial output data Enable pulse output PPG1 setup Select output trigger Set next pulse output data TPU1 setup Start counter Compare match? Yes Set next pulse output data [10] [7] [3] [4] [4] [5] [6] [5] [6] [7] [8] [9] [9] No [1] [2] [1] [2] [3] Set TIOR in TPU1 to make TGRA an output compare register (toggle output). Set the PPG output trigger cycle. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. Set the initial output values in PODR. Set the bits in NDER for the pins to be used for pulse output to 1. Select the TPU compare match event to be used as the output trigger in PCR. Set the next pulse output values in NDR. Set the CST bit in TSTR to 1 to start the TCNT counter.
[8]
[10] At each TGIA interrupt, set the next output values in NDR.
Figure 15.6 Setup Procedure for Normal Pulse Output (PPG1)
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Section 15 Programmable Pulse Generator (PPG)
15.4.3
Example of Normal Pulse Output (Example of 5-Phase Pulse Output)
Figure 15.7 shows an example in which pulse output is used for cyclic 5-phase pulse output.
TCNT value TGRA TCNT Compare match
H'0000 NDRH 80 C0 40 60 20 30 10 18 08 88 80 C0 40
Time
PODRH
00
80
C0
40
60
20
30
10
18
08
88
80
C0
PO15 PO14
PO13
PO12
PO11
Figure 15.7 Normal Pulse Output Example (5-Phase Pulse Output) 1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in TIER to 1 to enable the compare match/input capture A (TGIA) interrupt. 2. Write H'F8 to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. 3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. 4. 5-phase pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC or DMAC is set for activation by the TGIA interrupt, pulse output can be obtained without imposing a load on the CPU.
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Section 15 Programmable Pulse Generator (PPG)
15.4.4
Non-Overlapping Pulse Output
During non-overlapping operation, transfer from NDR to PODR is performed as follows: * At compare match A, the NDR bits are always transferred to PODR. * At compare match B, the NDR bits are transferred only if their value is 0. The NDR bits are not transferred if their value is 1. Figure 15.8 illustrates the non-overlapping pulse output operation.
NDER Q Compare match A Compare match B
Pulse output pin
C Q PODR D
Q NDR D
Internal data bus
Normal output/inverted output
Figure 15.8 Non-Overlapping Pulse Output Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlapping margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next data must be written before the next compare match B occurs.
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Section 15 Programmable Pulse Generator (PPG)
Figure 15.9 shows the timing of this operation.
Compare match A
Compare match B Write to NDR NDR Write to NDR
PODR 0 output 0/1 output 0 output 0/1 output Write to NDR here
Write to NDR Do not write here to NDR here
Do not write to NDR here
Figure 15.9 Non-Overlapping Operation and NDR Write Timing
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Section 15 Programmable Pulse Generator (PPG)
15.4.5
Sample Setup Procedure for Non-Overlapping Pulse Output
Figures 15.10 and 15.11 show a sample procedure for setting up non-overlapping pulse output. * Sample Setup Procedure for PPG0
Non-overlapping pulse output Select TGR functions Set TGR values TPU0 setup Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set non-overlapping groups Set next pulse output data TPU0 setup Start counter Compare match A? Yes Set next pulse output data [11] [3] [4] [4] [5] [6] [7] [8] [7] [5] [6] PPG0 setup [1] [2] [3] [1] Set TIOR in TPU0 to make TGRA and TGRB output compare registers (with output disabled). Set the pulse output trigger cycle in TGRB and the non-overlapping margin in TGRA. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. Set the initial output values in PODR. Set the bits in NDER for the pins to be used for pulse output to 1. Select the TPU compare match event to be used as the pulse output trigger in PCR. In PMR, select the groups that will operate in non-overlapping mode. Set the next pulse output values in NDR.
[2]
[9]
[8] [9]
[10] No
[10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR.
Figure 15.10 Setup Procedure for Non-Overlapping Pulse Output (PPG0)
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Section 15 Programmable Pulse Generator (PPG)
* Sample Setup Procedure for PPG1
Non-overlapping pulse output Select TGR functions Set TGR values TPU1 setup Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set non-overlapping groups Set next pulse output data TPU1 setup Start counter Compare match A? Yes Set next pulse output data [11] [3] [4] [4] [5] [6] [7] [8] [7] [5] [6] PPG1 setup [1] [2] [3] [1] Set TIOR in TPU1 to make TGRA and TGRB output compare registers (toggle output). Set the pulse output trigger cycle in TGRB and the non-overlapping margin in TGRA. Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. Set the initial output values in PODR. Set the bits in NDER for the pins to be used for pulse output to 1. Select the TPU compare match event to be used as the pulse output trigger in PCR. In PMR, select the groups that will operate in non-overlapping mode. Set the next pulse output values in NDR.
[2]
[9]
[8] [9]
[10] No
[10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR.
Figure 15.11 Setup Procedure for Non-Overlapping Pulse Output (PPG1)
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Section 15 Programmable Pulse Generator (PPG)
15.4.6
Example of Non-Overlapping Pulse Output (Example of 4-Phase Complementary Non-Overlapping Pulse Output)
Figure 15.12 shows an example in which pulse output is used for 4-phase complementary nonoverlapping pulse output.
TCNT value TGRB TGRA H'0000 NDRH 95 65 59 56 95 65 Time TCNT
PODRH
00
95
05
65
41
59
50
56
14
95
05
65
Non-overlapping margin PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 15.12 Non-Overlapping Pulse Output Example (4-Phase Complementary)
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Section 15 Programmable Pulse Generator (PPG)
1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the cycle in TGRB and the non-overlapping margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. 2. Write H'FF to NDERH, and set bits G3CMS1, G3CMS0, G2CMS1, and G2CMS0 in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set bits G3NOV and G2NOV in PMR to 1 to select non-overlapping pulse output. Write output data H'95 to NDRH. 3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) to NDRH. 4. 4-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC or DMAC is set for activation by a TGIA interrupt, pulse can be output without imposing a load on the CPU.
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Section 15 Programmable Pulse Generator (PPG)
15.4.7
Inverted Pulse Output
If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 15.13 shows the outputs when the G3INV and G2INV bits are cleared to 0, in addition to the settings of Figure 15.12.
TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time
PODRL
00
95
05
65
41
59
50
56
14
95
05
65
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 15.13 Inverted Pulse Output (Example)
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Section 15 Programmable Pulse Generator (PPG)
15.4.8
Pulse Output Triggered by Input Capture
Pulse output of PPG0 can be triggered by TPU0 input capture as well as by compare match. If TGRA functions as an input capture register in the TPU0 channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 15.14 shows the timing of this output. PPG1 cannot be used to trigger pulse output by input capturer.
P
TIOC pin Input capture signal
NDR
N
PODR
M
N
PO
M
N
Figure 15.14 Pulse Output Triggered by Input Capture (Example)
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Section 15 Programmable Pulse Generator (PPG)
15.5
15.5.1
Usage Notes
Module Stop State Setting
PPG operation can be disabled or enabled using the module stop control register. The initial value is for PPG operation to be halted. Register access is enabled by clearing the module stop state. For details, refer to section 27, Power-Down Modes. 15.5.2 Operation of Pulse Output Pins
Pins PO0 to PO7 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur. 15.5.3 TPU Setting when PPG1 is in Use
When using PPG1, output toggling on compare-matches must be specified in the TIOR register of the TPU that acts as the activation source and output must be selected as the PPG1 function.
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Section 15 Programmable Pulse Generator (PPG)
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Section 16 8-Bit Timers (TMR)
Section 16 8-Bit Timers (TMR)
This LSI has four units (unit 0 to unit 3) of an on-chip 8-bit timer module that comprise two 8-bit counter channels, totaling eight channels. The 8-bit timer module can be used to count external events and also be used as a multifunction timer in a variety of applications, such as generation of counter reset, interrupt requests, and pulse output with a desired duty cycle using a compare-match signal with two registers. Figures 16.1 to 16.4 show block diagrams of the 8-bit timer module (unit 0 to unit 3). This section describes unit 0 (channels 0 and 1) and unit 2 (channels 4 and 5), both of which have the same functions. Unit 2 and unit 3 can generate baud rate clock for SCI and have the same functions.
16.1
Features
* Selection of seven clock sources The counters can be driven by one of six internal clock signals (P/2, P/8, P/32, P/64, P/1024, or P/8192) or an external clock input (only internal clock available in units 2 and 3: P, P/2, P/8, P/32, P/64, P/1024, and P/8192). * Selection of three ways to clear the counters The counters can be cleared on compare match A or B, or by an external reset signal. (This is available only in unit 0 and unit 1.) * Timer output control by a combination of two compare match signals The timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to output pulses with a desired duty cycle or PWM output. * Cascading of two channels Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the lower 8 bits (16-bit count mode). TMR_1 can be used to count TMR_0 compare matches (compare match count mode). * Three interrupt sources Compare match A, compare match B, and overflow interrupts can be requested independently. (This is available only in unit 0 and unit 1.) * Generation of trigger to start A/D converter conversion (available in unit 0 to unit 3) * Capable of generating baud rate clock for SCI_5 and SCI_6. (This is available only in unit 2 and unit 3). For details, see section 18, Serial Communication Interface (SCI, IrDA, CRC). * Module stop state specifiable
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Section 16 8-Bit Timers (TMR)
Internal clocks P/2 P/8 P/32 P/64 P/1024 P/8192 External clocks TMCI0 TMCI1 Clock select TCORA_0 Compare match A1 Compare match A0 Comparator A_0 TCORA_1 Counter clock 1 Counter clock 0
Comparator A_1
TMO0 TMO1
Overflow 1 Overflow 0 Counter clear 0 Counter clear 1 Compare match B1 Compare match B0 Control logic
TCNT_0
TCNT_1
Comparator B_0
Comparator B_1
TMRI0 TMRI1 A/D conversion start request signal*
TCORB_0
TCORB_1
TCSR_0 TCR_0
TCSR_1 TCR_1
TCCR_0 CMIA0 CMIA1 CMIB0 CMIB1 OVI0 OVI1 Interrupt signals [Legend] TCORA_0: TCNT_0: TCORB_0: TCSR_0: TCR_0: TCCR_0: Note: * Time constant register A_0 Timer counter_0 Time constant register B_0 Timer control/status register_0 Timer control register_0 Timer counter control register_0 TCORA_1: TCNT_1: TCORB_1: TCSR_1: TCR_1: TCCR_1: Channel 0 (TMR_0)
TCCR_1 Channel 1 (TMR_1)
Time constant register A_1 Timer counter_1 Time constant register B_1 Timer control/status register_1 Timer control register_1 Timer counter control register_1
For the corresponding A/D converter channels, see section 21, A/D Converter.
Figure 16.1 Block Diagram of 8-Bit Timer Module (Unit 0)
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Internal bus
Section 16 8-Bit Timers (TMR)
Internal clocks P/2 P/8 P/32 P/64 P/1024 P/8192 External clocks TMCI2 TMCI3 Clock select TCORA_2 Compare match A3 Compare match A2 Comparator A_2 TCORA_3 Counter clock 3 Counter clock 2
Comparator A_3
TMO2 TMO3
Overflow 3 Overflow 2 Counter clear 2 Counter clear 3 Compare match B3 Compare match B2 Control logic
TCNT_2
TCNT_3
Internal bus
Comparator B_2
Comparator B_3
TMRI2 TMRI3 A/D conversion start request signal*
TCORB_2
TCORB_3
TCSR_2 TCR_2
TCSR_3 TCR_3
TCCR_2 CMIA2 CMIA3 CMIB2 CMIB3 OVI2 OVI3 Interrupt signals [Legend] TCORA_2: TCNT_2: TCORB_2: TCSR_2: TCR_2: TCCR_2: Note: * Channel 2 (TMR_2)
TCCR_3 Channel 3 (TMR_3)
TCORA_3: Time constant register A_3 Time constant register A_2 TCNT_3: Timer counter_3 Timer counter_2 TCORB_3: Time constant register B_3 Time constant register B_2 TCSR_3: Timer control/status register_3 Timer control/status register_2 TCR_3: Timer control register_3 Timer control register_2 TCCR_3: Timer counter control register_3 Timer counter control register_2 For the corresponding A/D converter channels, see section 21, A/D Converter.
Figure 16.2 Block Diagram of 8-Bit Timer Module (Unit 1)
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Section 16 8-Bit Timers (TMR)
Internal clocks P P/2 P/8 P/32 P/64 P/1024 P/8192 Counter clock 5 Counter clock 4 Clock select TCORA_4 Compare match A5 Compare match A4 Comparator A_4 TCORA_5
Comparator A_5
Overflow 5 Overflow 4 Counter clear 4 Counter clear5 Compare match B5 Compare match B4 Control logic
TCNT_4
TCNT_5
To SCI_5 TMO4 TMO5
Comparator B_4
Comparator B_5
TCORB_4 A/D conversion start request signal*
TCORB_5
TCSR_4 TCR_4
TCSR_5 TCR_5
TCCR_4 Channel 4 (TMR_4) CMIA4 CMIB4 CMIA5 CMIB5 Interrupt signals [Legend] TCORA_4: TCNT_4: TCORB_4: TCSR_4: TCR_4: TCCR_4: Note: * Time constant register A_4 Timer counter_4 Time constant register B_4 Timer control/status register_4 Timer control register_4 Timer counter control register_4 TCORA_5: TCNT_5: TCORB_5: TCSR_5: TCR_5: TCCR_5: CMI4 CMI5
TCCR_5 Channel 5 (TMR_5)
Time constant register A_5 Timer counter_5 Time constant register B_5 Timer control/status register_5 Timer control register_5 Timer counter control register_5
For the corresponding A/D converter channels, see section 21, A/D Converter.
Figure 16.3 Block Diagram of 8-Bit Timer Module (Unit 2)
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Internal bus
Section 16 8-Bit Timers (TMR)
Internal clocks P P/2 P/8 P/32 P/64 P/1024 P/8192 Counter clock 7 Counter clock 6 Clock select TCORA_6 Compare match A7 Compare match A6 Comparator A_6 TCORA_7
Comparator A_7
Overflow 7 Overflow 6 Counter clear 6 Counter clear 7 Compare match B7 Compare match B6 Control logic
TCNT_6
TCNT_7
Internal bus
To SCI_6 TMO6 TMO7
Comparator B_6
Comparator B_7
TCORB_6 A/D conversion start request signal*
TCORB_7
TCSR_6 TCR_6
TCSR_7 TCR_7
TCCR_6 Channel 6 (TMR_6) CMIA6 CMIB6 CMIA7 CMIB7 CMI6 CMI7
TCCR_7 Channel 7 (TMR_7)
Interrupt signals [Legend] TCORA_7: Time constant register A_7 TCORA_6: Time constant register A_6 TCNT_7: Timer counter_7 TCNT_6: Timer counter_6 TCORB_7: Time constant register B_7 TCORB_6: Time constant register B_6 TCSR_7: Timer control/status register_7 TCSR_6: Timer control/status register_6 TCR_7: Timer control register_7 TCR_6: Timer control register_6 TCCR_7: Timer counter control register_7 TCCR_6: Timer counter control register_6 Note: * For the corresponding A/D converter channels, see section 21, A/D Converter.
Figure 16.4 Block Diagram of 8-Bit Timer Module (Unit 3)
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Section 16 8-Bit Timers (TMR)
16.2
Input/Output Pins
Table 16.1 shows the pin configuration of the TMR. Table 16.1 Pin Configuration
Unit 0 Channel Name 0 Timer output pin Timer clock input pin Timer reset input pin 1 Timer output pin Timer clock input pin Timer reset input pin 1 2 Timer output pin Timer clock input pin Timer reset input pin 3 Timer output pin Timer clock input pin Timer reset input pin 2 4 5 3 6 7
Symbol TMO0 TMCI0 TMRI0 TMO1 TMCI1 TMRI1 TMO2 TMCI2 TMRI2 TMO3 TMCI3 TMRI3
I/O
Function
Output Outputs compare match Input Input Inputs external clock for counter Inputs external reset to counter
Output Outputs compare match Input Input Inputs external clock for counter Inputs external reset to counter
Output Outputs compare match Input Input Inputs external clock for counter Inputs external reset to counter
Output Outputs compare match Input Input
Inputs external clock for counter Inputs external reset to counter
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Section 16 8-Bit Timers (TMR)
16.3
Register Descriptions
The TMR has the following registers. Unit 0: * Channel 0 (TMR_0): Timer counter_0 (TCNT_0) Time constant register A_0 (TCORA_0) Time constant register B_0 (TCORB_0) Timer control register_0 (TCR_0) Timer counter control register_0 (TCCR_0) Timer control/status register_0 (TCSR_0) * Channel 1 (TMR_1): Timer counter_1 (TCNT_1) Time constant register A_1 (TCORA_1) Time constant register B_1 (TCORB_1) Timer control register_1 (TCR_1) Timer counter control register_1 (TCCR_1) Timer control/status register_1 (TCSR_1) Unit 1: * Channel 2 (TMR_2): Timer counter_2 (TCNT_2) Time constant register A_2 (TCORA_2) Time constant register B_2 (TCORB_2) Timer control register_2 (TCR_2) Timer counter control register_2 (TCCR_2) Timer control/status register_2 (TCSR_2) * Channel 3 (TMR_3): Timer counter_3 (TCNT_3) Time constant register A_3 (TCORA_3) Time constant register B_3 (TCORB_3) Timer control register_3 (TCR_3) Timer counter control register_3 (TCCR_3) Timer control/status register_3 (TCSR_3)
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Section 16 8-Bit Timers (TMR)
Unit 2: * Channel 4 (TMR_4): Timer counter_4 (TCNT_4) Time constant register A_4 (TCORA_4) Time constant register B_4 (TCORB_4) Timer control register_4 (TCR_4) Timer counter control register_4 (TCCR_4) Timer control/status register_4 (TCSR_4) * Channel 5 (TMR_5): Timer counter_5 (TCNT_5) Time constant register A_5 (TCORA_5) Time constant register B_5 (TCORB_5) Timer control register_5 (TCR_5) Timer counter control register_5 (TCCR_5) Timer control/status register_5 (TCSR_5) Unit 3: * Channel 6 (TMR_6): Timer counter_6 (TCNT_6) Time constant register A_6 (TCORA_6) Time constant register B_6 (TCORB_6) Timer control register_6 (TCR_6) Timer counter control register_6 (TCCR_6) Timer control/status register_6 (TCSR_6) * Channel 7 (TMR_7): Timer counter_7 (TCNT_7) Time constant register A_7 (TCORA_7) Time constant register B_7 (TCORB_7) Timer control register_7 (TCR_7) Timer counter control register_7 (TCCR_7) Timer control/status register_7 (TCSR_7)
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Section 16 8-Bit Timers (TMR)
16.3.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR and bits ICKS1 and ICKS0 in TCCR are used to select a clock. TCNT can be cleared by an external reset input signal, compare match A signal, or compare match B signal. Which signal to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When TCNT overflows from H'FF to H'00, bit OVF in TCSR is set to 1. TCNT is initialized to H'00.
TCNT_0 4 3 TCNT_1 4 3
Bit Bit Name Initial Value R/W
7
6
5
2
1
0
7
6
5
2
1
0
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
16.3.2
Time Constant Register A (TCORA)
TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. The value in TCORA is continually compared with the value in TCNT. When a match is detected, the corresponding CMFA flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match A) and the settings of bits OS1 and OS0 in TCSR. TCORA is initialized to H'FF.
TCORA_0 4 3 TCORA_1 4 3
Bit Bit Name Initial Value R/W
7
6
5
2
1
0
7
6
5
2
1
0
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
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Section 16 8-Bit Timers (TMR)
16.3.3
Time Constant Register B (TCORB)
TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit register so they can be accessed together by a word transfer instruction. TCORB is continually compared with the value in TCNT. When a match is detected, the corresponding CMFB flag in TCSR is set to 1. Note however that comparison is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can be freely controlled by this compare match signal (compare match B) and the settings of bits OS3 and OS2 in TCSR. TCORB is initialized to H'FF.
TCORB_0 4 3 TCORB_1 4 3
Bit Bit Name Initial Value R/W
7
6
5
2
1
0
7
6
5
2
1
0
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
1 R/W
16.3.4
Timer Control Register (TCR)
TCR selects the TCNT clock source and the condition for clearing TCNT, and enables/disables interrupt requests.
Bit Bit Name Initial Value R/W 7 CMIEB 0 R/W 6 CMIEA 0 R/W 5 OVIE 0 R/W 4 CCLR1 0 R/W 3 CCLR0 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Bit 7
Bit Name CMIEB
Initial Value 0
R/W R/W
Description Compare Match Interrupt Enable B Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set 2 to 1. * 0: CMFB interrupt requests (CMIB) are disabled 1: CMFB interrupt requests (CMIB) are enabled
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Section 16 8-Bit Timers (TMR)
Bit 6
Bit Name CMIEA
Initial Value 0
R/W R/W
Description Compare Match Interrupt Enable A Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set 2 to 1. * 0: CMFA interrupt requests (CMIA) are disabled 1: CMFA interrupt requests (CMIA) are enabled
5
OVIE
0
R/W
Timer Overflow Interrupt Enable*3 Selects whether OVF interrupt requests (OVI) are enabled or disabled when the OVF flag in TCSR is set to 1. 0: OVF interrupt requests (OVI) are disabled 1: OVF interrupt requests (OVI) are enabled
4 3
CCLR1 CCLR0
0 0
R/W R/W
Counter Clear 1 and 0*1 These bits select the method by which TCNT is cleared. 00: Clearing is disabled 01: Cleared by compare match A 10: Cleared by compare match B 11: Cleared at rising edge (TMRIS in TCCR is cleared to 0) of the external reset input or when the external 3 reset input is high (TMRIS in TCCR is set to 1) *
2 1 0
CKS2 CKS1 CKS0
0 0 0
R/W R/W R/W
Clock Select 2 to 0*
1
These bits select the clock input to TCNT and count condition. See table 16.2.
Notes: 1. To use an external reset or external clock, the DDR and ICR bits in the corresponding pin should be set to 0 and 1, respectively. For details, see section 13, I/O Ports. 2. In unit 2 and unit 3, one interrupt signal is used for CMIEB or CMIEA. For details, see section 16.7, Interrupt Sources. 3. Available only in unit 0 and unit 1.
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Section 16 8-Bit Timers (TMR)
16.3.5
Timer Counter Control Register (TCCR)
TCCR selects the TCNT internal clock source and controls external reset input.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 TMRIS 0 R/W 2 0 R 1 ICKS1 0 R/W 0 ICKS0 0 R/W
Bit 7 to 4 3
Bit Name TMRIS
Initial Value All 0 0
R/W R R/W
Description Reserved These bits are always read as 0. It should not be set to 0. Timer Reset Input Select* Selects an external reset input when the CCLR1 and CCLR0 bits in TCR are B'11. 0: Cleared at rising edge of the external reset 1: Cleared when the external reset is high
2 1 0 Note: *
ICKS1 ICKS0
0 0 0
R R/W R/W
Reserved This bit is always read as 0. It should not be set to 0. Internal Clock Select 1 and 0 These bits in combination with bits CKS2 to CKS0 in TCR select the internal clock. See table 16.2.
Available only in unit 0 and unit 1. The write value should always be 0 in unit 2 and unit 3.
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Section 16 8-Bit Timers (TMR)
Table 16.2 Clock Input to TCNT and Count Condition (Unit 0)
TCR Channel TMR_0 Bit 2 CKS2 0 0 TCCR Bit 1 Bit 0 Bit 1 Bit 0 CKS1 CKS0 ICKS1 ICKS0 Description 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 TMR_1 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 All 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock input prohibited Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at falling edge of P/8192. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_1 overflow signal* . Clock input prohibited Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at falling edge of P/8192. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_0 compare match A* . Uses external clock. Counts at rising edge* . Uses external clock. Counts at falling edge* . Uses external clock. Counts at both rising and falling 2 edges* .
2 2 1 1
Notes: 1. If the clock input of channel 0 is the TCNT_1 overflow signal and that of channel 1 is the TCNT_0 compare match signal, no incrementing clock is generated. Do not use this setting. 2. To use the external clock, the DDR and ICR bits in the corresponding pin should be set to 0 and 1, respectively. For details, see section 13, I/O Ports.
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Section 16 8-Bit Timers (TMR)
Table 16.3 Clock Input to TCNT and Count Condition (Unit 1)
TCR Channel TMR_2 Bit 2 CKS2 0 0 TCCR Bit 1 Bit 0 Bit 1 Bit 0 CKS1 CKS0 ICKS1 ICKS0 Description 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 TMR_3 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 All 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock input prohibited Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at falling edge of P/8192. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_3 overflow signal* . Clock input prohibited Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at falling edge of P/8192. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_2 compare match A* . Uses external clock. Counts at rising edge* . Uses external clock. Counts at falling edge* . Uses external clock. Counts at both rising and falling 2 edges* .
2 2 1 1
Notes: 1. If the clock input of channel 2 is the TCNT_3 overflow signal and that of channel 3 is the TCNT_2 compare match signal, no incrementing clock is generated. Do not use this setting. 2. To use the external clock, the DDR and ICR bits in the corresponding pin should be set to 0 and 1, respectively. For details, see section 13, I/O Ports.
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Section 16 8-Bit Timers (TMR)
Table 16.4 Clock Input to TCNT and Count Condition (Unit 2)
TCR Channel TMR_4 Bit 2 CKS2 0 0 TCCR Bit 1 Bit 0 Bit 1 Bit 0 CKS1 CKS0 ICKS1 ICKS0 Description 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 TMR_5 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 All 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock input prohibited Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at rising edge of P. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_5 overflow signal*. Clock input prohibited Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at rising edge of P. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_4 compare match A*. Setting prohibited Setting prohibited Setting prohibited
Note:
*
If the clock input of channel 4 is the TCNT_5 overflow signal and that of channel 5 is the TCNT_4 compare match signal, no incrementing clock is generated. Do not use this setting.
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Section 16 8-Bit Timers (TMR)
Table 16.5 Clock Input to TCNT and Count Condition (Unit 3)
TCR Channel TMR_6 Bit 2 CKS2 0 0 TCCR Bit 1 Bit 0 Bit 1 Bit 0 CKS1 CKS0 ICKS1 ICKS0 Description 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 TMR_7 0 0 0 0 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 All 1 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Clock input prohibited Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at rising edge of P. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_7 overflow signal*. Clock input prohibited Uses internal clock. Counts at rising edge of P/8. Uses internal clock. Counts at rising edge of P/2. Uses internal clock. Counts at falling edge of P/8. Uses internal clock. Counts at falling edge of P/2. Uses internal clock. Counts at rising edge of P/64. Uses internal clock. Counts at rising edge of P/32. Uses internal clock. Counts at falling edge of P/64. Uses internal clock. Counts at falling edge of P/32. Uses internal clock. Counts at rising edge of P/8192. Uses internal clock. Counts at rising edge of P/1024. Uses internal clock. Counts at rising edge of P. Uses internal clock. Counts at falling edge of P/1024. Counts at TCNT_6 compare match A*. Setting prohibited Setting prohibited Setting prohibited
Note:
*
If the clock input of channel 6 is the TCNT_7 overflow signal and that of channel 7 is the TCNT_6 compare match signal, no incrementing clock is generated. Do not use this setting.
Rev. 2.00 Sep. 25, 2008 Page 734 of 1340 REJ09B0413-0200
Section 16 8-Bit Timers (TMR)
16.3.6
Timer Control/Status Register (TCSR)
TCSR displays status flags, and controls compare match output.
* TCSR_0 Bit Bit Name Initial Value R/W * TCSR_1 Bit Bit Name Initial Value R/W 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 1 R 3 OS3 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W 0 OS0 0 R/W
7 CMFB 0 R/(W)*
6 CMFA 0 R/(W)*
5 OVF 0 R/(W)*
4 ADTE 0 R/W
3 OS3 0 R/W
2 OS2 0 R/W
1 OS1 0 R/W
0 OS0 0 R/W
Note: * Only 0 can be written to this bit, to clear the flag.
* TCSR_0, TCSR_4
Bit 7 Bit Name CMFB Initial Value 0 R/W
1
Description
R/(W)* Compare Match Flag B [Setting condition] * * When TCNT matches TCORB When writing 0 after reading CMFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When the DTC is activated by a CMIB interrupt while the DISEL bit in MRB of the DTC is 0 [Clearing conditions]
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Section 16 8-Bit Timers (TMR)
Bit 6
Bit Name CMFA
Initial Value 0
R/W
1
Description
R/(W)* Compare Match Flag A [Setting condition] * * When TCNT matches TCORA When writing 0 after reading CMFA = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When the DTC is activated by a CMIA interrupt while the DISEL bit in MRB in the DTC is 0 [Clearing conditions]
5
OVF
0
R/(W)*1 Timer Overflow Flag [Setting condition] When TCNT overflows from H'FF to H'00 [Clearing condition] When writing 0 after reading OVF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
4
ADTE
0
R/W
A/D Trigger Enable Selects enabling or disabling of A/D converter start requests by compare match A. 0: A/D converter start requests by compare match A are disabled 1: A/D converter start requests by compare match A are enabled
3 2
OS3 OS2
0 0
R/W R/W
Output Select 3 and 2*2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output)
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Section 16 8-Bit Timers (TMR)
Bit 1 0
Bit Name OS1 OS0
Initial Value 0 0
R/W R/W R/W
Description Output Select 1 and 0*2 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output)
Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags. 2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first compare match occurs after a reset.
* TCSR_1, TCSR_5
Bit 7 Bit Name CMFB Initial Value 0 R/W
1
Description
R/(W)* Compare Match Flag B [Setting condition] * * When TCNT matches TCORB When writing 0 after reading CMFB = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When the DTC is activated by a CMIB interrupt while the DISEL bit in MRB of the DTC is 0*3 [Clearing conditions]
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Section 16 8-Bit Timers (TMR)
Bit 6
Bit Name CMFA
Initial Value 0
R/W
1
Description
R/(W)* Compare Match Flag A [Setting condition] * * When TCNT matches TCORA When writing 0 after reading CMFA = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When the DTC is activated by a CMIA interrupt while the DISEL bit in MRB of the DTC is 0*3 [Clearing conditions]
5
OVF
0
R/(W)*1 Timer Overflow Flag [Setting condition] When TCNT overflows from H'FF to H'00 [Clearing condition] Cleared by reading OVF when OVF = 1, then writing 0 to OVF (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
4 3 2
OS3 OS2
1 0 0
R R/W R/W
Reserved This bit is always read as 1 and cannot be modified. Output Select 3 and 2*2 These bits select a method of TMO pin output when compare match B of TCORB and TCNT occurs. 00: No change when compare match B occurs 01: 0 is output when compare match B occurs 10: 1 is output when compare match B occurs 11: Output is inverted when compare match B occurs (toggle output)
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Section 16 8-Bit Timers (TMR)
Bit 1 0
Bit Name OS1 OS0
Initial Value 0 0
R/W R/W R/W
Description Output Select 1 and 0*2 These bits select a method of TMO pin output when compare match A of TCORA and TCNT occurs. 00: No change when compare match A occurs 01: 0 is output when compare match A occurs 10: 1 is output when compare match A occurs 11: Output is inverted when compare match A occurs (toggle output)
Notes: 1. Only 0 can be written to bits 7 to 5, to clear these flags. 2. Timer output is disabled when bits OS3 to OS0 are all 0. Timer output is 0 until the first compare match occurs after a reset. 3. Available only in unit 0 and unit 1.
16.4
16.4.1
Operation
Pulse Output
Figure 16.5 shows an example of the 8-bit timer being used to generate a pulse output with a desired duty cycle. The control bits are set as follows: 1. Clear the bit CCLR1 in TCR to 0 and set the bit CCLR0 in TCR to 1 so that TCNT is cleared at a TCORA compare match. 2. Set the bits OS3 to OS0 in TCSR to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides pulses output at a cycle determined by TCORA with a pulse width determined by TCORB. No software intervention is required. The timer output is 0 until the first compare match occurs after a reset.
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Section 16 8-Bit Timers (TMR)
TCNT H'FF TCORA TCORB H'00 Counter clear
TMO
Figure 16.5 Example of Pulse Output 16.4.2 Reset Input
Figure 16.6 shows an example of the 8-bit timer being used to generate a pulse which is output after a desired delay time from a TMRI input. The control bits are set as follows: 1. Set both bits CCLR1 and CCLR0 in TCR to 1 and set the TMRIS bit in TCCR to 1 so that TCNT is cleared at the high level input of the TMRI signal. 2. In TCSR, set bits OS3 to OS0 to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match. With these settings, the 8-bit timer provides pulses output at a desired delay time from a TMRI input determined by TCORA and with a pulse width determined by TCORB and TCORA.
TCORB TCORA TCNT
H'00
TMRI TMO
Figure 16.6 Example of Reset Input
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Section 16 8-Bit Timers (TMR)
16.5
16.5.1
Operation Timing
TCNT Count Timing
Figure 16.7 shows the TCNT count timing for internal clock input. Figure 16.8 shows the TCNT count timing for external clock input. Note that the external clock pulse width must be at least 1.5 states for increment at a single edge, and at least 2.5 states for increment at both edges. The counter will not increment correctly if the pulse width is less than these values.
P
Internal clock
TCNT input clock TCNT N-1 N N+1
Figure 16.7 Count Timing for Internal Clock Input
P
External clock input pin
TCNT input clock TCNT N-1 N N+1
Figure 16.8 Count Timing for External Clock Input
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Section 16 8-Bit Timers (TMR)
16.5.2
Timing of CMFA and CMFB Setting at Compare Match
The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. Therefore, when the TCOR and TCNT values match, the compare match signal is not generated until the next TCNT clock input. Figure 16.9 shows this timing.
P TCNT TCOR Compare match signal CMF N N N+1
Figure 16.9 Timing of CMF Setting at Compare Match 16.5.3 Timing of Timer Output at Compare Match
When a compare match signal is generated, the timer output changes as specified by the bits OS3 to OS0 in TCSR. Figure 16.10 shows the timing when the timer output is toggled by the compare match A signal.
P Compare match A signal Timer output pin
Figure 16.10 Timing of Toggled Timer Output at Compare Match A
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Section 16 8-Bit Timers (TMR)
16.5.4
Timing of Counter Clear by Compare Match
TCNT is cleared when compare match A or B occurs, depending on the settings of the bits CCLR1 and CCLR0 in TCR. Figure 16.11 shows the timing of this operation.
P Compare match signal TCNT N H'00
Figure 16.11 Timing of Counter Clear by Compare Match 16.5.5 Timing of TCNT External Reset*
TCNT is cleared at the rising edge or high level of an external reset input, depending on the settings of bits CCLR1 and CCLR0 in TCR. The clear pulse width must be at least 2 states. Figure 16.12 and Figure 16.13 shows the timing of this operation. Note: * Clearing by an external reset is available only in units 0 and 1.
P External reset input pin Clear signal TCNT N-1 N H'00
Figure 16.12 Timing of Clearance by External Reset (Rising Edge)
P External reset input pin
Clear signal
TCNT
N-1
N
H'00
Figure 16.13 Timing of Clearance by External Reset (High Level)
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Section 16 8-Bit Timers (TMR)
16.5.6
Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 16.14 shows the timing of this operation.
P TCNT Overflow signal H'FF H'00
OVF
Figure 16.14 Timing of OVF Setting
16.6
Operation with Cascaded Connection
If the bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match count mode). 16.6.1 16-Bit Counter Mode
When the bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. (1) Setting of Compare Match Flags
* The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs. * The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs. (2) Counter Clear Specification
* If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the 16-bit counter (TCNT_0 and TCNT_1 together) is cleared when a 16-bit compare match event occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear by the TMRI0 pin has been set. * The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be cleared independently.
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Section 16 8-Bit Timers (TMR)
(3)
Pin Output
* Control of output from the TMO0 pin by the bits OS3 to OS0 in TCSR_0 is in accordance with the 16-bit compare match conditions. * Control of output from the TMO1 pin by the bits OS3 to OS0 in TCSR_1 is in accordance with the lower 8-bit compare match conditions. 16.6.2 Compare Match Count Mode
When the bits CKS2 to CKS0 in TCR_1 are set to B'100, TCNT_1 counts compare match A for channel 0. Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag, generation of interrupts, output from the TMO pin, and counter clear are in accordance with the settings for each channel.
16.7
16.7.1
Interrupt Sources
Interrupt Sources and DTC Activation
* Interrupt in unit 0 and unit 1 There are three interrupt sources for the 8-bit timer (TMR_0 or TMR_1): CMIA, CMIB, and OVI. Their interrupt sources and priorities are shown in table 16.6. Each interrupt source is enabled or disabled by the corresponding interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts (This is available in unit 0 and unit 1 only). Table 16.6 8-Bit Timer (TMR_0 or TMR_1) Interrupt Sources (in Unit 0 and Unit 1)
Signal Name CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Name CMIA0 CMIB0 OVI0 CMIA1 CMIB1 OVI1 Interrupt Source Interrupt Flag DTC Activation Possible Possible Not possible Low Possible Possible Not possible Low High Priority High
TCORA_0 compare match CMFA TCORB_0 compare match CMFB TCNT_0 overflow OVF
TCORA_1 compare match CMFA TCORB_1 compare match CMFB TCNT_1 overflow OVF
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Section 16 8-Bit Timers (TMR)
* Interrupt in unit 2 and unit 3 There are two interrupt sources for the 8-bit timer (TMR_4 or TMR_5): CMIA, CMIB. The interrupt signal is CMI only. The interrupt sources are shown in table 16.7. When enabling or disabling is set by the interrupt enable bit in TCR or TCSR, and when either CMIA or CMIB interrupt source is generated, CMI is sent to the interrupt controller. To verify which interrupt source is generated, confirm by checking each flag in TCSR. No overflow-related interrupt signal exists. DTC cannot be activated by this interrupt. Table 16.7 8-Bit Timer (TMR_4 or TMR_5) Interrupt Sources (in Unit 2 and Unit 3)
Signal Name CMI4 Name CMIA4 CMIB4 CMI5 CMIA5 CMIB5 Interrupt Source TCORA_4 compare match TCORB_4 compare match TCORA_5 compare match TCORB_5 compare match Interrupt Flag CMFA CMFB CMFA CMFB Not possible DTC Activation Not possible Priority
16.7.2
A/D Converter Activation
The A/D converter can be activated by a compare match A for the even channels of each TMR unit. * If the ADTE bit in TCSR is set to 1 when the CMFA flag in TCSR is set to 1 by the occurrence of a compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. Note: * For the corresponding A/D converter channels, see section 21, A/D Converter.
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Section 16 8-Bit Timers (TMR)
16.8
16.8.1
Usage Notes
Notes on Setting Cycle
If the compare match is selected for counter clear, TCNT is cleared at the last state in the cycle in which the values of TCNT and TCOR match. TCNT updates the counter value at this last state. Therefore, the counter frequency is obtained by the following formula.
f = / (N + 1 ) f: Counter frequency : Operating frequency N: TCOR value
16.8.2
Conflict between TCNT Write and Counter Clear
If a counter clear signal is generated during the T2 state of a TCNT write cycle, the clear takes priority and the write is not performed as shown in figure 16.15.
TCNT write cycle by CPU T1 T2 P Address Internal write signal Counter clear signal TCNT N H'00 TCNT address
Figure 16.15 Conflict between TCNT Write and Clear
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Section 16 8-Bit Timers (TMR)
16.8.3
Conflict between TCNT Write and Increment
If a TCNT input clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented as shown in figure 16.16.
TCNT write cycle by CPU T1 T2 P Address Internal write signal TCNT input clock TCNT N Counter write data M TCNT address
Figure 16.16 Conflict between TCNT Write and Increment 16.8.4 Conflict between TCOR Write and Compare Match
If a compare match event occurs during the T2 state of a TCOR write cycle, the TCOR write takes priority and the compare match signal is inhibited as shown in figure 16.17.
TCOR write cycle by CPU T1 T2 P Address Internal write signal TCNT TCOR N N TCOR write data Compare match signal Inhibited N+1 M TCOR address
Figure 16.17 Conflict between TCOR Write and Compare Match
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Section 16 8-Bit Timers (TMR)
16.8.5
Conflict between Compare Matches A and B
If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 16.8. Table 16.8 Timer Output Priorities
Output Setting Toggle output 1-output 0-output No change Low Priority High
16.8.6
Switching of Internal Clocks and TCNT Operation
TCNT may be incremented erroneously depending on when the internal clock is switched. Table 16.9 shows the relationship between the timing at which the internal clock is switched (by writing to the bits CKS1 and CKS0) and the TCNT operation. When the TCNT clock is generated from an internal clock, the rising or falling edge of the internal clock pulse are always monitored. Table 16.9 assumes that the falling edge is selected. If the signal levels of the clocks before and after switching change from high to low as shown in item 3, the change is considered as the falling edge. Therefore, a TCNT clock pulse is generated and TCNT is incremented. This is similar to when the rising edge is selected. The erroneous increment of TCNT can also happen when switching between rising and falling edges of the internal clock, and when switching between internal and external clocks.
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Section 16 8-Bit Timers (TMR)
Table 16.9 Switching of Internal Clock and TCNT Operation
No. 1 Timing to Change CKS1 and CKS0 Bits Switching from low to low*
1
TCNT Clock Operation
Clock before switchover Clock after switchover TCNT input clock TCNT N CKS bits changed N+1
2
Switching from low to high*
2
Clock before switchover Clock after switchover TCNT input clock TCNT N N+1 N+2
CKS bits changed
3
Switching from high to low*3
Clock before switchover Clock after switchover TCNT input clock TCNT N N+1 CKS bits changed *4
N+2
4
Switching from high to high
Clock before switchover Clock after switchover TCNT input clock TCNT N N+1 N+2 CKS bits changed
Notes: 1. 2. 3. 4.
Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated because the change of the signal levels is considered as a falling edge; TCNT is incremented.
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Section 16 8-Bit Timers (TMR)
16.8.7
Mode Setting with Cascaded Connection
If 16-bit counter mode and compare match count mode are specified at the same time, input clocks for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter mode and compare match count mode simultaneously. 16.8.8 Module Stop State Setting
Operation of the TMR can be disabled or enabled using the module stop control register. The initial setting is for operation of the TMR to be halted. Register access is enabled by clearing the module stop state. For details, see section 27, Power-Down Modes. 16.8.9 Interrupts in Module Stop State
If the module stop state is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be disabled before entering the module stop state.
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Section 16 8-Bit Timers (TMR)
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Section 17 Watchdog Timer (WDT)
Section 17 Watchdog Timer (WDT)
The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow. At the same time, the WDT can also generate an internal reset signal. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. Figure 17.1 shows a block diagram of the WDT.
17.1
Features
* Selectable from eight counter input clocks * Switchable between watchdog timer mode and interval timer mode In watchdog timer mode If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not the entire LSI is reset at the same time. In interval timer mode If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
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Section 17 Watchdog Timer (WDT)
Overflow WOVI (interrupt request signal) WDTOVF Internal reset signal* Interrupt control Clock Clock select
Reset control
P/2 P/64 P/128 P/512 P/2048 P/8192 P/32768 P/131072 Internal clocks
RSTCSR
TCNT
TCSR Bus interface
Module bus WDT [Legend] Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Note: * An internal reset signal can be generated by the RSTCSR setting.
Figure 17.1 Block Diagram of WDT
17.2
Input/Output Pin
Table 17.1 shows the WDT pin configuration. Table 17.1 Pin Configuration
Name Watchdog timer overflow* Note: * Symbol WDTOVF I/O Output Function Outputs a counter overflow signal in watchdog timer mode
In boundary scan valid mode, counter overflow signal output cannot be used.
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Internal bus
Section 17 Watchdog Timer (WDT)
17.3
Register Descriptions
The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and RSTCSR have to be written to in a method different from normal registers. For details, see section 17.6.1, Notes on Register Access. * Timer counter (TCNT) * Timer control/status register (TCSR) * Reset control/status register (RSTCSR) 17.3.1 Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in TCSR is cleared to 0.
Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0
17.3.2
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
Bit Bit Name Initial Value R/W Note: 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 1 R 3 1 R 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
* Only 0 can be written to this bit, to clear the flag.
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Section 17 Watchdog Timer (WDT)
Bit 7
Bit Name OVF
Initial Value 0
R/W
Description
6
WT/IT
0
5
TME
0
R/(W)* Overflow Flag Indicates that TCNT has overflowed in interval timer mode. Only 0 can be written to this bit, to clear the flag. [Setting condition] When TCNT overflows in interval timer mode (changes from H'FF to H'00) When internal reset request generation is selected in watchdog timer mode, OVF is cleared automatically by the internal reset. [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF. (When the CPU is used to clear this flag while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) R/W Timer Mode Select Selects whether the WDT is used as a watchdog timer or interval timer. 0: Interval timer mode When TCNT overflows, an interval timer interrupt (WOVI) is requested. 1: Watchdog timer mode When TCNT overflows, the WDTOVF signal is output. R/W Timer Enable When this bit is set to 1, TCNT starts counting. When this bit is cleared, TCNT stops counting and is initialized to H'00. R R/W R/W R/W Reserved These are read-only bits and cannot be modified. Clock Select 2 to 0 Select the clock source to be input to TCNT. The overflow cycle for P = 20 MHz is indicated in parentheses. 000: Clock P/2 (cycle: 25.6 s) 001: Clock P/64 (cycle: 819.2 s) 010: Clock P/128 (cycle: 1.6 ms) 011: Clock P/512 (cycle: 6.6 ms) 100: Clock P/2048 (cycle: 26.2 ms) 101: Clock P/8192 (cycle: 104.9 ms) 110: Clock P/32768 (cycle: 419.4 ms) 111: Clock P/131072 (cycle: 1.68 s)
4, 3 2 1 0
CKS2 CKS1 CKS0
All 1 0 0 0
Note:
*
Only 0 can be written to this bit, to clear the flag.
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Section 17 Watchdog Timer (WDT)
17.3.3
Reset Control/Status Register (RSTCSR)
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by WDT overflows.
Bit Bit Name Initial Value R/W 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 0 R/W 4 1 R 3 1 R 2 1 R 1 1 R 0 1 R
Note: * Only 0 can be written to this bit, to clear the flag.
Bit 7
Bit Name WOVF
Initial Value 0
R/W
Description
R/(W)* Watchdog Timer Overflow Flag This bit is set when TCNT overflows in watchdog timer mode. This bit cannot be set in interval timer mode, and only 0 can be written. [Setting condition] When TCNT overflows (changed from H'FF to H'00) in watchdog timer mode [Clearing condition] Reading RSTCSR when WOVF = 1, and then writing 0 to WOVF
6
RSTE
0
R/W
Reset Enable Specifies whether or not this LSI is internally reset if TCNT overflows during watchdog timer operation. 0: LSI is not reset even if TCNT overflows (Though this LSI is not reset, TCNT and TCSR in WDT are reset) 1: LSI is reset if TCNT overflows
5
0
R/W
Reserved Although this bit is readable/writable, reading from or writing to this bit does not affect operation.
4 to 0 Note: *
All 1
R
Reserved These are read-only bits and cannot be modified.
Only 0 can be written to this bit, to clear the flag.
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Section 17 Watchdog Timer (WDT)
17.4
17.4.1
Operation
Watchdog Timer Mode
To use the WDT in watchdog timer mode, set both the WT/IT and TME bits in TCSR to 1. During watchdog timer operation, if TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This ensures that TCNT does not overflow while the system is operating normally. Software must prevent TCNT overflows by rewriting the TCNT value (normally H'00 is written) before overflow occurs. This WDTOVF signal can be used to reset the LSI internally in watchdog timer mode. If TCNT overflows when the RSTE bit in RSTCSR is set to 1, a signal that resets this LSI internally is generated at the same time as the WDTOVF signal. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The WDTOVF signal is output for 133 cycles of P when RSTE = 1 in RSTCSR, and for 130 cycles of P when RSTE = 0 in RSTCSR. The internal reset signal is output for 519 cycles of P. When RSTE = 1, an internal reset signal is generated. Since the system clock control register (SCKCR) is initialized, the multiplication ratio of P becomes the initial value. When RSTE = 0, an internal reset signal is not generated. Neither SCKCR nor the multiplication ratio of P is changed. When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT overflows when the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire LSI.
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Section 17 Watchdog Timer (WDT)
TCNT value Overflow H'FF
H'00 WT/IT = 1 TME = 1 H'00 written to TCNT WOVF = 1 WDTOVF and internal reset are generated WT/IT = 1 H'00 written TME = 1 to TCNT
Time
WDTOVF signal
133 states*2
Internal reset signal*1 519 states Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated. 2. 130 states when the RSTE bit is cleared to 0.
Figure 17.2 Operation in Watchdog Timer Mode
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Section 17 Watchdog Timer (WDT)
17.4.2
Interval Timer Mode
To use the WDT as an interval timer, set the WT/IT bit to 0 and the TME bit to 1 in TCSR. When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each time the TCNT overflows. Therefore, an interrupt can be generated at intervals. When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested at the same time the OVF bit in the TCSR is set to 1.
TCNT value H'FF Overflow Overflow Overflow Overflow
H'00 WT/IT = 0 TME = 1 WOVI WOVI WOVI WOVI
Time
[Legend] WOVI: Interval timer interrupt request
Figure 17.3 Operation in Interval Timer Mode
17.5
Interrupt Source
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. The OVF flag must be cleared to 0 in the interrupt handling routine. Table 17.2 WDT Interrupt Source
Name WOVI Interrupt Source TCNT overflow Interrupt Flag OVF DTC Activation Impossible
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Section 17 Watchdog Timer (WDT)
17.6
17.6.1
Usage Notes
Notes on Register Access
The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. (1) Writing to TCNT, TCSR, and RSTCSR
TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a byte transfer instruction. For writing, TCNT and TCSR are assigned to the same address. Accordingly, perform data transfer as shown in figure 17.4. The transfer instruction writes the lower byte data to TCNT or TCSR. To write to RSTCSR, execute a word transfer instruction for address H'FFA6. A byte transfer instruction cannot be used to write to RSTCSR. The method of writing 0 to the WOVF bit in RSTCSR differs from that of writing to the RSTE bit in RSTCSR. Perform data transfer as shown in figure 17.4. At data transfer, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit. To write to the RSTE bit, perform data transfer as shown in figure 17.4. In this case, the transfer instruction writes the value in bit 6 of the lower byte to the RSTE bit, but has no effect on the WOVF bit.
TCNT write or writing to the RSTE bit in RSTCSR: 15 Address: H'FFA4 (TCNT) H'FFA6 (RSTCSR) 8 H'5A 7 Write data 0
TCSR write: Address: H'FFA4 (TCSR) 15 H'A5 8 7 Write data 0
Writing 0 to the WOVF bit in RSTCSR: 15 Address: H'FFA6 (RSTCSR)
8 H'A5
7 H'00
0
Figure 17.4 Writing to TCNT, TCSR, and RSTCSR
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Section 17 Watchdog Timer (WDT)
(2)
Reading from TCNT, TCSR, and RSTCSR
These registers can be read from in the same way as other registers. For reading, TCSR is assigned to address H'FFA4, TCNT to address H'FFA5, and RSTCSR to address H'FFA7. 17.6.2 Conflict between Timer Counter (TCNT) Write and Increment
If a TCNT clock pulse is generated during the T2 cycle of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 17.5 shows this operation.
TCNT write cycle T1 P T2
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 17.5 Conflict between TCNT Write and Increment 17.6.3 Changing Values of Bits CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before the values of bits CKS2 to CKS0 are changed. 17.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode
If the timer mode is switched from watchdog timer mode to interval timer mode while the WDT is operating, errors could occur in the incrementation. The watchdog timer must be stopped (by clearing the TME bit to 0) before switching the timer mode.
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Section 17 Watchdog Timer (WDT)
17.6.5
Internal Reset in Watchdog Timer Mode
This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer mode operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag. 17.6.6 System Reset by WDTOVF Signal
If the WDTOVF signal is input to the RES pin, this LSI will not be initialized correctly. Make sure that the WDTOVF signal is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal, use a circuit like that shown in figure 17.6.
This LSI Reset input RES
Reset signal to entire system
WDTOVF
Figure 17.6 Circuit for System Reset by WDTOVF Signal (Example) 17.6.7 Transition to Watchdog Timer Mode or Software Standby Mode
When the WDT operates in watchdog timer mode, a transition to software standby mode is not made even when the SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1. Instead, a transition to sleep mode is made. To transit to software standby mode, the SLEEP instruction must be executed after halting the WDT (clearing the TME bit to 0). When the WDT operates in interval timer mode, a transition to software standby mode is made through execution of the SLEEP instruction when the SSBY bit in SBYCR is set to 1.
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Section 17 Watchdog Timer (WDT)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Section 18 Serial Communication Interface (SCI, IrDA, CRC)
This LSI has six independent serial communication interface (SCI) channels. The SCI can handle both asynchronous and clocked synchronous serial communication. Asynchronous serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA). A function is also provided for serial communication between processors (multiprocessor communication function). The SCI also supports the smart card (smart card) interface supporting ISO/IEC 7816-3 (Identification Card) as an extended asynchronous communication mode. SCI_5 enables transmitting and receiving IrDA communication waveform based on the IrDA Specifications version 1.0. This LSI incorporates the on-chip CRC (Cyclic Redundancy Check) computing unit that realizes high reliability of high-speed data transfer. Since the CRC computing unit is not connected to SCI, operation is executed by writing data to registers. Figure 18.1 shows a block diagram of the SCI_0 to SCI_4. Figure 18.2 shows a block diagram of the SCI_5 and SCI_6.
18.1
Features
* Choice of asynchronous or clocked synchronous serial communication mode * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously. Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data. * On-chip baud rate generator allows any bit rate to be selected The external clock can be selected as a transfer clock source (except for the smart card interface). * Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data) * Four interrupt sources The interrupt sources are transmit-end, transmit-data-empty, receive-data-full, and receive error. The transmit-data-empty and receive-data-full interrupt sources can activate the DTC or DMAC. * Module stop state specifiable
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Asynchronous Mode (SCI_0, 1, 2, 4, 5, and 6): Data length: 7 or 8 bits Stop bit length: 1 or 2 bits Parity: Even, odd, or none Receive error detection: Parity, overrun, and framing errors Break detection: Break can be detected by reading the RxD pin level directly in case of a framing error * Enables average transfer rate clock input from TMR (SCI_5, SCI_6) * Average transfer rate generator (SCI_2) 10.667-MHz operation: 115.152 kbps or 460.606 kbps can be selected 16-MHz operation: 115.196 kbps, 460.784 kbps, or 720 kbps can be selected 32-MHz operation: 720 kbps * Average transfer rate generator (SCI_5, SCI_6) 8-MHz operation: 460.784 kbps can be selected 10.667-MHz operation: 115.152 kbps or 460.606 kbps can be selected 12-MHz operation: 230.263 kbps or 460.526 kbps can be selected 16-MHz operation: 115.196 kbps, 460.784 kbps, 720 kbps, or 921.569 kbps can be selected 24-MHz operation: 115.132 kbps, 460.526 kbps, 720 kbps, or 921.053 kbps can be selected 32-MHz operation: 720 kbps can be selected Clocked Synchronous Mode (SCI_0, 1, 2, and 4): * Data length: 8 bits * Receive error detection: Overrun errors Smart Card Interface: * An error signal can be automatically transmitted on detection of a parity error during reception * Data can be automatically re-transmitted on receiving an error signal during transmission * Both direct convention and inverse convention are supported * * * * *
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Table 18.1 lists the functions of each channel. Table 18.1 Function List of SCI Channels
SCI_0, 1, 4 Clocked synchronous mode Asynchronous mode TMR clock input When average transfer rate generator is used P = 8 MHz O O -- -- SCI_2 O O -- -- 460.606 kbps 115.152 kbps P = 12 MHz P = 16 MHz -- -- -- 720 kbps 460 784kbps 115.196 kbps P = 24 MHz -- -- SCI_5, SCI_6 -- O O 460.784 kbps 460.606 kbps 115.152 kbps 460.526 kbps 230.263 kbps 921.569 kbps 720 kbps 460.784 kbps 115.196 kbps 921.053 kbps 720 kbps 460.526 kbps 115.132 kbps P = 32 MHz -- 720 kbps 720 kbps
P = 10.667 MHz --
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Module data bus
RDR
TDR
SCMR SSR SCR
BRR P Baud rate generator P/4 P/16 P/64
RxD
RSR
TSR
SMR SEMR
TxD
Transmission/ reception control Parity generation Parity check Clock External clock TEI TXI RXI ERI SCR: SSR: SCMR: BRR: SEMR:
SCK
[Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register
Average transfer rate generator (SCI_2) At 10.667-MHz operation: 115.152 kbps 460.606 kbps At 16-MHz operation: 115.196 kbps 460.784 kbps 720 kbps At 32-MHz operation: 720 kbps
Serial control register Serial status register Smart card mode register Bit rate register Serial extended mode register (available only for SCI_2)
Figure 18.1 Block Diagram of SCI_0, 1, 2, and 4
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Internal data bus
Bus interface
Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Module data bus
RDR
TDR
SCMR SSR SCR
BRR P Baud rate generator P/4 P/16
RxD0
RSR
TSR
IrCR* Transmission/ reception control
Bus interface
P/64 Clock TEI TXI RXI ERI Average transfer rate generator At 8-MHz operation: 460.784 kbps At 10.667-MHz operation: 115.152 kbps 460.606 kbps At 12-MHz operation: 230.263 kbps 460.526 kbps At 16-MHz operation: 115.196 kbps 460.784 kbps 720 kbps, 921.569 kbps At 24-MHz operation: 115.132 kbps 460.526 kbps 720 kbps 921.053 kbps At 32-MHz operation: 720 kbps
TxD0 Parity check
Parity generation
Note: * SCL_5 only. [Legend] RSR: Receive shift register RDR: Receive data register TSR: Transmit shift register TDR: Transmit data register SMR: Serial mode register SCR: Serial control register SSR: Serial status register SCMR: Smart card mode register BRR: Bit rate register SEMR: Serial extended mode register IrCR: IrDA control register (available only for SCI_5)
TMO4, 6 TMO5, 7 TMR
Figure 18.2 Block Diagram of SCI_5 and SCI_6
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Internal data bus
Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.2
Input/Output Pins
Table 18.2 lists the pin configuration of the SCI. Table 18.2 Pin Configuration
Channel 0 Pin Name* SCK0 RxD0 TxD0 1 SCK1 RxD1 TxD1 2 SCK2 RxD2 TxD2 4 SCK4 RxD4 TxD4 5 RxD5/IrRxD TxD5/IrTxD 6 Note: * RxD6 TxD6 I/O I/O Input Output I/O Input Output I/O Input Output I/O Input Output Input Output Input Output Function Channel 0 clock input/output Channel 0 receive data input Channel 0 transmit data output Channel 1 clock input/output Channel 1 receive data input Channel 1 transmit data output Channel 2 clock input/output Channel 2 receive data input Channel 2 transmit data output Channel 4 clock input/output Channel 4 receive data input Channel 4 transmit data output Channel 5 receive data input Channel 5 transmit data output Channel 6 receive data input Channel 6 transmit data output
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel designation.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.3
Register Descriptions
The SCI has the following registers. Some bits in the serial mode register (SMR), serial status register (SSR), and serial control register (SCR) have different functions in different modesnormal serial communication interface mode and smart card interface mode; therefore, the bits are described separately for each mode in the corresponding register sections. Channel 0: * * * * * * * * * Receive shift register_0 (RSR_0) Transmit shift register_0 (TSR_0) Receive data register_0 (RDR_0) Transmit data register_0 (TDR_0) Serial mode register_0 (SMR_0) Serial control register_0 (SCR_0) Serial status register_0 (SSR_0) Smart card mode register_0 (SCMR_0) Bit rate register_0 (BRR_0)
Channel 1: * * * * * * * * * Receive shift register_1 (RSR_1) Transmit shift register_1 (TSR_1) Receive data register_1 (RDR_1) Transmit data register_1 (TDR_1) Serial mode register_1 (SMR_1) Serial control register_1 (SCR_1) Serial status register_1 (SSR_1) Smart card mode register_1 (SCMR_1) Bit rate register_1 (BRR_1)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Channel 2: * * * * * * * * * * Receive shift register_2 (RSR_2) Transmit shift register_2 (TSR_2) Receive data register_2 (RDR_2) Transmit data register_2 (TDR_2) Serial mode register_2 (SMR_2) Serial control register_2 (SCR_2) Serial status register_2 (SSR_2) Smart card mode register_2 (SCMR_2) Bit rate register_2 (BRR_2) Serial extended mode register_2 (SEMR_2)
Channel 4: * * * * * * * * * Receive shift register_4 (RSR_4) Transmit shift register_4 (TSR_4) Receive data register_4 (RDR_4) Transmit data register_4 (TDR_4) Serial mode register_4 (SMR_4) Serial control register_4 (SCR_4) Serial status register_4 (SSR_4) Smart card mode register_4 (SCMR_4) Bit rate register_4 (BRR_4)
Channel 5: * * * * * * * * * * * Receive shift register_5 (RSR_5) Transmit shift register_5 (TSR_5) Receive data register_5 (RDR_5) Transmit data register_5 (TDR_5) Serial mode register_5 (SMR_5) Serial control register_5 (SCR_5) Serial status register_5 (SSR_5) Smart card mode register_5 (SCMR_5) Bit rate register_5 (BRR_5) Serial extended mode register_5 (SEMR_5) IrDA control register_5 (IrCR)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Channel 6: * * * * * * * * * * Receive shift register_6 (RSR_6) Transmit shift register_6 (TSR_6) Receive data register_6 (RDR_6) Transmit data register_6 (TDR_6) Serial mode register_6 (SMR_6) Serial control register_6 (SCR_6) Serial status register_6 (SSR_6) Smart card mode register_6 (SCMR_6) Bit rate register_6 (BRR_6) Serial extended mode register_6 (SEMR_6)
18.3.1
Receive Shift Register (RSR)
RSR is a shift register which is used to receive serial data input from the RxD pin and converts it into parallel data. When one frame of data has been received, it is transferred to RDR automatically. RSR cannot be directly accessed by the CPU. 18.3.2 Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI has received one frame of serial data, it transfers the received serial data from RSR to RDR where it is stored. This allows RSR to receive the next data. Since RSR and RDR function as a double buffer in this way, continuous receive operations can be performed. After confirming that the RDRF bit in SSR is set to 1, read RDR only once. RDR cannot be written to by the CPU.
Bit Bit Name Initial Value R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 7 6 5 4 3 2 1 0
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.3.3
Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered structures of TDR and TSR enable continuous serial transmission. If the next transmit data has already been written to TDR when one frame of data is transmitted, the SCI transfers the written data to TSR to continue transmission. Although TDR can be read from or written to by the CPU at all times, to achieve reliable serial transmission, write transmit data to TDR for only once after confirming that the TDRE bit in SSR is set to 1.
Bit Bit Name Initial Value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 6 5 4 3 2 1 0
18.3.4
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first automatically transfers transmit data from TDR to TSR, and then sends the data to the TxD pin. TSR cannot be directly accessed by the CPU. 18.3.5 Serial Mode Register (SMR)
SMR is used to set the SCI's serial transfer format and select the baud rate generator clock source. Some bits in SMR have different functions in normal mode and smart card interface mode. * When SMIF in SCMR = 0
Bit Bit Name Initial Value R/W 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
* When SMIF in SCMR = 1
Bit Bit Name Initial Value R/W 7 GM 0 R/W 6 BLK 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 BCP1 0 R/W 2 BCP0 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode 0: Asynchronous mode 1: Clocked synchronous mode* 6 CHR 0 R/W Character Length (valid only in asynchronous mode) 0: Selects 8 bits as the data length. 1: Selects 7 bits as the data length. LSB-first is fixed and the MSB (bit 7) in TDR is not transmitted in transmission. In clocked synchronous mode, a fixed data length of 8 bits is used. 5 PE 0 R/W Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. For a multiprocessor format, parity bit addition and checking are not performed regardless of the PE bit setting. 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity. 1: Selects odd parity. 3 STOP 0 R/W Stop Bit Length (valid only in asynchronous mode) Selects the stop bit length in transmission. 0: 1 stop bit 1: 2 stop bits In reception, only the first stop bit is checked. If the second stop bit is 0, it is treated as the start bit of the next transmit frame. 2 MP 0 R/W Multiprocessor Mode (valid only in asynchronous mode) When this bit is set to 1, the multiprocessor function is enabled. The PE bit and O/E bit settings are invalid in multiprocessor mode.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 1 0
Bit Name CKS1 CKS0
Initial Value 0 0
R/W R/W R/W
Description Clock Select 1, 0 These bits select the clock source for the baud rate generator. 00: P clock (n = 0) 01: P/4 clock (n = 1) 10: P/16 clock (n = 2) 11: P/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 18.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 18.3.9, Bit Rate Register (BRR)).
Note:
*
Available in SCI_0, 1, 2, and 4 only. Setting is prohibited in SCI_5 and SCI_6.
Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1):
Bit 7 Bit Name GM Initial Value 0 R/W R/W Description GSM Mode Setting this bit to 1 allows GSM mode operation. In GSM mode, the TEND set timing is put forward to 11.0 etu from the start and the clock output control function is appended. For details, see sections 18.7.6, Data Transmission (Except in Block Transfer Mode) and 18.7.8, Clock Output Control (only SCI_0, 1, 2, and 4). 6 5 BLK PE 0 0 R/W R/W Setting this bit to 1 allows block transfer mode operation. For details, see section 18.7.3, Block Transfer Mode. Parity Enable (valid only in asynchronous mode) When this bit is set to 1, the parity bit is added to transmit data before transmission, and the parity bit is checked in reception. Set this bit to 1 in smart card interface mode. 4 O/E 0 R/W Parity Mode (valid only when the PE bit is 1 in asynchronous mode) 0: Selects even parity 1: Selects odd parity For details on the usage of this bit in smart card interface mode, see section 18.7.2, Data Format (Except in Block Transfer Mode).
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 3 2
Bit Name BCP1 BCP0
Initial Value 0 0
R/W R/W R/W
Description Base clock Pulse 1, 0 These bits select the number of base clock cycles in a 1bit data transfer time in smart card interface mode. 00: 32 clock cycles (S = 32) 01: 64 clock cycles (S = 64) 10: 372 clock cycles (S = 372) 11: 256 clock cycles (S = 256) For details, see section 18.7.4, Receive Data Sampling Timing and Reception Margin. S is described in section 18.3.9, Bit Rate Register (BRR).
1 0
CKS1 CKS0
0 0
R/W R/W
Clock Select 1, 0 These bits select the clock source for the baud rate generator. 00: P clock (n = 0) 01: P/4 clock (n = 1) 10: P/16 clock (n = 2) 11: P/64 clock (n = 3) For the relation between the settings of these bits and the baud rate, see section 18.3.9, Bit Rate Register (BRR). n is the decimal display of the value of n in BRR (see section 18.3.9, Bit Rate Register (BRR)).
Note:
etu (Elementary Time Unit): 1-bit transfer time
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.3.6
Serial Control Register (SCR)
SCR is a register that enables/disables the following SCI transfer operations and interrupt requests, and selects the transfer clock source. For details on interrupt requests, see section 18.9, Interrupt Sources. Some bits in SCR have different functions in normal mode and smart card interface mode. * When SMIF in SCMR = 0
Bit Bit Name Initial Value R/W 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W
* When SMIF in SCMR = 1
Bit Bit Name Initial Value R/W 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W
* Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1, a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 5
Bit Name TE
Initial Value 0
R/W R/W
Description Transmit Enable When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed to 1.
4
RE
0
R/W
Receive Enable When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained.
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (valid only when the MP bit in SMR is 1 in asynchronous mode) When this bit is set to 1, receive data in which the multiprocessor bit is 0 is skipped, and setting of the RDRF, FER, and ORER status flags in SSR is disabled. On receiving data in which the multiprocessor bit is 1, this bit is automatically cleared and normal reception is resumed. For details, see section 18.5, Multiprocessor Communication Function. When receive data including MPB = 0 in SSR is being received, transfer of the received data from RSR to RDR, detection of reception errors, and the settings of RDRF, FER, and ORER flags in SSR are not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is automatically cleared to 0, and RXI and ERI interrupt requests (in the case where the TIE and RIE bits in SCR are set to 1) and setting of the FER and ORER flags are enabled.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 2
Bit Name TEIE
Initial Value 0
R/W R/W
Description Transmit End Interrupt Enable When this bit is set to 1, a TEI interrupt request is enabled. A TEI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0 in order to clear the TEND flag to 0, or by clearing the TEIE bit to 0.
1 0
CKE1 CKE0
0 0
R/W R/W
Clock Enable 1, 0 (for SCI_0, 1, and 4) These bits select the clock source and SCK pin function. * Asynchronous mode The SCK pin functions as I/O port. 01: On-chip baud rate generator The clock with the same frequency as the bit rate is output from the SCK pin. 1X: External clock The clock with a frequency 16 times the bit rate should be input from the SCK pin. * Clocked synchronous mode The SCK pin functions as the clock output pin. 1X: External clock The SCK pin functions as the clock input pin. 0X: Internal clock 00: On-chip baud rate generator
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 1 0
Bit Name CKE1 CKE0
Initial Value 0 0
R/W R/W R/W
Description Clock Enable 1, 0 (for SCI_2) These bits select the clock source and SCK pin function. * Asynchronous mode The SCK pin functions as I/O port. 01: On-chip baud rate generator The clock with the same frequency as the bit rate is output from the SCK pin. 1X: External clock or average transfer rate generator When an external clock is used, the clock with a frequency 16 times the bit rate should be input from the SCK pin. When an average transfer rate generator is used. * Clocked synchronous mode The SCK pin functions as the clock output pin. 1X: External clock The SCK pin functions as the clock input pin. 0X: Internal clock 00: On-chip baud rate generator
1 0
CKE1 CKE0
0 0
R/W R/W
Clock Enable 1, 0 (for SCI_5 and SCI_6) These bits select the clock source. * Asynchronous mode 00: On-chip baud rate generator 1X: TMR clock input or average transfer rate generator When an average transfer rate generator is used. When TMR clock input is used. * Clocked synchronous mode Not available
[Legend] X: Don't care
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
* Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1):
Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable When this bit is set to 1,a TXI interrupt request is enabled. A TXI interrupt request can be cancelled by reading 1 from the TDRE flag and then clearing the flag to 0, or by clearing the TIE bit to 0. 6 RIE 0 R/W Receive Interrupt Enable When this bit is set to 1, RXI and ERI interrupt requests are enabled. RXI and ERI interrupt requests can be cancelled by reading 1 from the RDRF, FER, PER, or ORER flag and then clearing the flag to 0, or by clearing the RIE bit to 0. 5 TE 0 R/W Transmit Enable When this bit is set to 1, transmission is enabled. Under this condition, serial transmission is started by writing transmit data to TDR, and clearing the TDRE flag in SSR to 0. Note that SMR should be set prior to setting the TE bit to 1 in order to designate the transmission format. If transmission is halted by clearing this bit to 0, the TDRE flag in SSR is fixed 1. 4 RE 0 R/W Receive Enable When this bit is set to 1, reception is enabled. Under this condition, serial reception is started by detecting the start bit in asynchronous mode or the synchronous clock input in clocked synchronous mode. Note that SMR should be set prior to setting the RE bit to 1 in order to designate the reception format. Even if reception is halted by clearing this bit to 0, the RDRF, FER, PER, and ORER flags are not affected and the previous value is retained. 3 MPIE 0 R/W Multiprocessor Interrupt Enable (valid only when the MP bit in SMR is 1 in asynchronous mode) Write 0 to this bit in smart card interface mode. 2 TEIE 0 R/W Transmit End Interrupt Enable Write 0 to this bit in smart card interface mode.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 1 0
Bit Name CKE1 CKE0
Initial Value 0 0
R/W R/W R/W
Description Clock Enable 1, 0* These bits control the clock output from the SCK pin. In GSM mode, clock output can be dynamically switched. For details, see section 18.7.8, Clock Output Control (only SCI_0, 1, 2, and 4). * When GM in SMR = 0 00: Output disabled (SCK pin functions as I/O port.) * 01: Clock output 1X: Reserved * When GM in SMR = 1 00: Output fixed low 01: Clock output 10: Output fixed high 11: Clock output
Note:
*
No SCK pins exist in SCI_5 and SCI_6.
18.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE, RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in normal mode and smart card interface mode. * When SMIF in SCMR = 0
Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W
Note: * Only 0 can be written, to clear the flag.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
* When SMIF in SCMR = 1
Bit Bit Name Initial Value R/W 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W
Note: * Only 0 can be written, to clear the flag.
Bit Functions in Normal Serial Communication Interface Mode (When SMIF in SCMR = 0):
Bit 7 Bit Name TDRE Initial Value 1 R/W Description
R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When a TXI interrupt request is issued allowing DMAC or DTC to write data to TDR
[Clearing conditions]
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 6
Bit Name RDRF
Initial Value 0
R/W
Description
R/(W)* Receive Data Register Full Indicates whether receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When an RXI interrupt request is issued allowing DMAC or DTC to read data from RDR
[Clearing conditions] *
The RDRF flag is not affected and retains its previous value when the RE bit in SCR is cleared to 0. Note that when the next serial reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost. 5 ORER 0 R/(W)* Overrun Error Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition] * When the next serial reception is completed while RDRF = 1 In RDR, receive data prior to an overrun error occurrence is retained, but data received after the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to ORER after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 4
Bit Name FER
Initial Value 0
R/W
Description
R/(W)* Framing Error Indicates that a framing error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] * When the stop bit is 0 In 2-stop-bit mode, only the first stop bit is checked whether it is 1 but the second stop bit is not checked. Note that receive data when the framing error occurs is transferred to RDR, however, the RDRF flag is not set. In addition, when the FER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to FER after reading FER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the FER flag is not affected and retains its previous value.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 3
Bit Name PER
Initial Value 0
R/W
Description
R/(W)* Parity Error Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] * When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to PER after reading PER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the PER bit is not affected and retains its previous value.
2
TEND
1
R
Transmit End [Setting conditions] * * When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a transmit character When 0 is written to TDRE after reading TDRE = 1 When a TXI interrupt request is issued allowing DMAC or DTC to write data to TDR
[Clearing conditions] * * 1 MPB 0 R
Multiprocessor Bit Stores the multiprocessor bit value in the receive frame. When the RE bit in SCR is cleared to 0 its previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer Sets the multiprocessor bit value to be added to the transmit frame.
Note:
*
Only 0 can be written, to clear the flag.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit Functions in Smart Card Interface Mode (When SMIF in SCMR = 1):
Bit 7 Bit Name TDRE Initial Value 1 R/W Description
R/(W)* Transmit Data Register Empty Indicates whether TDR contains transmit data. [Setting conditions] * * * When the TE bit in SCR is 0 When data is transferred from TDR to TSR When 0 is written to TDRE after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When a TXI interrupt request is issued allowing DMAC or DTC to write data to TDR
[Clearing conditions]
6
RDRF
0
R/(W)* Receive Data Register Full Indicates whether receive data is stored in RDR. [Setting condition] * When serial reception ends normally and receive data is transferred from RSR to RDR When 0 is written to RDRF after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When an RXI interrupt request is issued allowing DMAC or DTC to read data from RDR
[Clearing conditions] *
The RDRF flag is not affected and retains its previous value even when the RE bit in SCR is cleared to 0. Note that when the next reception is completed while the RDRF flag is being set to 1, an overrun error occurs and the received data is lost.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 5
Bit Name ORER
Initial Value 0
R/W
Description Indicates that an overrun error has occurred during reception and the reception ends abnormally. [Setting condition] * When the next serial reception is completed while RDRF = 1 In RDR, the receive data prior to an overrun error occurrence is retained, but data received following the overrun error occurrence is lost. When the ORER flag is set to 1, subsequent serial reception cannot be performed. Note that, in clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to ORER after reading ORER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the ORER flag is not affected and retains its previous value.
R/(W)* Overrun Error
4
ERS
0
R/(W)* Error Signal Status [Setting condition] * * When a low error signal is sampled When 0 is written to ERS after reading ERS = 1 [Clearing condition]
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 3
Bit Name PER
Initial Value 0
R/W
Description Indicates that a parity error has occurred during reception in asynchronous mode and the reception ends abnormally. [Setting condition] * When a parity error is detected during reception Receive data when the parity error occurs is transferred to RDR, however, the RDRF flag is not set. Note that when the PER flag is being set to 1, the subsequent serial reception cannot be performed. In clocked synchronous mode, serial transmission also cannot continue. [Clearing condition] * When 0 is written to PER after reading PER = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) Even when the RE bit in SCR is cleared, the PER flag is not affected and retains its previous value.
R/(W)* Parity Error
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 2
Bit Name TEND
Initial Value 1
R/W R
Description Transmit End This bit is set to 1 when no error signal is sent from the receiving side and the next transmit data is ready to be transferred to TDR. [Setting conditions] * * When both the TE and ERS bits in SCR are 0 When ERS = 0 and TDRE = 1 after a specified time passed after completion of 1-byte data transfer. The set timing depends on the register setting as follows: When GM = 0 and BLK = 0, 2.5 etu after transmission start When GM = 0 and BLK = 1, 1.5 etu after transmission start When GM = 1 and BLK = 0, 1.0 etu after transmission start When GM = 1 and BLK = 1, 1.0 etu after transmission start [Clearing conditions] * * When 0 is written to TEND after reading TEND = 1 When a TXI interrupt request is issued allowing DMAC or DTC to write the next data to TDR
1 0 Note: *
MPB MPBT
0 0
R R/W
Multiprocessor Bit Not used in smart card interface mode. Multiprocessor Bit Transfer Write 0 to this bit in smart card interface mode.
Only 0 can be written, to clear the flag.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.3.8
Smart Card Mode Register (SCMR)
SCMR selects smart card interface mode and its format.
Bit Bit Name Initial Value R/W 7 1 6 1 5 1 4 1 3 SDIR 0 R/W 2 SINV 0 R/W 1 1 0 SMIF 0 R/W
Bit 7 to 4 3
Bit Name SDIR
Initial Value All 1 0
R/W R/W
Description Reserved These bits are always read as 1. Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: Transfer with LSB-first 1: Transfer with MSB-first This bit is valid only when the 8-bit data format is used for transmission/reception; when the 7-bit data format is used, data is always transmitted/received with LSB-first.
2
SINV
0
R/W
Smart Card Data Invert Inverts the transmit/receive data logic level. This bit does not affect the logic level of the parity bit. To invert the parity bit, invert the O/E bit in SMR. 0: TDR contents are transmitted as they are. Receive data is stored as it is in RDR. 1: TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR.
1 0
SMIF
1 0
R/W
Reserved This bit is always read as 1. Smart Card Interface Mode Select When this bit is set to 1, smart card interface mode is selected. 0: Normal asynchronous or clocked synchronous mode 1: Smart card interface mode
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control independently for each channel, different bit rates can be set for each channel. Table 18.3 shows the relationships between the N setting in BRR and bit rate B for normal asynchronous mode and clocked synchronous mode, and smart card interface mode. The initial value of BRR is H'FF, and it can be read from or written to by the CPU at all times. Table 18.3 Relationships between N Setting in BRR and Bit Rate B
Mode Asynchronous mode ABCS Bit Bit Rate 0
N= P x 10 64 x 2
6 2n - 1
Error
-1 xB -1 Error (%) = { Error (%) = { P x 106 B x 64 x 2
2n - 1
- 1 } x 100 x (N + 1) - 1 } x 100 x (N + 1)
1 Clocked synchronous mode Smart card interface mode [Legend] B: N: P: n and S:
N=
P x 106 32 x 2
2n - 1
P x 106 B x 32 x 2
2n - 1
xB -1
N=
P x 106 8x2
2n - 1
xB -1
P x 106 Error (%) = { BxSx2
2n + 1
N=
P x 106 Sx2
2n + 1
xB
- 1 } x 100 x (N + 1)
Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Determined by the SMR settings shown in the following table. SMR Setting SMR Setting n 0 1 2 3 BCP1 0 0 1 1 BCP0 0 1 0 1 S 32 64 372 256
CKS1 0 0 1 1
CKS0 0 1 0 1
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Table 18.4 shows sample N settings in BRR in normal asynchronous mode. Table 18.5 shows the maximum bit rate settable for each operating frequency. Tables 18.7 and 18.9 show sample N settings in BRR in clocked synchronous mode and smart card interface mode, respectively. In smart card interface mode, the number of base clock cycles S in a 1-bit data transfer time can be selected. For details, see section 18.7.4, Receive Data Sampling Timing and Reception Margin. Tables 18.6 and 18.8 show the maximum bit rates with external clock input. When the ABCS bit in the serial extended mode register_2, 5, and 6 (SEMR_2, 5, and 6) of SCI_2, 5, and 6 are set to 1 in asynchronous mode, the bit rate is two times that of shown in table 18.4. Table 18.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency P (MHz) 8 Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 1 1 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 2 2 1 1 0 0 0 0 0 0 0 9.8304 N 174 127 255 127 255 127 63 31 15 9 7 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 10 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 n 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -2.34 0.00 -2.34
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Operating Frequency P (MHz) 12.288 Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 2 1 1 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 14 Error (%) -0.17 0.16 0.16 0.16 0.16 0.16 0.16 -0.93 -0.93 0.00 n 3 2 2 1 1 0 0 0 0 0 0 14.7456 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16
Note: In SCI_2, 5, and 6, this is an example when the ABCS bit in SEMR_2, 5, and 6 is 0. When the ABCS bit is set to 1, the bit rate is two times.
Table 18.4 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
Operating Frequency P (MHz) 17.2032 Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 16 13 Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 18 Error (%) -0.12 0.16 0.16 0.16 0.16 0.16 0.16 -0.69 1.02 0.00 -2.34 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Operating Frequency P (MHz) 25 Bit Rate (bit/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 3 3 2 2 1 1 0 0 0 0 0 N 110 80 162 80 162 80 162 80 40 24 19 Error (%) -0.02 -0.47 0.15 -0.47 0.15 -0.47 0.15 -0.47 -0.76 0.00 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 132 97 194 97 194 97 194 97 48 29 23 30 Error (%) 0.13 -0.35 0.16 -0.35 0.16 -0.35 0.16 -0.35 -0.35 0 1.73 n 3 3 2 2 1 1 0 0 0 0 0 N 145 106 214 106 214 106 214 106 53 32 26 33 Error (%) 0.33 0.39 -0.07 0.39 -0.07 0.39 -0.07 0.39 -0.54 0 -0.54 n 3 3 2 2 1 1 0 0 0 0 0 N 154 113 227 113 227 113 227 113 56 34 27 35 Error (%) 0.23 -0.06 -0.06 -0.06 -0.06 -0.06 -0.06 -0.06 -0.06 0.00 1.73
Note: In SCI_2, 5, and 6, this is an example when the ABCS bit in SEMR_2, 5, and 6 is 0. When the ABCS bit is set to 1, the bit rate is two times.
Table 18.5 Maximum Bit Rate for Each Operating Frequency (Asynchronous Mode)
Maximum Bit Rate (bit/s) 250000 307200 312500 375000 384000 437500 460800 500000 Maximum Bit Rate (bit/s) 537600 562500 614400 625000 781250 937500 1031250 1093750
P (MHz) 8 9.8304 10 12 12.288 14 14.7456 16
n 0 0 0 0 0 0 0 0
N 0 0 0 0 0 0 0 0
P (MHz) 17.2032 18 19.6608 20 25 30 33 35
n 0 0 0 0 0 0 0 0
N 0 0 0 0 0 0 0 0
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Table 18.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
P (MHz) 8 9.8304 10 12 12.288 14 14.7456 16 External Input Clock (MHz) 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 Maximum Bit Rate (bit/s) 125000 153600 156250 187500 192000 218750 230400 250000 P (MHz) 17.2032 18 19.6608 20 25 30 33 35 External Input Clock (MHz) 4.3008 4.5000 4.9152 5.0000 6.2500 7.5000 8.2500 8.7500 Maximum Bit Rate (bit/s) 268800 281250 307200 312500 390625 468750 515625 546875
Note: In SCI_2, this is an example when the ABCS bit in SEMR_2 is 0. When the ABCS bit is set to 1, the bit rate is two times.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Table 18.7 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)*2
Operating Frequency P (MHz) Bit Rate (bit/s) 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2.5M 5M 3 2 2 1 1 0 0 0 0 0 0 0 124 -- 249 -- 124 -- 199 1 99 79 39 19 7 3 1 0 0*1 1 0 0 0 0 0 199 0 -- -- -- 3 3 2 249 124 -- 249 -- 99 99 79 39 15 7 3 2 1 0 0 0 0 0 0 0 199 1 159 0 -- -- 3 97 77 124 2 249 2 124 1 199 0 99 49 19 9 4 1 0*
1
8 n N n
10 N n
16 N n
20 N n
25 N n
30 N n
33 N n
35 N
3 3 2 155 2 155 1 249 1 124 0 62 24 -- -- -- -- 0 0 0 -- 0 --
233 116 3 187 2 93 74 74 29 14 -- 2 -- 2 1 0 0 -- -- -- -- 187 1 149 0 128 3 205 2 102 2 205 1 82 82 32 -- -- -- -- 1 0 0 -- -- -- -- 164 0 136 218 108 218 87 174 87 34 -- -- -- --
249 2 124 1 249 1 99 49 24 9 4 0 0 0 0 0 0
0 0 0 -- -- -- --
[Legend] Space: Setting prohibited. : Can be set, but there will be error. Notes: 1. Continuous transmission or reception is not possible. 2. No clocked synchronous mode exists in SCI_5 and SCI_6.
Table 18.8 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)*
P (MHz) 8 10 12 14 16 18 Note * External Input Clock (MHz) 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 Maximum Bit Rate (bit/s) 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 P (MHz) 20 25 30 33 35 External Input Clock (MHz) 3.3333 4.1667 5.0000 5.5000 5.8336 Maximum Bit Rate (bit/s) 3333333.3 4166666.7 5000000.0 5500000.0 5833625.0
No clocked synchronous mode exists in SCI_5 and SCI_6.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Table 18.9 BRR Settings for Various Bit Rates (Smart Card Interface Mode, n = 0, S = 372)
Operating Frequency P (MHz) 7.1424 Bit Rate (bit/sec) 9600 0 0 0.00 0 1 30 0 1 n N Error (%) n N 10.00 Error (%) n 10.7136 N Error (%) 25 n 0 N 1 13.00 Error (%) 8.99
Operating Frequency P (MHz) 14.2848 Bit Rate (bit/sec) 9600 0 1 0.00 0 1 12.01 0 2 n N Error (%) n N 16.00 Error (%) n 18.00 N Error (%) 15.99 n 0 N 2 20.00 Error (%) 6.66
Operating Frequency P (MHz) 25.00 Bit Rate (bit/sec) 9600 0 3 12.49 0 3 5.01 0 4 n N Error (%) n N 30.00 Error (%) n 33.00 N Error (%) 7.59 n 0 N 4 35.00 Error (%) 1.99
Table 18.10 Maximum Bit Rate for Each Operating Frequency (Smart Card Interface Mode, S = 372)
P (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 n 0 0 0 0 0 0 N 0 0 0 0 0 0 P (MHz) 18.00 20.00 25.00 30.00 33.00 35.00 Maximum Bit Rate (bit/s) 24194 26882 33602 40323 44355 47043 n 0 0 0 0 0 0 N 0 0 0 0 0 0
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.3.10 Serial Extended Mode Register (SEMR_2) SEMR_2 selects the clock source in asynchronous mode of SCI_2. The base clock is automatically specified when the average transfer rate operation is selected.
Bit Bit Name Initial Value R/W 7 Undefined R 6 Undefined R 5 Undefined R 4 Undefined R 3 ABCS 0 R/W 2 ACS2 0 R/W 1 ACS1 0 R/W 0 ACS0 0 R/W
Bit 7 to 4
Bit Name
Initial Value
R/W
Description Reserved These bits are always read as undefined and cannot be modified.
Undefined R
3
ABCS
0
R/W
Asynchronous Mode Base clock Select (valid only in asynchronous mode) Selects the base clock for a 1-bit period. 0: The base clock has a frequency 16 times the transfer rate 1: The base clock has a frequency 8 times the transfer rate
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 2 1 0
Bit Name ACS2 ACS1 ACS0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Asynchronous Mode Clock Source Select (valid when CKE1 = 1 in asynchronous mode) These bits select the clock source for the average transfer rate function. When the average transfer rate function is enabled, the base clock is automatically specified regardless of the ABCS bit value. 000: External clock input 001: 115.152 kbps of average transfer rate specific to P = 10.667 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 010: 460.606 kbps of average transfer rate specific to P = 10.667 MHz is selected (operated using the base clock with a frequency 8 times the transfer rate) 011: 720 kbps of average transfer rate specific to P = 32 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 100: Setting prohibited 101: 115.196 kbps of average transfer rate specific to P = 16 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 110: 460.784 kbps of average transfer rate specific to P = 16 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 111: 720 kbps of average transfer rate specific to P = 16 MHz is selected (operated using the base clock with a frequency 8 times the transfer rate) The average transfer rate only supports operating frequencies of 10.667 MHz, 16 MHz, and 32 MHz.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.3.11 Serial Extended Mode Register 5 and 6 (SEMR_5 and SEMR_6) SEMR_5 and SEMR_6 select the clock source in asynchronous mode of SCI_5 and SCI_6. The base clock is automatically specified when the average transfer rate operation is selected. TMQ output in TMR unit 2 and unit 3 can also be set as the serial transfer base clock. Figure 18.3 describes the examples of base clock features when the average transfer rate operation is selected. Figure 18.4 describes the examples of base clock features when the TMO output in TMR is selected.
Bit Bit Name Initial Value R/W 7 Undefined R 6 Undefined R 5 Undefined R 4 ABCS 0 R/W 3 ACS3 0 R/W 2 ACS2 0 R/W 1 ACS1 0 R/W 0 ACS0 0 R/W
Bit 7 to 5
Bit Name
Initial Value
R/W
Description Reserved These bits are always read as undefined and cannot be modified. Asynchronous Mode Base Clock Select (valid only in asynchronous mode) Selects the base clock for a 1-bit period. 0: The base clock has a frequency 16 times the transfer rate 1: The base clock has a frequency 8 times the transfer rate Asynchronous Mode Clock Source Select These bits select the clock source for the average transfer rate function in the asynchronous mode. When the average transfer rate function is enabled, the base clock is automatically specified regardless of the ABCS bit value. The average transfer rate only corresponds to 8MHz, 10.667MHz, 12MHz, 16MHz, 24MHz, and 32MHz. No other clock is available. Setting of ACS3 to ACS0 must be done in the asynchronous mode (the C/A bit in SMR = 0) and the external clock input mode (the CKE bit I SCR = 1). The setting examples are in figures 18.3 and 18.4. (Each number in the four-digit number below corresponds to the value in the bits ACS3 to ACS0 from left to right respectively.)
Undefined R
4
ABCS
0
R/W
3 2 1 0
ACS3 ACS2 ACS1 ACS0
0 0 0 0
R/W R/W R/W R/W
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 3 2 1 0
Bit Name ACS3 ACS2 ACS1 ACS0
Initial Value 0 0 0 0
R/W R/W R/W R/W R/W
Description 0000: Average transfer rate generator is not used. 0001: 115.152 kbps of average transfer rate specific to P = 10.667 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 0010: 460.606 kbps of average transfer rate specific to P = 10.667 MHz is selected (operated using the base clock with a frequency 8 times the transfer rate) 0011: 921.569 kbps of average transfer rate specific to P = 16 MHz is selected or 460.784 kbps of average transfer rate specific to P = 8MHz is selected (operated using the base clock with a frequency 8 times the transfer rate) 0100: TMR clock input This setting allows the TMR compare match output to be used as the base clock. The table below shows the correspondence between the SCI channels and the compare match output. Compare Match TMR Unit Output Unit 2 TMO4, TMO5 Unit 3 TMO6, TMO7
SCI Channel SCI_5 SCI_6
0101: 115.196 kbps of average transfer rate specific to P = 16 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 0110: 460.784 kbps of average transfer rate specific to P = 16 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 0111: 720 kbps of average transfer rate specific to P = 16 MHz is selected (operated using the base clock with a frequency 8 times the transfer rate)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 3 2 1 0
Bit Name ACS3 ACS2 ACS1 ACS0
Initial Value 0 0 0 0
R/W R/W R/W R/W R/W
Description 1000: 115.132 kbps of average transfer rate specific to P = 24 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 1001: 460.526 kbps of average transfer rate specific to P = 24 or MHz or 230.263 kbps of average transfer rate specific to P = 12MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 1010: 720 kbps of average transfer rate specific to P = 24 MHz is selected (operated using the base clock with a frequency 8 times the transfer rate) 1011: 921.053 kbps of average transfer rate specific to P = 24 or MHz or 460.526 kbps of average transfer rate specific to P = 12MHz is selected (operated using the base clock with a frequency 8 times the transfer rate) 1100: 720 kbps of average transfer rate specific to P = 32 MHz is selected (operated using the base clock with a frequency 16 times the transfer rate) 1101: Reserved (setting prohibited) 111x: Reserved (setting prohibited)
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When = 10.667 MHz
Base clock with 115.152-kbps average transfer rate (ACS3 to 0 = B'0001)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 2 3 4 2.667 MHz 1.8424 MHz 45 67 89 10 11 12 13 14 15 16
Base clock 10.667 MHz/4= 2.667 MHz 2.667 MHz x (38/55) = 1.8424 MHz (Average) 1 bit = Base clock x 16*
123
Average transfer rate = 1.8424 MHz/16 = 115.152 kbps Average error with 115.2 kbps = -0.043%
Base clock with 460.606-kbps average transfer rate (ACS3 to 0 = B'0010)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 1 2 3 4 5.333 MHz 3.6848 MHz 45 67 8
Base clock 10.667 MHz/2 = 5.333 MHz 5.333 MHz x (38/55) = 3.6848 MHz (Average) 1 bit = Base clock x 8*
123
Average transfer rate = 3.6848 MHz/8 = 460.606 kbps Average error with 460.6 kbps = -0.043%
Figure 18.3 Examples of Base Clock when Average Transfer Rate Is Selected (1)
Section 18 Serial Communication Interface (SCI, IrDA, CRC)
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Note: * The length of one bit varies according to the base clock synchronization.
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When = 16 MHz
Base clock with 115.196-kbps average transfer rate (ACS3 to 0 = B'0101) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 2 MHz 1.8431 MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 bit = Base clock x 16* Average transfer rate = 1.8431 MHz/16 = 115.196 kbps Average error with 115.2 kbps = -0.004%
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Average transfer rate = 7.3725 MHz/16 = 460.784 kbps Average error with 460.8 kbps = -0.004% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 8 MHz 5.76 MHz 123 45 678 1 bit = Base clock x 8* Average transfer rate = 5.76 MHz/8 = 720 kbps Average error with 720 kbps = 0% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 8 MHz 7.3725 MHz 12345678 1 bit = Base clock x 8* Average transfer rate = 7.3725 MHz/8 = 921.569 kbps Average error with 921.6 kbps = -0.003%
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Base clock 16 MHz/8 = 2 MHz 2 MHz x (47/51) = 1.8431 MHz (Average)
Base clock with 460.784-kbps average transfer rate (ACS3 to 0 = B'0110) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 1 2 3 4 5 6 7 8 Base clock 8 MHz 16 MHz/2 = 8 MHz 8 MHz x (47/51) 7.3725 MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 = 7.3725 MHz (Average) 1 bit = Base clock x 16*
Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Base clock with 720-kbps average transfer rate (ACS3 to 0 = B'0111)
Base clock 16 MHz/2 = 8 MHz 8 MHz x (18/25) = 5.76 MHz (Average)
Base clock with 921.569-kbps average transfer rate (ACS3 to 0 = B'0011)
Base clock 16 MHz/2 = 8 MHz 8 MHz x (47/51) = 7.3725 MHz (Average)
Figure 18.3 Examples of Base Clock when Average Transfer Rate Is Selected (2)
Note: * The length of one bit varies according to the base clock synchronization.
When = 24 MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 3 MHz 1 67 89 10 11 12 13 14 15 16 1 bit = Base clock x 16* Average transfer rate =1.8421 MHz/16 = 115.132 kbps Average error with 115.2 kbps = -0.059% 1.8421 MHz 23 45
Base clock with 115.132-kbps average transfer rate (ACS3 to 0 = B'1000)
Base clock 24 MHz/8 = 3 MHz 3 MHz x (35/57) = 1.8421 MHz (average)
Base clock with 460.526-kbps average transfer rate (ACS3 to 0 = B'1001) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 12 MHz 1 67 89 10 11 12 13 14 15 16 1 bit = Base clock x 16* Average transfer rate = 7.3684 MHz/16 = 460.526 kbps Average error with 921.6 kbps = -0.059% 7.3684 MHz 23 45
Base clock 24 MHz/2 = 12 MHz 12 MHz x (35/57) = 7.3684 MHz (Average)
Base clock with 720-kbps average transfer rate (ACS3 to 0 = B'1010) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 12 MHz 5.76 MHz 1 bit = Base clock x 8* Average transfer rate = 5.76 MHz/8= 720 kbps Average error with 720 kbps = 0%
Base clock 24 MHz/2 = 12 MHz 12 MHz x (12/25) = 5.76 MHz (Average)
Base clock with 921.053-kbps average transfer rate (ACS3 to 0 = B'1011) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 1 2 12 MHz 1 8 7.3684 MHz 23 45 67 1 bit = Base clock x 8*
Base clock 24 MHz/2 = 12 MHz 12 MHz x (35/57) = 7.3684 MHz (Average)
Average transfer rate = 7.3684 MHz/8= 921.053 kbps Average error with 921.6 kbps = -0.059%
Figure 18.3 Examples of Base Clock when Average Transfer Rate Is Selected (3)
Section 18 Serial Communication Interface (SCI, IrDA, CRC)
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Note: * The length of one bit varies according to the base clock synchronization.
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SCI_5 Clock enable Base clock SCK5 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 4 MHz 3 MHz 1 1 bit = Base clock x 16 Average transfer rate = 3 MHz/16 = 187.5 kbps 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1 2 3 4 5 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3
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Example when TMR clock input is used in SCI_5 187.5-kbps average transfer rate is generated by TMR when = 32 MHz (1) TMO4 is set as a base clock and generates 4 MHz. (2) TMO5 is set as TCNT_4 compare match count and generates a clock enable multiplied by 3/4. The average transfer rate will be 3 MHz/16 = 187.5 kbps.
Section 18 Serial Communication Interface (SCI, IrDA, CRC)
TMR and SCI Settings: TMR (Unit 2) * TCR_4 = H'09 (TCNT4 cleared by TCORA_4 compare match, TCNT4 incremented at rising edge of P/2) * TCCR_4 = H'01 TMO5 * TCR_5 = H'0C (TCNT5 cleared by TCORA_5 compare match, TCNT5 incremented by TCNT_4 compare match A) TMO4 * TCCR_5 = H'00 * TCSR_4 = H'09 (0 output on TCORA_4 compare match, 1 output on TCORB_4 compare match) * TCSR_5 = H'09 (0 output on TCORA_5 compare match, 1 output on TCORB_5 compare match) * TCNT_4 = TCNT_5 = 0 * TCORA_4 = H'03, TCORB_4 = H'01 * TCORA_5 = H'03, TCORB_5 = H'00 * SEMR_5 = H'04 When SCI_6 is used, set TMO6 as a base clock and TMO7 as a clock enable.
Base clock TMO4 output = 4 MHz
Clock enable TMO5 output
Figure 18.4 Example of Average Transfer Rate Setting when TMR Clock Is Input
SCK5 Base clock = 4 MHz 3/4 = 3 MHz (Average)
Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.3.12 IrDA Control Register (IrCR) IrCR selects the function of SCI_5.
Bit Bit Name Initial Value R/W 7 IrE 0 R/W 6 IrCKS2 0 R/W 5 IrCKS1 0 R/W 4 IrCKS0 0 R/W 3 IrTxINV 0 R/W 2 IrRxINV 0 R/W 1 0 0 0
Bit 7
Bit Name IrE
Initial Value 0
R/W R/W
Description IrDA Enable* Sets the SCI_5 I/O to normal SCI or IrDA. 0: TxD5/IrTxD and RxD5/IrRxD pins operate as TxD5 and RxD5. 1: TxD5/IrTxD and RxD5/IrRxD pins are operate as IrTxD and IrRxD.
6 5 4
IrCK2 IrCK1 IrCK0
0 0 0
R/W R/W R/W
IrDA Clock Select 2 to 0 Sets the pulse width of high state at encoding the IrTxD output pulse when the IrDA function is enabled. 000: Pulse-width = B x 3/16 (Bit rate x 3/16) 001: Pulse-width = P/2 010: Pulse-width = P/4 011: Pulse-width = P/8 100: Pulse-width = P/16 101: Pulse-width = P/32 110: Pulse-width = P/64 111: Pulse-width = P/128
3
IrTxINV
0
R/W
IrTx Data Invert This bit specifies the inversion of the logic level in IrTxD output. When inversion is done, the pulse width of high state specified by the bits 6 to 4 becomes the pulse width in low state. 0: Outputs the transmission data as it is as IrTxD output 1: Outputs the inverted transmission data as IrTxD output
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 2
Bit Name IrRxINV
Initial Value 0
R/W R/W
Description IrRx Data Invert This bit specifies the inversion of the logic level in IrRxD output. When inversion is done, the pulse width of high state specified by the bits 6 to 4 becomes the pulse width in low state. 0: Uses the IrRxD input data as it is as receive data. 1: Uses the inverted IrRxD input data as receive data.
1, 0
All 0
--
Reserved These bits are always read as 0. It should not be set to 0.
Note:
*
The IrDA function should be used when the ABCS bit in SEMR_5 is set to 0 and the ACS3 to ACS0 bits in SEMR_5 are set to B'0000.
18.4
Operation in Asynchronous Mode
Figure 18.5 shows the general format for asynchronous serial communication. One frame consists of a start bit (low level), transmit/receive data, a parity bit, and stop bits (high level). In asynchronous serial communication, the communication line is usually held in the mark state (high level). The SCI monitors the communication line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transmission and reception.
Idle state (mark state) 1 0/1 Parity bit 1 bit, or none 1 1
1 Serial data 0 Start bit 1 bit
LSB D0 D1 D2 D3 D4 D5 D6
MSB D7
Stop bit
Transmit/receive data 7 or 8 bits
1 or 2 bits
One unit of transfer data (character or frame)
Figure 18.5 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.4.1
Data Transfer Format
Table 18.11 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. For details on the multiprocessor bit, see section 18.5, Multiprocessor Communication Function. Table 18.11 Serial Transfer Formats (Asynchronous Mode)
SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 - - - - MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1
S
2
Serial Transfer Format and Frame Length 3 4 5 6 7 8 9 10 11
8-bit data STOP
12
S
8-bit data
STOP STOP
S
8-bit data
P
STOP
S
8-bit data
P
STOP STOP
S
7-bit data
STOP
S
7-bit data
STOP STOP
S
7-bit data
P
STOP
S
7-bit data
P
STOP STOP
S
8-bit data
MPB STOP
S
8-bit data
MPB STOP STOP
S
7-bit data
MPB STOP
S
7-bit data
MPB STOP STOP
[Legend] S: Start bit STOP: Stop bit P: Parity bit MPB: Multiprocessor bit
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times* the bit rate. In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization. Since receive data is sampled at the rising edge of the 8th pulse* of the base clock, data is latched at the middle of each bit, as shown in figure 18.6. Thus the reception margin in asynchronous mode is determined by formula (1) below.
M = | (0.5 - 1 ) - (L - 0.5) F - | D - 0.5 | (1 + F ) | x 100 2N N [%] ... Formula (1)
[Legend] M: Reception margin N: Ratio of bit rate to clock (When ABCS = 0, N = 16. When ABCS = 1, N = 8.) D: Duty cycle of clock (D = 0.5 to 1.0) L: Frame length (L = 9 to 12) F: Absolute value of clock frequency deviation
Assuming values of F = 0 and D = 0.5 in formula (1), the reception margin is determined by the formula below.
M = ( 0.5 -
1 ) x 100 2 x 16
[%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
16 clocks 8 clocks 0 Internal basic clock Receive data (RxD) Synchronization sampling timing Data sampling timing 7 15 0 7 15 0
Start bit
D0
D1
Figure 18.6 Receive Data Sampling Timing in Asynchronous Mode Note: * This is an example when the ABCS bit in SEMR_2, 5, and 6 is 0. When the ABCS bit is 1, a frequency of 8 times the bit rate is used as a base clock and receive data is sampled at the rising edge of the 4th pulse of the base clock.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.4.3
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCK pin can be selected as the SCI's transfer clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input to the SCK pin, the clock frequency should be 16 times the bit rate (when ABCS = 0) and 8 times the bit rate (when ABCS = 1). In addition, when an external clock is specified, the average transfer rate or the base clock of TMR_4 to TMR_7 can be selected by the ACS3 to ACS0 bits in SEMR_5 and SEMR_6. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 18.7.
SCK TxD 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 frame
Figure 18.7 Phase Relation between Output Clock and Transmit Data (Asynchronous Mode)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.4.4
SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 18.8 When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or RDR. When the external clock is used in asynchronous mode, the clock must be supplied even during initialization.
Start initialization [1] Clear TE and RE bits in SCR to 0 Set corresponding bit in ICR to 1 [1] [2] Set the bit in ICR for the corresponding pin when receiving data or using an external clock. Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock output is selected in asynchronous mode, the clock is output immediately after SCR settings are made. [3] [4] Set the data transfer format in SMR and SCMR. Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0)
[2]
Set data transfer format in SMR and SCMR Set value in BRR Wait
[3]
[4]
[5] No 1-bit interval elapsed Yes Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits
[5]

Figure 18.8 Sample SCI Initialization Flowchart
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.4.5
Serial Data Transmission (Asynchronous Mode)
Figure 18.9 shows an example of the operation for transmission in asynchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is cleared to 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt processing routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or multiprocessor bit (may be omitted depending on the format), and stop bit. 4. The SCI checks the TDRE flag at the timing for sending the stop bit. 5. If the TDRE flag is 0, the next transmit data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. 6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. Figure 18.10 shows a sample flowchart for transmission in asynchronous mode.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1
1
1 Idle state (mark state)
TDRE TEND TXI interrupt Data written to TDR and request generated TDRE flag cleared to 0 in TXI interrupt processing routine 1 frame TXI interrupt request generated
TEI interrupt request generated
Figure 18.9 Example of Operation for Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Initialization Start transmission
[1]
Read TDRE flag in SSR No
[2]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a 1 is output for a frame, and transmission is enabled. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC or DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0.
TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
All data transmitted? Yes
No
[3] Read TEND flag in SSR No
TEND = 1 Yes Break output Yes Clear DR to 0 and set DDR to 1
No
[4]
Clear TE bit in SCR to 0
Figure 18.10 Example of Serial Transmission Flowchart
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.4.6
Serial Data Reception (Asynchronous Mode)
Figure 18.11 shows an example of the operation for reception in asynchronous mode. In serial reception, the SCI operates as described below. 1. The SCI monitors the communication line, and if a start bit is detected, performs internal synchronization, stores receive data in RSR, and checks the parity bit and stop bit. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. 5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled.
Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0
1
1 Idle state (mark state)
RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine
ERI interrupt request generated by framing error
1 frame
Figure 18.11 Example of SCI Operation for Reception (Example with 8-Bit Data, Parity, One Stop Bit)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Table 18.12 shows the states of the SSR status flags and receive data handling when a receive error is detected. If a receive error is detected, the RDRF flag retains its state before receiving data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 18.12 shows a sample flowchart for serial data reception. Table 18.12 SSR Status Flags and Receive Data Handling
SSR Status Flag RDRF* 1 0 0 1 1 0 1 Note: * ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 Receive Data Lost Transferred to RDR Transferred to RDR Lost Lost Transferred to RDR Lost Receive Error Type Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error
The RDRF flag retains the state it had before data reception.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
[2] [3] Receive error processing and break detection: [2] If a receive error occurs, read the ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure Yes PER FER ORER = 1 that the ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot be No resumed if any of these flags are set to Error processing 1. In the case of a framing error, a (Continued on next page) break can be detected by reading the value of the input port corresponding to [4] Read RDRF flag in SSR the RxD pin. Read ORER, PER, and FER flags in SSR No [4] SCI state check and receive data read: Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag and RDR, and clear the RDRF flag to 0. However, the RDRF flag is cleared automatically when the DMAC or DTC is initiated by an RXI interrupt and reads data from RDR.
RDRF = 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0
No
All data received? Yes Clear RE bit in SCR to 0
[5]
Figure 18.12 Sample Serial Reception Flowchart (1)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
[3] Error processing
No
ORER = 1 Yes Overrun error processing
No
FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes
No
PER = 1 Yes Parity error processing
Clear ORER, PER, and FER flags in SSR to 0

Figure 18.12 Sample Serial Reception Flowchart (2)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a number of processors sharing communication lines by means of asynchronous serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station, and a data transmission cycle for the specified receiving station. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle. Figure 18.13 shows an example of inter-processor communication using the multiprocessor format. The transmitting station first sends data which includes the ID code of the receiving station and a multiprocessor bit set to 1. It then transmits transmit data added with a multiprocessor bit cleared to 0. The receiving station skips data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again received. The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1, transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags, RDRF, FER, and ORER in SSR to 1 are prohibited until data with a 1 multiprocessor bit is received. On reception of a receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt is generated. When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings are the same as those in normal asynchronous mode. The clock used for multiprocessor communication is the same as that in normal asynchronous mode.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Transmitting station Communication line
Receiving station A (ID = 01) Serial data
Receiving station B (ID = 02)
Receiving station C (ID = 03)
Receiving station D (ID = 04)
H'01 (MPB = 1)
H'AA (MPB = 0)
ID transmission cycle = Data transmission cycle = receiving station Data transmission to specification receiving station specified by ID [Legend] MPB: Multiprocessor bit
Figure 18.13 Example of Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.5.1
Multiprocessor Serial Data Transmission
Figure 18.14 shows a sample flowchart for multiprocessor serial data transmission. For an ID transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same as those in asynchronous mode.
Initialization Start transmission Read TDRE flag in SSR No
[1]
[2]
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a 1 is output for one frame, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC or DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port to 1, clear DR to 0, and then clear the TE bit in SCR to 0.
TDRE = 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0
All data transmitted? Yes Read TEND flag in SSR
No
[3]
TEND = 1 Yes Break output? Yes Clear DR to 0 and set DDR to 1
No
No
[4]
Clear TE bit in SCR to 0

Figure 18.14 Sample Multiprocessor Serial Transmission Flowchart
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.5.2
Multiprocessor Serial Data Reception
Figure 18.16 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure 18.15 shows an example of SCI operation for multiprocessor format reception.
Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data 1) D1 D7 Stop MPB bit 0
1
1
1 Idle state (mark state)
MPIE RDRF
RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine
ID1 If not this station's ID, MPIE bit is set to 1 again RXI interrupt request is not generated, and RDR retains its state
(a) Data does not match station's ID
1
Start bit 0 D0 D1
Data (ID2) D7
Stop MPB bit 1 1
Start bit 0 D0
Data (Data 2) D1 D7
Stop MPB bit 0
1
1 Idle state (mark state)
MPIE RDRF
RDR value
ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine
ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt processing routine
Data 2 MPIE bit set to 1 again
(b) Data matches station's ID
Figure 18.15 Example of SCI Operation for Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Initialization Start reception Set MPIE bit in SCR to 1 Read ORER and FER flags in SSR FER ORER = 1 No Read RDRF flag in SSR No
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI state check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI state check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. [4]
[2]
Yes
[3]
RDRF = 1 Yes Read receive data in RDR
No
This station's ID? Yes Read ORER and FER flags in SSR FER ORER = 1 No Read RDRF flag in SSR No Yes
RDRF = 1 Yes Read receive data in RDR No
All data received? Yes Clear RE bit in SCR to 0
[5] Error processing (Continued on next page)
Figure 18.16 Sample Multiprocessor Serial Reception Flowchart (1)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
[5]
Error processing
No
ORER = 1 Yes Overrun error processing
No
FER = 1 Yes Break? No Framing error processing Clear RE bit in SCR to 0 Yes
Clear ORER, PER, and FER flags in SSR to 0

Figure 18.16 Sample Multiprocessor Serial Reception Flowchart (2)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.6
Operation in Clocked Synchronous Mode (SCI_0, 1, 2, and 4 only)
Figure 18.17 shows the general format for clocked synchronous communication. In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses. One character in transfer data consists of 8-bit data. In data transmission, the SCI outputs data from one falling edge of the synchronization clock to the next. In data reception, the SCI receives data in synchronization with the rising edge of the synchronization clock. After 8-bit data is output, the transmission line holds the MSB output state. In clocked synchronous mode, no parity bit or multiprocessor bit is added. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that the next transmit data can be written during transmission or the previous receive data can be read during reception, enabling continuous data transfer. (Setting is prohibited in SCI_5 and SCI_6.)
One unit of transfer data (character or frame) * Synchronization clock LSB Serial data Don't care Note: * Holds a high level except during continuous transfer. Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care *
Figure 18.17 Data Format in Clocked Synchronous Communication (LSB-First) 18.6.1 Clock
Either an internal clock generated by the on-chip baud rate generator or an external synchronization clock input at the SCK pin can be selected, according to the setting of the CKE1 and CKE0 bits in SCR. When the SCI is operated on an internal clock, the synchronization clock is output from the SCK pin. Eight synchronization clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. Note that in the case of reception only, the synchronization clock is output until an overrun error occurs or until the RE bit is cleared to 0. (Setting is prohibited in SCI_5 and SCI_6.)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.6.2
SCI Initialization (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)
Before transmitting and receiving data, first clear the TE and RE bits in SCR to 0, then initialize the SCI as described in a sample flowchart in figure 18.18. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is cleared to 0, the TDRE flag is set to 1. However, clearing the RE bit to 0 does not initialize the RDRF, PER, FER, and ORER flags, or RDR.
Start initialization [1] Clear TE and RE bits in SCR to 0 Set corresponding bit in ICR to 1 [1] Set the bit in ICR for the corresponding pin when receiving data or using an external clock.
Set CKE1 and CKE0 bits in SCR (TE and RE bits are 0)
[2] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. [3] Set the data transfer format in SMR and SCMR. [4] Write a value corresponding to the bit rate to BRR. This step is not necessary if an external clock is used. [5] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used.
[2]
Set data transfer format in SMR and SCMR Set value in BRR Wait
[3]
[4]
1-bit interval elapsed? Yes
No
Set TE or RE bit in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits
[5]
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared to 0 or set to 1 simultaneously.
Figure 18.18 Sample SCI Initialization Flowchart
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.6.3
Serial Data Transmission (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)
Figure 18.19 shows an example of the operation for transmission in clocked synchronous mode. In transmission, the SCI operates as described below. 1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. 2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated. Because the TXI interrupt processing routine writes the next transmit data to TDR before transmission of the current transmit data has finished, continuous transmission can be enabled. 3. 8-bit data is sent from the TxD pin synchronized with the output clock when clock output mode has been specified and synchronized with the input clock when use of an external clock has been specified. 4. The SCI checks the TDRE flag at the timing for sending the last bit. 5. If the TDRE flag is cleared to 0, the next transmit data is transferred from TDR to TSR, and serial transmission of the next frame is started. 6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin retains the output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. The SCK pin is fixed high. Figure 18.20 shows a sample flowchart for serial data transmission. Even if the TDRE flag is cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1. Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the RE bit to 0 does not clear the receive error flags.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Transfer direction Synchronization clock Serial data TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt processing routine 1 frame TXI interrupt request generated TEI interrupt request generated Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 18.19 Example of Operation for Transmission in Clocked Synchronous Mode
[1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. However, the TDRE flag is checked and cleared automatically when the DMAC or DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR.
Initialization Start transmission
[1]
Read TDRE flag in SSR No
[2]
TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
All data transmitted Yes Read TEND flag in SSR
No
[3]
TEND = 1 Yes Clear TE bit in SCR to 0
No
Figure 18.20 Sample Serial Transmission Flowchart
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.6.4
Serial Data Reception (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)
Figure 18.21 shows an example of SCI operation for reception in clocked synchronous mode. In serial reception, the SCI operates as described below. 1. The SCI performs internal initialization in synchronization with a synchronization clock input or output, starts receiving data, and stores the receive data in RSR. 2. If an overrun error (when reception of the next data is completed while the RDRF flag in SSR is still set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag remains to be set to 1. 3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is generated. Because the RXI interrupt processing routine reads the receive data transferred to RDR before reception of the next receive data has finished, continuous reception can be enabled.
Synchronization clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt processing routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 18.21 Example of Operation for Reception in Clocked Synchronous Mode Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 18.22 shows a sample flowchart for serial data reception.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Initialization Start reception
[1]
[1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1.
Read ORER flag in SSR Yes
[2]
ORER = 1 No
[3]
Error processing
No
(Continued below) [4] SCI state check and receive data read: Read RDRF flag in SSR [4] Read SSR and check that the RDRF flag is set to 1, then read the receive RDRF = 1 data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from Yes 0 to 1 can also be identified by an RXI interrupt. Read receive data in RDR and clear RDRF flag in SSR to 0 [5] Serial reception continuation All data received Yes Clear RE bit in SCR to 0 [5] procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0 should be finished. However, the RDRF flag is cleared automatically when the DMAC or DTC is initiated by a receive data full interrupt (RXI) and reads data from RDR.
No
[3]
Error processing Overrun error processing Clear ORER flag in SSR to 0
Figure 18.22 Sample Serial Reception Flowchart 18.6.5 Simultaneous Serial Data Transmission and Reception (Clocked Synchronous Mode) (SCI_0, 1, 2, and 4 only)
Figure 18.23 shows a sample flowchart for simultaneous serial transmit and receive operations. After initializing the SCI, the following procedure should be used for simultaneous serial data transmit and receive operations. To switch from transmit mode to simultaneous transmit and receive mode, after checking that the SCI has finished transmission and the TDRE and TEND flags are set to 1, clear the TE bit to 0. Then simultaneously set both the TE and RE bits to 1 with a single instruction. To switch from receive mode to simultaneous transmit and receive mode, after checking that the SCI has finished reception, clear the RE bit to 0. Then after checking that the RDRF bit and receive error flags (ORER, FER, and PER) are cleared to 0, simultaneously set both the TE and RE bits to 1 with a single instruction.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Initialization Start transmission/reception
[1]
Read TDRE flag in SSR No
[2]
[1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. [2] SCI state check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error processing, clear the ORER flag to 0. Reception cannot be resumed if the ORER flag is set to 1. [4] SCI state check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt.
TDRE = 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0
Read ORER flag in SSR Yes [3] Error processing [4]
ORER = 1 No Read RDRF flag in SSR No
RDRF = 1 Yes
[5] Serial transmission/reception continuation procedure: To continue serial transmission/ Read receive data in RDR, and reception, before the MSB (bit 7) of clear RDRF flag in SSR to 0 the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to No 0. Also, before the MSB (bit 7) of All data received? [5] the current frame is transmitted, read 1 from the TDRE flag to Yes confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Clear TE and RE bits in SCR to 0 However, the TDRE flag is checked and cleared automatically when the DMAC or DTC is initiated by a transmit data empty interrupt (TXI) request and writes data to TDR. Similarly, the RDRF flag is cleared Note: When switching from transmit or receive operation to automatically when the DMAC or simultaneous transmit and receive operations, first clear DTC is initiated by a receive data the TE bit and RE bit to 0, then set both these bits to 1 full interrupt (RXI) and reads data simultaneously. from RDR.
Figure 18.23 Sample Flowchart of Simultaneous Serial Transmission and Reception
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.7
Operation in Smart Card Interface Mode
The SCI supports the smart card interface, supporting the ISO/IEC 7816-3 (Identification Card) standard, as an extended serial communication interface function. Smart card interface mode can be selected using the appropriate register. 18.7.1 Sample Connection
Figure 18.24 shows a sample connection between the smart card and this LSI. As in the figure, since this LSI communicates with the smart card using a single transmission line, interconnect the TxD and RxD pins and pull up the data transmission line to VCC using a resistor. Setting the RE and TE bits to 1 with the smart card not connected enables closed transmission/reception allowing self diagnosis. To supply the smart card with the clock pulses generated by the SCI, input the SCK pin output to the CLK pin of the smart card. A reset signal can be supplied via the output port of this LSI. (In SCI_5 and SCI-6, the clock generated in SCI cannot be provided to smart cards.)
VCC TxD RxD SCK Rx (port) This LSI Main unit of the device to be connected Data line Clock line Reset line I/O CLK RST IC card
Figure 18.24 Pin Connection for Smart Card Interface
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.7.2
Data Format (Except in Block Transfer Mode)
Figure 18.25 shows the data transfer formats in smart card interface mode. * One frame contains 8-bit data and a parity bit in asynchronous mode. * During transmission, at least 2 etu (elementary time unit: time required for transferring one bit) is secured as a guard time after the end of the parity bit before the start of the next frame. * If a parity error is detected during reception, a low error signal is output for 1 etu after 10.5 etu has passed from the start bit. * If an error signal is sampled during transmission, the same data is automatically re-transmitted after at least 2 etu.
In normal transmission/reception
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
Output from the transmitting station
When a parity error is generated
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE
Output from the transmitting station Output from the receiving station Start bit Data bits Parity bit Error signal
[Legend] Ds: D0 to D7: Dp: DE:
Figure 18.25 Data Formats in Normal Smart Card Interface Mode For communication with the smart cards of the direct convention and inverse convention types, follow the procedure below.
(Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) state
Figure 18.26 Direct Convention (SDIR = SINV = O/E = 0)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
For the direct convention type, logic levels 1 and 0 correspond to states Z and A, respectively, and data is transferred with LSB-first as the start character, as shown in figure 18.26. Therefore, data in the start character in the figure is H'3B. When using the direct convention type, write 0 to both the SDIR and SINV bits in SCMR. Write 0 to the O/E bit in SMR in order to use even parity, which is prescribed by the smart card standard.
(Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) state
Figure 18.27 Inverse Convention (SDIR = SINV = O/E = 1) For the inverse convention type, logic levels 1 and 0 correspond to states A and Z, respectively and data is transferred with MSB-first as the start character, as shown in figure 18.27. Therefore, data in the start character in the figure is H'3F. When using the inverse convention type, write 1 to both the SDIR and SINV bits in SCMR. The parity bit is logic level 0 to produce even parity, which is prescribed by the smart card standard, and corresponds to state Z. Since the SNIV bit of this LSI only inverts data bits D7 to D0, write 1 to the O/E bit in SMR to invert the parity bit in both transmission and reception. 18.7.3 Block Transfer Mode
Block transfer mode is different from normal smart card interface mode in the following respects. * Even if a parity error is detected during reception, no error signal is output. Since the PER bit in SSR is set by error detection, clear the PER bit before receiving the parity bit of the next frame. * During transmission, at least 1 etu is secured as a guard time after the end of the parity bit before the start of the next frame. * Since the same data is not re-transmitted during transmission, the TEND flag is set 11.5 etu after transmission start. * Although the ERS flag in block transfer mode displays the error signal status as in normal smart card interface mode, the flag is always read as 0 because no error signal is transferred.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.7.4
Receive Data Sampling Timing and Reception Margin
Only the internal clock generated by the on-chip baud rate generator can be used as a transfer clock in smart card interface mode. In this mode, the SCI can operate on a base clock with a frequency of 32, 64, 372, or 256 times the bit rate according to the BCP1 and BCP0 bit settings (the frequency is always 16 times the bit rate in normal asynchronous mode). At reception, the falling edge of the start bit is sampled using the base clock in order to perform internal synchronization. Receive data is sampled on the 16th, 32nd, 186th and 128th rising edges of the base clock so that it can be latched at the middle of each bit as shown in figure 18.28. The reception margin here is determined by the following formula.
M = | (0.5 -
[Legend]
1 ) - (L - 0.5) F - | D - 0.5 | (1 + F ) | x 100% 2N N
M: Reception margin (%) N: Ratio of bit rate to clock (N = 32, 64, 372, 256) D: Duty cycle of clock (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5, and N = 372 in the above formula, the reception margin is determined by the formula below.
M= ( 0.5 -
1 ) x 100% = 49.866% 2 x 372
372 clock cycles 186 clock cycles 0 Internal basic clock Receive data (RxD) Synchronization sampling timing 185 371 0 185 371 0
Start bit
D0
D1
Data sampling timing
Figure 18.28 Receive Data Sampling Timing in Smart Card Interface Mode (When Clock Frequency is 372 Times the Bit Rate)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.7.5
Initialization
Before transmitting and receiving data, initialize the SCI using the following procedure. Initialization is also necessary before switching from transmission to reception and vice versa. 1. 2. 3. 4. 5. Clear the TE and RE bits in SCR to 0. Set the ICR bit of the corresponding pin to 1. Clear the error flags ERS, PER, and ORER in SSR to 0. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR appropriately. Also set the PE bit to 1. Set the SMIF, SDIR, and SINV bits in SCMR appropriately. When the DDR corresponding to the TxD pin is cleared to 0, the TxD and RxD pins are changed from port pins to SCI pins, placing the pins into high impedance state. Set the value corresponding to the bit rate in BRR. Set the CKE1 and CKE0 bits in SCR appropriately. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0 simultaneously. When the CKE0 bit is set to 1, the SCK pin is allowed to output clock pulses. Set the TIE, RIE, TE, and RE bits in SCR appropriately after waiting for at least a 1-bit interval. Setting the TE and RE bits to 1 simultaneously is prohibited except for self diagnosis.
6. 7.
8.
To switch from reception to transmission, first verify that reception has completed, then initialize the SCI. At the end of initialization, RE and TE should be set to 0 and 1, respectively. Reception completion can be verified by reading the RDRF, PER, or ORER flag. To switch from transmission to reception, first verify that transmission has completed, then initialize the SCI. At the end of initialization, TE and RE should be set to 0 and 1, respectively. Transmission completion can be verified by reading the TEND flag.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.7.6
Data Transmission (Except in Block Transfer Mode)
Data transmission in smart card interface mode (except in block transfer mode) is different from that in normal serial communication interface mode in that an error signal is sampled and data can be re-transmitted. Figure 18.29 shows the data re-transfer operation during transmission. 1. If an error signal from the receiving end is sampled after one frame of data has been transmitted, the ERS bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the ERS bit to 0 before the next parity bit is sampled. 2. For the frame in which an error signal is received, the TEND bit in SSR is not set to 1. Data is re-transferred from TDR to TSR allowing automatic data retransmission. 3. If no error signal is returned from the receiving end, the ERS bit in SSR is not set to 1. 4. In this case, one frame of data is determined to have been transmitted including re-transfer, and the TEND bit in SSR is set to 1. Here, a TXI interrupt request is generated if the TIE bit in SCR is set to 1. Writing transmit data to TDR starts transmission of the next data. Figure 18.31 shows a sample flowchart for transmission. All the processing steps are automatically performed using a TXI interrupt request to activate the DTC or DMAC. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt request if the TIE bit in SCR has been set to 1. This activates the DTC or DMAC by a TXI request thus allowing transfer of transmit data if the TXI interrupt request is specified as a source of DTC or DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs, the SCI automatically retransmits the same data. During re-transmission, TEND remains as 0, thus not activating the DTC or DMAC. Therefore, the SCI and DTC or DMAC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DTC or DMAC, be sure to set and enable the DTC or DMAC prior to making SCI settings. For DTC or DMAC settings, see section 12, Data Transfer Controller (DTC) and section 10, DMA Controller (DMAC).
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Retransfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE)
(n + 1) th transfer frame
Ds D0 D1 D2 D3 D4
TDRE
Transfer from TDR to TSR
TEND
[2]
Transfer from TDR to TSR
Transfer from TDR to TSR
[4]
FER/ERS
[1] [3]
Figure 18.29 Data Re-Transfer Operation in SCI Transmission Mode Note that the TEND flag is set in different timings depending on the GM bit setting in SMR. Figure 18.30 shows the TEND flag set timing.
I/O data TXI (TEND interrupt)
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE
Guard time
12.5 etu
GM = 0
11.0 etu
GM = 1
[Legend] Ds: D0 to D7: Dp: DE:
Start bit Data bits Parity bit Error signal
Figure 18.30 TEND Flag Set Timing during Transmission
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Start Initialization Start transmission
ERS = 0? Yes
No
Error processing
No
TEND = 1? Yes
Write data to TDR and clear TDRE flag in SSR to 0
No
All data transmitted?
Yes No ERS = 0? Yes
Error processing
No TEND = 1? Yes
Clear TE bit in SCR to 0 End
Figure 18.31 Sample Transmission Flowchart
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.7.7
Serial Data Reception (Except in Block Transfer Mode)
Data reception in smart card interface mode is similar to that in normal serial communication interface mode. Figure 18.32 shows the data re-transfer operation during reception. 1. If a parity error is detected in receive data, the PER bit in SSR is set to 1. Here, an ERI interrupt request is generated if the RIE bit in SCR is set to 1. Clear the PER bit to 0 before the next parity bit is sampled. 2. For the frame in which a parity error is detected, the RDRF bit in SSR is not set to 1. 3. If no parity error is detected, the PER bit in SSR is not set to 1. 4. In this case, data is determined to have been received successfully, and the RDRF bit in SSR is set to 1. Here, an RXI interrupt request is generated if the RIE bit in SCR is set to 1. Figure 18.33 shows a sample flowchart for reception. All the processing steps are automatically performed using an RXI interrupt request to activate the DTC or DMAC. In reception, setting the RIE bit to 1 allows an RXI interrupt request to be generated when the RDRF flag is set to 1. This activates the DTC or DMAC by an RXI request thus allowing transfer of receive data if the RXI interrupt request is specified as a source of DTC or DMAC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs during reception, i.e., either the ORER or PER flag is set to 1, a transmit/receive error interrupt (ERI) request is generated and the error flag must be cleared. If an error occurs, the DTC or DMAC is not activated and receive data is skipped, therefore, the number of bytes of receive data specified in the DTC or DMAC is transferred. Even if a parity error occurs and the PER bit is set to 1 in reception, receive data is transferred to RDR, thus allowing the data to be read. Note: For operations in block transfer mode, see section 18.4, Operation in Asynchronous Mode.
(n + 1) th transfer frame (DE) Ds D0 D1 D2 D3 D4
nth transfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1]
Retransfer frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
[4]
[3]
Figure 18.32 Data Re-Transfer Operation in SCI Reception Mode
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Start Initialization Start reception
ORER = 0 and PER = 0?
No
Yes No
Error processing
RDRF = 1? Yes
Read data from RDR and clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
Figure 18.33 Sample Reception Flowchart 18.7.8 Clock Output Control (Only SCI_0, 1, 2, and 4)
Clock output can be fixed using the CKE1 and CKE0 bits in SCR when the GM bit in SMR is set to 1. Specifically, the minimum width of a clock pulse can be specified. Figure 18.34 shows an example of clock output fixing timing when the CKE0 bit is controlled with GM = 1 and CKE1 = 0.
CKE0
SCK
Given pulse width
Given pulse width
Figure 18.34 Clock Output Fixing Timing
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
At power-on and transitions to/from software standby mode, use the following procedure to secure the appropriate clock duty cycle. * At power-on To secure the appropriate clock duty cycle simultaneously with power-on, use the following procedure. 1. Initially, port input is enabled in the high-impedance state. To fix the potential level, use a pull-up or pull-down resistor. 2. Fix the SCK pin to the specified output using the CKE1 bit in SCR. 3. Set SMR and SCMR to enable smart card interface mode. Set the CKE0 bit in SCR to 1 to start clock output. * At mode switching At transition from smart card interface mode to software standby mode 1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the values for the output fixed state in software standby mode. (SCI_0, 1, 2, and 4 only) 2. Write 0 to the TE and RE bits in SCR to stop transmission/reception. Simultaneously, set the CKE1 bit to the value for the output fixed state in software standby mode. 3. Write 0 to the CKE0 bit in SCR to stop the clock. 4. Wait for one cycle of the serial clock. In the mean time, the clock output is fixed to the specified level with the duty cycle retained. 5. Make the transition to software standby mode. At transition from smart card interface mode to software standby mode 1. Clear software standby mode. 2. Write 1 to the CKE0 bit in SCR to start clock output. A clock signal with the appropriate duty cycle is then generated.
Software standby
Normal operation
Normal operation
[1] [2] [3]
[4] [5]
[6]
[7]
Figure 18.35 Clock Stop and Restart Procedure
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.8
IrDA Operation
If the IrDA function is enabled using the IrE bit in IrCR, the TxD5 and RxD5 pins in SCI_5 are allowed to encode and decode the waveform based on the IrDA Specifications version 1.0 (function as the IrTxD and IrRxD pins)*. Connecting these pins to the infrared data transceiver achieves infrared data communication based on the system defined by the IrDA Specifications version 1.0. In the system defined by the IrDA Specifications version 1.0, communication is started at a transfer rate of 9600 bps, which can be modified later as required. Since the IrDA interface provided by this LSI does not incorporate the capability of automatic modification of the transfer rate, the transfer rate must be modified through programming. Figure 18.36 is the IrDA block diagram.
IrDA SCI5
TxD5/IrTxD
Pulse encoder
TxD
RxD RxD5/IrRxD Pulse decoder
IrCR
Figure 18.36 IrDA Block Diagram Note: * The IrDA function should be used when the ABCS bit in SEMR_5 is set to 0 and the ACS3 to ACS0 bits in SEMR_5 are set to B'0000.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
(1)
Transmission
During transmission, the output signals from the SCI (UART frames) are converted to IR frames using the IrDA interface (see figure 18.37). For serial data of level 0, a high-level pulse having a width of 3/16 of the bit rate (1-bit interval) is output (initial setting). The high-level pulse can be selected using the IrCKS2 to IrCKS0 bits in IrCR. The high-level pulse width is defined to be 1.41 s at minimum and (3/16 + 2.5%) x bit rate or (3/16 x bit rate) +1.08 s at maximum. For example, when the frequency of system clock is 20 MHz, a high-level pulse width of 1.6 s can be specified because it is the smallest value in the range greater than 1.41 s. For serial data of level 1, no pulses are output.
UART frame Start bit 0 1 0 1 0 Data Stop bit 1 1 0 1
0
Transmission IR frame Start bit 0 1 0 1 0 Data
Reception
Stop bit 1 1 0 1
0
Bit cycle
Pulse width is 1.6 s to 3/16 bit cycle
Figure 18.37 IrDA Transmission and Reception (2) Reception
During reception, IR frames are converted to UART frames using the IrDA interface before inputting to SCI. 0 is output when the high level pulse is detected while 1 is output when no pulse is detected during one bit period. Note that a pulse shorter than the minimum pulse width of 1.41 s is also regarded as a 0 signal.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
(3)
High-Level Pulse Width Selection
Table 18.13 shows possible settings for bits IrCKS2 to IrCKS0 (minimum pulse width), and this LSI's operating frequencies and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission. Table 18.13 IrCKS2 to IrCKS0 Bit Settings
Operating Frequency P (MHz) 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 25 30 33 35 2400 78.13 100 100 100 100 101 101 101 101 101 101 101 101 101 110 110 110 110 Bit Rate (bps) (Upper Row)/Bit Interval x 3/16 (s) (Lower Row) 9600 19.53 100 100 100 100 101 101 101 101 101 101 101 101 101 110 110 110 110 19200 9.77 100 100 100 100 101 101 101 101 101 101 101 101 101 110 110 110 110 38400 4.88 100 100 100 100 101 101 101 101 101 101 101 101 101 110 110 110 110 57600 3.26 100 100 100 100 101 101 101 101 101 101 101 101 101 110 110 110 110 115200 1.63 100 100 100 100 101 101 101 101 101 101 101 101 101 110 110 110 110
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.9
18.9.1
Interrupt Sources
Interrupts in Normal Serial Communication Interface Mode
Table 18.14 shows the interrupt sources in normal serial communication interface mode. A different interrupt vector is assigned to each interrupt source, and individual interrupt sources can be enabled or disabled using the enable bits in SCR. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt request can activate the DTC or DMAC to allow data transfer. The TDRE flag is automatically cleared to 0 at data transfer by the DTC or DMAC. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DTC or DMAC to allow data transfer. The RDRF flag is automatically cleared to 0 at data transfer by the DTC or DMAC. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt has priority for acceptance. However, note that if the TDRE and TEND flags are cleared to 0 simultaneously by the TXI interrupt processing routine, the SCI cannot branch to the TEI interrupt processing routine later. Note that the priority order for interrupts is different between the group of SCI_0, 1, 2, and 4 and the group of SCI_5 and SCI_6. Table 18.14 SCI Interrupt Sources (SCI_0, 1, 2, and 4)
Name ERI RXI TXI TEI Interrupt Source Receive error Receive data full Interrupt Flag ORER, FER, or PER RDRF DTC Activation Not possible Possible Possible Not possible DMAC Activation Not possible Possible Possible Not possible Low Priority High
Transmit data empty TDRE Transmit end TEND
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Table 18.15 SCI Interrupt Sources (SCI_5 and SCI_6)
Name RXI TXI ERI TEI Interrupt Source Receive data full Interrupt Flag RDRF DTC Activation Not possible Not possible Not possible Not possible DMAC Activation Possible Possible Not possible Not possible Low Priority High
Transmit data empty TDRE Receive error Transmit end ORER, FER, or PER TEND
18.9.2
Interrupts in Smart Card Interface Mode
Table 18.16 shows the interrupt sources in smart card interface mode. A transmit end (TEI) interrupt request cannot be used in this mode. Note that the priority order for interrupts is different between the group of SCI_0, 1, 2, and 4 and the group of SCI_5 and SCI_6. Table 18.16 SCI Interrupt Sources (SCI_0, 1, 2, and 4)
Name ERI RXI TXI Interrupt Source Interrupt Flag DTC Activation Not possible Possible Possible DMAC Activation Not possible Possible Possible Low Priority High
Receive error or error ORER, PER, or ERS signal detection Receive data full Transmit data empty RDRF TEND
Table 18.17 SCI Interrupt Sources (SCI_5 and SCI_6)
Name RXI TXI ERI Interrupt Source Receive data full Transmit data empty Interrupt Flag RDRF TDRE DTC Activation Not possible Not possible Not possible DMAC Activation Possible Possible Not possible Low Priority High
Receive error or error ORER, PER, or ERS signal detection
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Data transmission/reception using the DTC or DMAC is also possible in smart card interface mode, similar to in the normal SCI mode. In transmission, the TEND and TDRE flags in SSR are simultaneously set to 1, thus generating a TXI interrupt. This activates the DTC or DMAC by a TXI request thus allowing transfer of transmit data if the TXI request is specified as a source of DTC or DMAC activation beforehand. The TDRE and TEND flags are automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs, the SCI automatically re-transmits the same data. During re-transmission, the TEND flag remains as 0, thus not activating the DTC or DMAC. Therefore, the SCI and DTC or DMAC automatically transmit the specified number of bytes, including re-transmission in the case of error occurrence. However, the ERS flag in SSR, which is set at error occurrence, is not automatically cleared; the ERS flag must be cleared by previously setting the RIE bit in SCR to 1 to enable an ERI interrupt request to be generated at error occurrence. When transmitting/receiving data using the DTC or DMAC, be sure to set and enable the DTC or DMAC prior to making SCI settings. For DTC or DMAC settings, see section 12, Data Transfer Controller (DTC) and section 10, DMA Controller (DMAC). In reception, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. This activates the DTC or DMAC by an RXI request thus allowing transfer of receive data if the RXI request is specified as a source of DTC or DMAC activation beforehand. The RDRF flag is automatically cleared to 0 at data transfer by the DTC or DMAC. If an error occurs, the RDRF flag is not set but the error flag is set. Therefore, the DTC or DMAC is not activated and an ERI interrupt request is issued to the CPU instead; the error flag must be cleared.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.10
Usage Notes
18.10.1 Module Stop Function Setting Operation of the SCI can be disabled or enabled using the module stop control register. The initial setting is for operation of the SCI to be halted. Register access is enabled by clearing the module stop state. For details, see section 27, Power-Down Modes. 18.10.2 Break Detection and Processing When framing error detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the PER flag may also be set. Note that, since the SCI continues the receive operation even after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. 18.10.3 Mark State and Break Detection When the TE bit is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send a break during serial data transmission. To maintain the communication line in mark state (the state of 1) until TE is set to 1, set both DDR and DR to 1. Since the TE bit is cleared to 0 at this point, the TxD pin becomes an I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set DDR to 1 and DR to 0, and then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. 18.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only) Transmission cannot be started when a receive error flag (ORER, FER, or RER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that the receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.10.5 Relation between Writing to TDR and TDRE Flag The TDRE flag in SSR is a status flag which indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR irrespective of the TDRE flag status. However, if new data is written to TDR when the TDRE flag is 0, that is, when the previous data has not been transferred to TSR yet, the previous data in TDR is lost. Be sure to write transmit data to TDR after verifying that the TDRE flag is set to 1. 18.10.6 Restrictions on Using DTC or DMAC * When the external clock source is used as a synchronization clock, update TDR by the DMAC or DTC and wait for at least five P clock cycles before allowing the transmit clock to be input. If the transmit clock is input within four clock cycles after TDR modification, the SCI may malfunction (see figure 18.38). * When using the DMAC or DTC to read RDR, be sure to set the receive end interrupt (RXI) as the DTC or DMAC activation source.
SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7
Note: When external clock is supplied, t must be more than four clock cycles.
Figure 18.38 Sample Transmission using DTC in Clocked Synchronous Mode * The DTC is not activated by the RXI or TXI request by SCI_5 or SCI6.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.10.7 SCI Operations during Power-Down State Transmission: Before specifying the module stop state or making a transition to software standby mode, stop the transmit operations (TE = TIE = TEIE = 0). TSR, TDR, and SSR are reset. The states of the output pins in the module stop state or in software standby mode depend on the port settings, and the pins output a high-level signal after cancellation. If the transition is made during data transmission, the data being transmitted will be undefined. To transmit data in the same transmission mode after cancellation of the power-down state, set the TE bit to 1, read SSR, write to TDR, clear TDRE in this order, and then start transmission. To transmit data in a different transmission mode, initialize the SCI first. For using the IrDA function, set the IrE bit in addition to setting the TE bit. Figure 18.39 shows a sample flowchart for transition to software standby mode during transmission. Figures 18.40 and 18.41 show the port pin states during transition to software standby mode. Before specifying the module stop state or making a transition to software standby mode from the transmission mode using DTC transfer, stop all transmit operations (TE = TIE = TEIE = 0). Setting the TE and TIE bits to 1 after cancellation sets the TXI flag to start transmission using the DTC. Reception: Before specifying the module stop state or making a transition to software standby mode, stop the receive operations (RE = 0). RSR, RDR, and SSR are reset. If transition is made during data reception, the data being received will be invalid. To receive data in the same reception mode after cancellation of the power-down state, set the RE bit to 1, and then start reception. To receive data in a different reception mode, initialize the SCI first. For using the IrDA function, set the IrE bit in addition to setting the RE bit. Figure 18.42 shows a sample flowchart for mode transition during reception.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Transmission
All data transmitted? Yes Read TEND flag in SSR
No
[1]
TEND = 1 Yes TE = 0 [2]
No
[1] Data being transmitted is lost halfway. Data can be normally transmitted from the CPU by setting the TE bit to 1, reading SSR, writing to TDR, and clearing the TDRE bit to 0 after clearing software standby mode; however, if the DTC has been activated, the data remaining in the DTC will be transmitted when both the TE and TIE bits are set to 1. [2] Clear the TIE and TEIE bits to 0 when they are 1. [3] Setting of the module stop state is included.
Make transition to software standby mode Cancel software standby mode
[3]
Change operating mode? Yes Initialization
No
TE = 1
Start transmission
Figure 18.39 Sample Flowchart for Software Standby Mode Transition during Transmission
Transition to Software standby Transmission end software standby mode canceled mode
Transmission start
TE bit SCK* output pin TxD output pin
Port input/output Port input/output
High output
Start SCI TxD output
Stop
Port input/output Port
High output SCI TxD output
Port Note: * Not output in SCI_5, 6.
Figure 18.40 Port Pin States during Software Standby Mode Transition (Internal Clock, Asynchronous Transmission)
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Transmission start
Transmission end
Transition to Software standby software standby mode canceled mode
TE bit SCK output pin TxD output pin
Port input/output
Port input/output
Marking output SCI TxD output
Last TxD bit retained
Port input/output Port
High output* SCI TxD output
Port Note: * Initialized in software standby mode
Figure 18.41 Port Pin States during Software Standby Mode Transition (Internal Clock, Clocked Synchronous Transmission) (Setting is Prohibited in SCI_5 and SCI_6)
Reception
Read RDRF flag in SSR
RDRF = 1 Yes Read receive data in RDR
No
[1]
[1] Data being received will be invalid.
RE = 0 Make transition to software standby mode Cancel software standby mode [2] [2] Setting of the module stop state is included.
Change operating mode? Yes Initialization
No
RE = 1
Start reception
Figure 18.42 Sample Flowchart for Software Standby Mode Transition during Reception
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.11
CRC Operation Circuit
The cyclic redundancy check (CRC) operation circuit detects errors in data blocks. 18.11.1 Features The features of the CRC operation circuit are listed below. * * * * CRC code generated for any desired data length in an 8-bit unit CRC operation executed on eight bits in parallel One of three generating polynomials selectable CRC code generation for LSB-first or MSB-first communication selectable
Figure 18.43 shows a block diagram of the CRC operation circuit.
CRCCR
Control signal
Internal bus
CRCDIR
CRC code generation circuit
CRCDOR
[Legend] CRCCR: CRC control register CRCDIR: CRC data input register CRCDOR: CRC data output register
Figure 18.43 Block Diagram of CRC Operation Circuit
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.11.2 Register Descriptions The CRC operation circuit has the following registers. * CRC control register (CRCCR) * CRC data input register (CRCDIR) * CRC data output register (CRCDOR) (1) CRC Control Register (CRCCR)
CRCCR initializes the CRC operation circuit, switches the operation mode, and selects the generating polynomial.
Bit Bit Name Initial Value R/W 7 DORCLR 0 W 6 0 R 5 0 R 4 0 R 3 0 R 2 LMS 0 R/W 1 G1 0 R/W 0 G0 0 R/W
Bit 7 6 to 3 2
Bit Name DORCLR -- LMS
Initial Value 0 All 0 0
R/W W R R/W
Description CRCDOR Clear Setting this bit to 1 clears CRCDOR to H'0000. Reserved The initial value should not be changed. CRC Operation Switch Selects CRC code generation for LSB-first or MSB-first communication. 0: Performs CRC operation for LSB-first communication. The lower byte (bits 7 to 0) is first transmitted when CRCDOR contents (CRC code) are divided into two bytes to be transmitted in two parts. 1: Performs CRC operation for MSB-first communication. The upper byte (bits 15 to 8) is first transmitted when CRCDOR contents (CRC code) are divided into two bytes to be transmitted in two parts.
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
Bit 1 0
Bit Name G1 G0
Initial Value 0 0
R/W R/W R/W
Description CRC Generating Polynomial Select: Selects the polynomial. 00: Reserved
8 2 01: X + X + X + 1 16 15 2 10: X + X + X + 1 16 12 5 11: X + X + X + 1
(2)
CRC Data Input Register (CRCDIR)
CRCDIR is an 8-bit readable/writable register, to which the bytes to be CRC-operated are written. The result is obtained in CRCDOR.
Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0
(3)
CRC Data Output Register (CRCDOR)
CRCDOR is a 16-bit readable/writable register that contains the result of CRC operation when the bytes to be CRC-operated are written to CRCDIR after CRCDOR is cleared. When the CRC operation result is additionally written to the bytes to which CRC operation is to be performed, the CRC operation result will be H'0000 if the data contains no CRC error. When bits 1 and 0 in CRCCR (G1 and G0 bits) are set to 0 and 1, respectively, the lower byte of this register contains the result.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 7 6 5 4 3 2 1 0
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.11.3 CRC Operation Circuit Operation The CRC operation circuit generates a CRC code for LSB-first/MSB-first communications. An example in which a CRC code for hexadecimal data H'F0 is generated using the X16 + X12 + X5 + 1 polynomial with the G1 and G0 bits in CRCCR set to B'11 is shown below.
1. Write H'83 to CRCCR 7 CRCCR 1 0 0 0 0 0 2. Write H'F0 to CRCDIR 7 CRCDIR 1 1 1 1 0 0
0 11
0 00
CRCDOR clearing 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 0 0 0 0 0 00 00 CRCDORH CRCDORL 7 1 1 1 0 1 0 1 0
CRC code generation 0 0 1 1 1 11 11
3. Read from CRCDOR CRC code = H'F78F 4. Serial transmission (LSB first) CRC code 7 1 1 F 1 1 0 1 7 1 0 1 7 1 0 8 0 0 1 1 F 1 0 1 7 1 1 F 1 1 0 0 0 0 Data 0 0 Output
Figure 18.44 LSB-First Data Transmission
1. Write H'87 to CRCCR 7 CRCCR 1 0 0 0 0 1 2. Write H'F0 to CRCDIR 7 CRCDIR 1 1 1 1 0 0 0
0 11
0 0
7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0
CRCDOR clearing 0 0 0 0 0 00 00 CRCDORH CRCDORL
7 1 0 1 0 1 0 0 1
CRC code generation 0 1 1 1 1 1 1 1 1
3. Read from CRCDOR CRC code = H'EF1F 4. Serial transmission (MSB first) Data 7 Output 1 1 F 1 1 0 0 0 0 0 0 7 1 1 E 1 0 1 1 F 1 CRC code 0 1 7 0 0 1 0 1 1 1 F 1 0 1
Figure 18.45 MSB-First Data Transmission
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
1. Serial reception (LSB first) CRC code 7 1 1 F 1 1 0 1 7 1 0 1 7 1 0 8 0 0 1 1 F 1 0 1 7 1 1 F 1 1 0 0 0 0 Data 0 0 Input
2. Write H'83 to CRCCR 7 CRCCR 1 0 0 0 0 0 1 0 1
3. Write H'F0 to CRCDIR 7 CRCDIR 1 1 1 1 0 0 0 0 0
CRCDOR clearing 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDORH CRCDORL 7 1 1 1 0 1 0 1 0
CRC code generation 0 0 1 1 1 1 1 1 1
4. Write H'8F to CRCDIR 7 CRCDIR 1 0 0 0 1 1 1 0 1
5. Write H'F7 to CRCDIR 7 CRCDIR 1 1 1 1 0 1 1 0 1
CRC code generation 7 CRCDORH CRCDORL 0 1 0 1 0 1 0 1 0 0 0 1 0 1 0 0 1 CRCDORH CRCDORL 7 0 0 0 0 0 0 0 0
CRC code generation 0 0 0 0 0 0 0 0 0
6. Read from CRCDOR CRC code = H'0000 No error
Figure 18.46 LSB-First Data Reception
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
1. Serial reception (MSB first) Data 7 Input 1 1 F 1 1 0 0 0 0 0 0 7 1 1 E 1 0 1 1 F 1 CRC code 0 1 7 0 0 1 0 1 1 1 F 1 0 1
2. Write H'83 to CRCCR 7 CRCCR 1 0 0 0 0 1 1 0 1
3. Write H'F0 to CRCDIR 7 CRCDIR 1 1 1 1 0 0 0 0 0
CRCDOR clearing 7 CRCDORH CRCDORL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CRCDORH CRCDORL 7 1 0 1 0 1 0 0 1
CRC code generation 0 1 1 1 1 1 1 1 1
4. Write H'EF to CRCDIR 7 CRCDIR 1 1 1 0 1 1 1 0 1
5. Write H'1F to CRCDIR 7 CRCDIR 0 0 0 1 1 1 1 0 1
CRC code generation 7 CRCDORH CRCDORL 0 0 0 0 0 0 1 0 1 0 1 0 1 0 0 1 0 CRCDORH CRCDORL 7 0 0 0 0 0 0 0 0
CRC code generation 0 0 0 0 0 0 0 0 0
6. Read from CRCDOR CRC code = H'0000 No error
Figure 18.47 MSB-First Data Reception
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Section 18 Serial Communication Interface (SCI, IrDA, CRC)
18.11.4 Note on CRC Operation Circuit Note that the sequence to transmit the CRC code differs between LSB-first transmission and MSB-first transmission.
1. CRC code generation After specifying the operation method, write data to CRCDIR in the sequence of (1) (2) (3) (4). 7 0 CRCDIR (1) (2) (3) (4) CRC code generation 0 (5) (6)
7 CRCDORH CRCDORL 2. Transmission data (i) LSB-first transmission
CRC code 7 (5) 07 (6) 07 (4) 07 (3) 07 (2) 07 (1) 0 Output
(ii) MSB-first transmission CRC code 7 Output (1) 07 (2) 07 (3) 07 (4) 07 (5) 07 (6) 0
Figure 18.48 LSB-First and MSB-First Transmit Data
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Section 19 USB Function Module (USB)
Section 19 USB Function Module (USB)
This LSI incorporates a USB function module (USB).
19.1
Features
* The UDC (USB device controller) conforming to USB2.0 and transceiver process USB protocol automatically. Automatic processing of USB standard commands for endpoint 0 (some commands and class/vendor commands require decoding and processing by firmware) * Transfer speed: Supports full-speed (12 Mbps) * Endpoint configuration:
Endpoint Name Endpoint 0 Maximum FIFO Buffer Abbreviation Transfer Type Packet Size Capacity (Byte) EP0s EP0i EP0o Endpoint 1 Endpoint 2 Endpoint 3 EP1 EP2 EP3 Setup Control-in Control-out Bulk-out Bulk-in Interrupt-in 8 8 8 64 64 8 8 8 8 128 128 8 DMA Transfer -- -- -- Possible Possible --
Configuration1-Interface0-AlternateSetting0
EndPoint1 EndPoint2 EndPoint3
* Interrupt requests: Generates various interrupt signals necessary for USB transmission/reception * Power mode: Self power mode or bus power mode can be selected by the power mode bit (PWMD) in the control register (CTLR).
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Section 19 USB Function Module (USB)
Figure 19.1 shows the block diagram of the USB.
Peripheral bus USB function module
Interrupt requests
Status and control registers D+ UDC FIFO Transceiver D-
Clock for USB (48 MHz) [Legend] UDC: USB device controller
Figure 19.1 Block Diagram of USB
19.2
Input/Output Pins
Table 19.1 shows the USB pin configuration. Table 19.1 Pin Configuration
Pin Name VBUS USD+ USDDrVcc DrVss I/O Input I/O I/O Input Input Function USB cable connection monitor pin USB data I/O pin USB data I/O pin Power supply pin for USB on-chip transceiver Ground pin for USB on-chip transceiver
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Section 19 USB Function Module (USB)
19.3
Register Descriptions
The USB has following registers. For the information on the addresses of these registers and the state of the register in each processing condition, see section 28, List of Registers. * * * * * * * * * * * * * * * * * * * * * * * * * * * Interrupt flag register 0 (IFR0) Interrupt flag register 1 (IFR1) Interrupt flag register 2 (IFR2) Interrupt select register 0 (ISR0) Interrupt select register 1 (ISR1) Interrupt select register 2 (ISR2) Interrupt enable register 0 (IER0) Interrupt enable register 1 (IER1) Interrupt enable register 2 (IER2) EP0i data register (EPDR0i) EP0o data register (EPDR0o) EP0s data register (EPDR0s) EP1 data register (EPDR1) EP2 data register (EPDR2) EP3 data register (EPDR3) EP0o receive data size register (EPSZ0o) EP1 receive data size register (EPSZ1) Trigger register (TRG) Data status register (DASTS) FIFO clear register (FCLR) DMA transfer setting register (DMA) Endpoint stall register (EPSTL) Configuration value register (CVR) Control register (CTLR) Endpoint information register (EPIR) Transceiver test register 0 (TRNTREG0) Transceiver test register 1 (TRNTREG1)
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Section 19 USB Function Module (USB)
19.3.1
Interrupt Flag Register 0 (IFR0)
IFR0, together with interrupt flag registers 1and 2 (IFR1and IFR2), indicates interrupt status information required by the application. When an interrupt source is generated, the corresponding bit is set to 1. And then this bit, in combination with interrupt enable register 0 (IER0), generates an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits. However, since EP1FULL and EP2EMPTY are status bits, these bits cannot be cleared.
Bit Bit Name Initial Value R/W 7 BRST 0 R/W 6 EP1 FULL 0 R 5 EP2 TR 0 R/W 4 3 2 EP0o TS 0 R/W 1 EP0i TR 0 R/W 0 EP0i TS 0 R/W
EP2 EMPTY SETUP TS 1 R 0 R/W
Bit 7
Bit Name BRST
Initial Value 0
R/W R/W
Description Bus Reset This bit is set to 1 when a bus reset signal is detected on the USB bus. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
6
EP1 FULL
0
R
EP1 FIFO Full This bit is set when endpoint 1 receives one packet of data successfully from the host, and holds a value of 1 as long as there is valid data in the FIFO buffer. This is a status bit, and cannot be cleared.
5
EP2 TR
0
R/W
EP2 Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 2 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
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Section 19 USB Function Module (USB)
Bit 4
Bit Name EP2 EMPTY
Initial Value 1
R/W R
Description EP2 FIFO Empty This bit is set when at least one of the dual endpoint 2 transmit FIFO buffers is ready for transmit data to be written. This is a status bit, and cannot be cleared.
3
SETUP TS
0
R/W
Setup Command Receive Complete This bit is set to 1 when endpoint 0 receives successfully a setup command requiring decoding on the application side, and returns an ACK handshake to the host. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
2
EP0o TS
0
R/W
EP0o Receive Complete This bit is set to 1 when endpoint 0 receives data from the host successfully, stores the data in the FIFO buffer, and returns an ACK handshake to the host. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
1
EP0i TR
0
R/W
EP0i Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 0 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
0
EP0i TS
0
R/W
EP0i Transmit Complete This bit is set when data is transmitted to the host from endpoint 0 and an ACK handshake is returned. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
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Section 19 USB Function Module (USB)
19.3.2
Interrupt Flag Register 1 (IFR1)
IFR1, together with interrupt flag registers 0 and 2 (IFR0 and IFR2), indicates interrupt status information required by the application. When an interrupt source is generated, the corresponding bit is set to 1. And then this bit, in combination with interrupt enable register 1 (IER1), generates an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 VBUS MN 0 R 2 EP3 TR 0 R/W 1 EP3 TS 0 R/W 0 VBUSF 0 R/W
Bit 7 6 5 4 3
Bit Name -- -- -- VBUS MN
Initial Value 0 0 0 0 0
R/W R R R R R
Description Reserved These bits are always read as 0. The write value should always be 0.
This is a status bit which monitors the state of the VBUS pin. This bit reflects the state of the VBUS pin and generates no interrupt request. This bit is always 0 when the PULLUP_E bit in DMA is 0.
2
EP3 TR
0
R/W
EP3 Transfer Request This bit is set if there is no valid transmit data in the FIFO buffer when an IN token for endpoint 3 is received from the host. A NACK handshake is returned to the host until data is written to the FIFO buffer and packet transmission is enabled. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
1
EP3 TS
0
R/W
EP3 Transmit Complete This bit is set when data is transmitted to the host from endpoint 3 and an ACK handshake is returned. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
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Section 19 USB Function Module (USB)
Bit 0
Bit Name VBUSF
Initial Value 0
R/W R/W
Description USB Disconnection Detection When the function is connected to the USB bus or disconnected from it, this bit is set to 1. The VBUS pin of this module is used for detecting connection or disconnection. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
19.3.3
Interrupt Flag Register 2 (IFR2)
IFR2, together with interrupt flag registers 0 and 1 (IFR0 and IFR1), indicates interrupt status information required by the application. When an interrupt source is generated, the corresponding bit is set to 1. And then this bit, in combination with interrupt enable register 2 (IER2), generates an interrupt request to the CPU. To clear, write 0 to the bit to be cleared and 1 to the other bits.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 SURSS 0 R 4 SURSF 0 R/W 3 CFDN 0 R/W 2 0 R 1 SETC 0 R/W 0 SETI 0 R/W
Bit 7 6 5
Bit Name -- -- SURSS
Initial Value 0 0 0
R/W R R R
Description Reserved These bits are always read as 0. The write value should always be 0. Suspend/Resume Status This is a status bit that describes bus state. 0: Normal state 1: Suspended state This bit is a status bit and generates no interrupt request.
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Section 19 USB Function Module (USB)
Bit 4
Bit Name SURSF
Initial Value 0
R/W R/W
Description Suspend/Resume Detection This bit is set to 1 when the state changed from normal to suspended state or vice versa. The corresponding interrupt output is RESUME, USBINTN2, and USBINTN3. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
3
CFDN
0
R/W
End Point Information Load End This bit is set to 1 when writing data in the endpoint information register to the EPIR register ends (load end). This module starts the USB operation after the endpoint information is completely set. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
2
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
1
SETC
0
R/W
Set_Configuration Command Detection When the Set_Configuration command is detected, this bit is set to 1. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
0
SETI
0
R/W
Set_Interface Command Detection When the Set_Interface command is detected, this bit is set to 1. (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
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Section 19 USB Function Module (USB)
19.3.4
Interrupt Select Register 0 (ISR0)
ISR0 selects the vector numbers of the interrupt requests indicated in interrupt flag register 0 (IFR0). If the USB issues an interrupt request to the INTC when a bit in ISR0 is cleared to 0, the interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the INTC when a bit in ISR0 is set to 1, the corresponding interrupt will be USBINTN3.
Bit Bit Name Initial Value R/W 7 BRST 0 R/W 6 EP1 FULL 0 R/W 5 EP2 TR 0 R/W 4 3 2 EP0o TS 0 R/W 1 EP0i TR 0 R/W 0 EP0i TS 0 R/W
EP2 EMPTY SETUP TS 0 R/W 0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name BRST EP1 FULL EP2 TR
Initial Value 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Bus Reset EP1 FIFO Full EP2 Transfer Request EP2 FIFO Empty Setup Command Receive Complete EP0o Receive Complete EP0i Transfer Request EP0i Transmission Complete
EP2 EMPTY 0 SETUP TS EP0o TS EP0i TR EP0i TS 0 0 0 0
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Section 19 USB Function Module (USB)
19.3.5
Interrupt Select Register 1 (ISR1)
ISR1 selects the vector numbers of the interrupt requests indicated in interrupt flag register 1 (IFR1). If the USB issues an interrupt request to the INTC when a bit in ISR1 is cleared to 0, the interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the INTC when a bit in ISR1 is set to 1, the corresponding interrupt will be USBINTN3.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 EP3 TR 1 R/W 1 EP3 TS 1 R/W 0 VBUSF 1 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name EP3 TR EP3 TS VBUSF
Initial Value 0 0 0 0 0 1 1 1
R/W R R R R R R/W R/W R/W
Description Reserved These bits are always read as 0. The write value should always be 0.
EP3 Transfer Request EP3 Transmission Complete USB Bus Connect
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Section 19 USB Function Module (USB)
19.3.6
Interrupt Select Register 2 (ISR2)
ISR2 selects the vector numbers of the interrupt requests indicated in interrupt flag register 2 (IFR2). If the USB issues an interrupt request to the INTC when a bit in ISR2 is cleared to 0, the interrupt corresponding to the bit will be USBINTN2. If the USB issues an interrupt request to the INTC when a bit in ISR2 is set to 1, the corresponding interrupt will be USBINTN3.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 SURSE 1 R/W 3 CFDN 1 R/W 2 1 R 1 SETCE 1 R/W 0 SETIE 1 R/W
Bit 7 6 5 4 3 2
Bit Name SURSE CFDN
Initial Value 0 0 0 1 1 1
R/W R R R R/W R/W R
Description Reserved These bits are always read as 0. The write value should always be 0. Suspend/Resume Detection End Point Information Load End Reserved This bit is always read as 1. The write value should always be 1.
1 0
SETCE SETIE
1 1
R/W R/W
Set_Configuration Command Detection Set_Interface Command Detection
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Section 19 USB Function Module (USB)
19.3.7
Interrupt Enable Register 0 (IER0)
IER0 enables the interrupt requests of interrupt flag register 0 (IFR0). When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is determined by the contents of interrupt select register 0 (ISR0).
Bit Bit Name Initial Value R/W 7 BRST 0 R/W 6 EP1 FULL 0 R/W 5 EP2 TR 0 R/W 4 3 2 EP0o TS 0 R/W 1 EP0i TR 0 R/W 0 EP0i TS 0 R/W
EP2 EMPTY SETUP TS 0 R/W 0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name BRST EP1 FULL EP2 TR EP2 EMPTY SETUP TS EP0o TS EP0i TR EP0i TS
Initial Value 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Bus Reset EP1 FIFO Full EP2 Transfer Request EP2 FIFO Empty Setup Command Receive Complete EP0o Receive Complete EP0i Transfer Request EP0i Transmission Complete
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Section 19 USB Function Module (USB)
19.3.8
Interrupt Enable Register 1 (IER1)
IER1 enables the interrupt requests of interrupt flag register 1 (IFR1). When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is determined by the contents of interrupt select register 1 (ISR1).
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 EP3 TR 0 R/W 1 EP3 TS 0 R/W 0 VBUSF 0 R/W
Bit 7 6 5 4 3 2 1 0
Bit Name EP3 TR EP3 TS VBUSF
Initial Value 0 0 0 0 0 0 0 0
R/W R R R R R R/W R/W R/W
Description Reserved These bits are always read as 0. The write value should always be 0.
EP3 Transfer Request EP3 Transmission Complete USB Bus Connect
19.3.9
Interrupt Enable Register 2 (IER2)
IER2 enables the interrupt requests of interrupt flag register 2 (IFR2). When an interrupt flag is set to 1 while the corresponding bit of each interrupt is set to 1, an interrupt request is sent to the CPU. The interrupt vector number is determined by the contents of interrupt select register 2 (ISR2).
Bit Bit Name Initial Value R/W 7 SSRSME 0 R/W 6 0 R 5 0 R 4 SURSE 0 R/W 3 CFDN 0 R/W 2 0 R 1 SETCE 0 R/W 0 SETIE 0 R/W
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Section 19 USB Function Module (USB)
Bit 7
Bit Name SSRSME
Initial Value 0
R/W R/W
Description Resume Detection for Software Standby Cancel For the details of the operation, see section 19.5.3, Suspend and Resume Operations.
6, 5
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
4
SURSE
0
R/W
Suspend/Resume Detection For the details of the operation, see section 19.5.3, Suspend and Resume Operations.
3 2
CFDN
0 0
R/W R
End Point Information Load End Reserved This bit is always read as 0. The write value should always be 0.
1 0
SETCE SETIE
0 0
R/W R/W
Set_Configuration Command Detection Set_Interface Command Detection
19.3.10 EP0i Data Register (EPDR0i) EPDR0i is an 8-byte transmit FIFO buffer for endpoint 0. EPDR0i holds one packet of transmit data for control-in. Transmit data is fixed by writing one packet of data and setting EP0iPKTE in the trigger register. When an ACK handshake is returned from the host after the data has been transmitted, EP0iTS in interrupt flag register 0 is set. This FIFO buffer can be initialized by means of EP0iCLR in the FCLR register.
Bit Bit Name Initial Value R/W 7 D7 Undefined W 6 D6 Undefined W 5 D5 Undefined W 4 D4 Undefined W 3 D3 Undefined W 2 D2 Undefined W 1 D1 Undefined W 0 D0 Undefined W
Bit 7 to 0
Bit Name D7 to D0
Initial Value
R/W
Description Data register for control-in transfer
Undefined W
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Section 19 USB Function Module (USB)
19.3.11 EP0o Data Register (EPDR0o) EPDR0o is an 8-byte receive FIFO buffer for endpoint 0. EPDR0o holds endpoint 0 receive data other than setup commands. When data is received successfully, EP0oTS in interrupt flag register 0 is set, and the number of receive bytes is indicated in the EP0o receive data size register. After the data has been read, setting EP0oRDFN in the trigger register enables the next packet to be received. This FIFO buffer can be initialized by means of BP0oCLR in the FCLR register.
Bit Bit Name Initial Value R/W 7 D7 0 R 6 D6 0 R 5 D5 0 R 4 D4 0 R 3 D3 0 R 2 D2 0 R 1 D1 0 R 0 D0 0 R
Bit 7 to 0
Bit Name D7 to D0
Initial Value All 0
R/W R
Description Data register for control-out transfer
19.3.12 EP0s Data Register (EPDR0s) EPDR0s is an 8-byte FIFO buffer specifically for receiving endpoint 0 setup commands. Only the setup command to be processed by the application is received. When command data is received successfully, the SETUPTS bit in interrupt flag register 0 is set. As a latest setup command must be received in high priority, if data is left in this buffer, it will be overwritten with new data. If reception of the next command is started while the current command is being read, command reception has priority, the read by the application is forcibly stopped, and the read data is invalid.
Bit Bit Name Initial Value R/W 7 D7 0 R 6 D6 0 R 5 D5 0 R 4 D4 0 R 3 D3 0 R 2 D2 0 R 1 D1 0 R 0 D0 0 R
Bit 7 to 0
Bit Name D7 to D0
Initial Value All 0
R/W R
Description Data register for storing the setup command at the control-out transfer
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Section 19 USB Function Module (USB)
19.3.13 EP1 Data Register (EPDR1) EPDR1 is a 128-byte receive FIFO buffer for endpoint 1. EPDR1 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When one packet of data is received successfully, EP1FULL in interrupt flag register 0 is set, and the number of receive bytes is indicated in the EP1 receive data size register. After the data has been read, the buffer that was read is enabled to receive data again by writing 1 to the EP1RDFN bit in the trigger register. The receive data in this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized by means of EP1CLR in the FCLR register.
Bit Bit Name Initial Value R/W 7 D7 0 R 6 D6 0 R 5 D5 0 R 4 D4 0 R 3 D3 0 R 2 D2 0 R 1 D1 0 R 0 D0 0 R
Bit 7 to 0
Bit Name D7 to D0
Initial Value All 0
R/W R
Description Data register for endpoint 1 transfer
19.3.14 EP2 Data Register (EPDR2) EPDR2 is a 128-byte transmit FIFO buffer for endpoint 2. EPDR2 has a dual-buffer configuration, and has a capacity of twice the maximum packet size. When transmit data is written to this FIFO buffer and EP2PKTE in the trigger register is set, one packet of transmit data is fixed, and the dual-FIFO buffer is switched over. The transmit data for this FIFO buffer can be transferred by DMA. This FIFO buffer can be initialized by means of EP2CLR in the FCLR register.
Bit Bit Name Initial Value R/W 7 D7 Undefined W 6 D6 Undefined W 5 D5 Undefined W 4 D4 Undefined W 3 D3 Undefined W 2 D2 Undefined W 1 D1 Undefined W 0 D0 Undefined W
Bit 7 to 0
Bit Name D7 to D0
Initial Value
R/W
Description Data register for endpoint 2 transfer
Undefined W
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Section 19 USB Function Module (USB)
19.3.15 EP3 Data Register (EPDR3) EPDR3 is an 8-byte transmit FIFO buffer for endpoint 3. EPDR3 holds one packet of transmit data for the interrupt transfer of endpoint 3. Transmit data is fixed by writing one packet of data and setting EP3PKTE in the trigger register. When an ACK handshake is returned from the host after one packet of data has been transmitted successfully, EP3TS in interrupt flag register 0 is set. This FIFO buffer can be initialized by means of EP3CLR in the FCLR register.
Bit Bit Name Initial Value R/W 7 D7 Undefined W 6 D6 Undefined W 5 D5 Undefined W 4 D4 Undefined W 3 D3 Undefined W 2 D2 Undefined W 1 D1 Undefined W 0 D0 Undefined W
Bit 7 to 0
Bit Name D7 to D0
Initial Value
R/W
Description Data register for endpoint 3 transfer
Undefined W
19.3.16 EP0o Receive Data Size Register (EPSZ0o) EPSZ0o indicates the number of bytes received at endpoint 0 from the host.
Bit Bit Name Initial Value R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R
Bit 7 to 0
Bit Name --
Initial Value All 0
R/W R
Description Number of receive data for endpoint 0
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Section 19 USB Function Module (USB)
19.3.17 EP1 Receive Data Size Register (EPSZ1) EPSZ1 is a receive data size resister for endpoint 1. EPSZ1 indicates the number of bytes received from the host. The FIFO for endpoint 1 has a dual-buffer configuration. The size of the received data indicated by this register is the size of the currently selected side (can be read by CPU).
Bit Bit Name Initial Value R/W 7 -- 0 R 6 -- 0 R 5 -- 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R
Bit 7 to 0
Bit Name --
Initial Value All 0
R/W R
Description Number of received bytes for endpoint 1
19.3.18 Trigger Register (TRG) TRG generates one-shot triggers to control the transfer sequence for each endpoint.
Bit Bit Name Initial Value R/W 7 Undefined 6 EP3 PKTE Undefined W 5 EP1 RDFN Undefined W 4 EP2 PKTE Undefined W 3 Undefined 2 1 0
EP0s RDFN EP0o RDFN EP0i PKTE Undefined W Undefined W Undefined W
Bit 7 6
Bit Name EP3 PKTE
Initial Value Undefined Undefined
R/W W
Description Reserved The write value should always be 0. EP3 Packet Enable After one packet of data has been written to the endpoint 3 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit.
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Section 19 USB Function Module (USB)
Bit 5
Bit Name EP1 RDFN
Initial Value Undefined
R/W W
Description EP1 Read Complete Write 1 to this bit after one packet of data has been read from the endpoint 1 FIFO buffer. The endpoint 1 receive FIFO buffer has a dual-buffer configuration. Writing 1 to this bit initializes the FIFO that was read, enabling the next packet to be received.
4
EP2 PKTE
Undefined
W
EP2 Packet Enable After one packet of data has been written to the endpoint 2 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit.
3 2
Undefined
W
Reserved The write value should always be 0. EP0s Read Complete Write 1 to this bit after data for the EP0s command FIFO has been read. Writing 1 to this bit enables transfer of data in the following data stage. A NACK handshake is returned in response to transfer requests from the host in the data stage until 1 is written to this bit.
EP0s RDFN Undefined
1
EP0o RDFN Undefined
W
EP0o Read Complete Writing 1 to this bit after one packet of data has been read from the endpoint 0 transmit FIFO buffer initializes the FIFO buffer, enabling the next packet to be received.
0
EP0i PKTE
Undefined
W
EP0i Packet Enable After one packet of data has been written to the endpoint 0 transmit FIFO buffer, the transmit data is fixed by writing 1 to this bit.
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Section 19 USB Function Module (USB)
19.3.19 Data Status Register (DASTS) DASTS indicates whether the transmit FIFO buffers contain valid data. A bit is set when data is written to the corresponding FIFO buffer and the packet enable state is set, and cleared when all data has been transmitted to the host.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 EP3 DE 0 R 4 EP2 DE 0 R 3 0 R 2 0 R 1 0 R 0 EP0i DE 0 R
Bit 7 6 5
Bit Name EP3 DE
Initial Value 0 0 0
R/W R R R
Description Reserved These bits are always read as 0. The write value should always be 0. EP3 Data Present This bit is set when the endpoint 3 FIFO buffer contains valid data.
4
EP2 DE
0
R
EP2 Data Present This bit is set when the endpoint 2 FIFO buffer contains valid data.
3 2 1 0
EP0i DE
0 0 0 0
R R R R
Reserved These bits are always read as 0. EP0i Data Present This bit is set when the endpoint 0 FIFO buffer contains valid data.
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Section 19 USB Function Module (USB)
19.3.20 FIFO Clear Register (FCLR) FCLR is a register to initialize the FIFO buffers for each endpoint. Writing 1 to a bit clears all the data in the corresponding FIFO buffer. Note that the corresponding interrupt flag is not cleared. Do not clear a FIFO buffer during transfer.
Bit Bit Name Initial Value R/W 7 Undefined 6 EP3 CLR Undefined W 5 EP1 CLR Undefined W 4 EP2 CLR Undefined W 3 Undefined 2 Undefined 1 EP0o CLR Undefined W 0 EP0i CLR Undefined W
Bit 7 6
Bit Name EP3 CLR
Initial Value Undefined Undefined
R/W W
Description Reserved The write value should always be 0. EP3 Clear Writing 1 to this bit initializes the endpoint 3 transmit FIFO buffer.
5
EP1 CLR
Undefined
W
EP1 Clear Writing 1 to this bit initializes both sides of the endpoint 1 receive FIFO buffer.
4
EP2 CLR
Undefined
W
EP2 Clear Writing 1 to this bit initializes both sides of the endpoint 2 transmit FIFO buffer.
3 2 1
EP0o CLR
Undefined Undefined
W
Reserved The write value should always be 0. EP0o Clear Writing 1 to this bit initializes the endpoint 0 receive FIFO buffer.
0
EP0i CLR
Undefined
W
EP0i Clear Writing 1 to this bit initializes the endpoint 0 transmit FIFO buffer.
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Section 19 USB Function Module (USB)
19.3.21 DMA Transfer Setting Register (DMA) DMA transfer can be carried out between the endpoint 1 and 2 data registers and memory by means of the on-chip direct memory access controller (DMAC). Dual address transfer is performed in bytes. To start DMA transfer, DMAC settings must be made in addition to the settings in this register.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 PULLUP_E 0 R/W 1 EP2DMAE 0 R/W 0 EP1DMAE 0 R/W
Bit 7 6 5 4 3 2
Bit Name
Initial Value 0 0 0 0 0
R/W R R R R R R/W
Description Reserved These bits are always read as 0. The write value should always be 0.
PULLUP_E 0
PULLUP Enable This pin performs the pull-up control for the D+ pin, with using PM4 as the pull-up control pin. 0: D+ is not pulled up. 1: D+ is pulled up.
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Section 19 USB Function Module (USB)
Bit 1
Bit Name EP2DMAE
Initial Value 0
R/W R/W
Description Endpoint 2 DMA Transfer Enable When this bit is set, DMA transfer is enabled from memory to the endpoint 2 transmit FIFO buffer. If there is at least one byte of open space in the FIFO buffer, a DMAC start interrupt signal (USBINTN1) is asserted. In DMA transfer, when 64 bytes are written to the FIFO buffer the EP2 packet enable bit is set automatically, allowing 64 bytes of data to be transferred, and if there is still space in the other side of the two FIFOs, the DMAC start interrupt signal (USBINTN1) is asserted again. However, if the size of the data packet to be transmitted is less than 64 bytes, the EP2 packet enable bit is not set automatically, and so should be set by the CPU with a DMA transfer end interrupt. As EP2-related interrupt requests to the CPU are not automatically masked, interrupt requests should be masked as necessary in the interrupt enable register. * Operating procedure 1. Write of 1 to the EP2 DMAE bit in DMAR 2. Set the DMAC to activate through USBINTN1 3. Transfer count setting in the DMAC 4. DMAC activation 5. DMA transfer 6. DMA transfer end interrupt generated See section 19.8.3, DMA Transfer for Endpoint 2.
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Section 19 USB Function Module (USB)
Bit 0
Bit Name EP1DMAE
Initial Value 0
R/W R/W
Description Endpoint 1 DMA Transfer Enable When this bit is set, a DMAC start interrupt signal (USBINTN0) is asserted and DMA transfer is enabled from the endpoint 1 receive FIFO buffer to memory. If there is at least one byte of receive data in the FIFO buffer, the DMAC start interrupt signal (USBINTN0) is asserted. In DMA transfer, when all the received data is read, EP1 is automatically read and the completion trigger operates. EP1-related interrupt requests to the CPU are not automatically masked. * Operating procedure: 1. Write of 1 to the EP1 DMAE bit in DMA 2. Set the DMAC to activate through USBINTN0 3. Transfer count setting in the DMAC 4. DMAC activation 5. DMA transfer 6. DMA transfer end interrupt generated See section 19.8.2, DMA Transfer for Endpoint 1.
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Section 19 USB Function Module (USB)
19.3.22 Endpoint Stall Register (EPSTL) The bits in EPSTL are used to forcibly stall the endpoints on the application side. While a bit is set to 1, the corresponding endpoint returns a stall handshake to the host. The stall bit for endpoint 0 is cleared automatically on reception of 8-byte command data for which decoding is performed by the function and the EP0 STL bit is cleared. When the SETUPTS flag in the IFR0 register is set to 1, writing 1 to the EP0 STL bit is ignored. For detailed operation, see section 19.7, Stall Operations.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 EP3STL 0 R/W 2 EP2STL 0 R/W 1 EP1STL 0 R/W 0 EP0STL 0 R/W
Bit 7 6 5 4 3
Bit Name EP3STL
Initial Value 0 0 0 0 0
R/W R R R R R/W
Description Reserved These bits are always read as 0. The write value should always be 0.
EP3 Stall When this bit is set to 1, endpoint 3 is placed in the stall state.
2
EP2STL
0
R/W
EP2 Stall When this bit is set to 1, endpoint 2 is placed in the stall state.
1
EP1STL
0
R/W
EP1 Stall When this bit is set to 1, endpoint 1 is placed in the stall state.
0
EP0STL
0
R/W
EP0 Stall When this bit is set to 1, endpoint 0 is placed in the stall state.
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Section 19 USB Function Module (USB)
19.3.23 Configuration Value Register (CVR) This register stores the Configuration, Interface, or Alternate set value when the Set Configuration or Set Interface command from the host is correctly received.
Bit Bit Name Initial Value R/W 7 CNFV1 0 R 6 CNFV0 0 R 5 INTV1 0 R 4 INTV0 0 R 3 0 R 2 ALTV2 0 R 1 ALTV1 0 R 0 ALTV0 0 R
Bit 7 6 5 4 3
Bit Name CNFV1 CNFV0 INTV1 INTV0
Initial Value All 0
R/W R
Description These bits store Configuration Setting value when they receive Set Configuration command. CNFV is updated when the SETC bit in IFR2 is set to 1. These bits store Interface Setting value when they receive Set Interface command. INTV is updated when the SETI bit in IFR2 is set to 1. Reserved This bit is always read as 0. The write value should always be 0.
All 0
R
0
R
2 1 0
ALTV2 ALTV1 ALTV0
0 0 0
R R R
These bits store Alternate Setting value when they receive Set Interface command. ALTV2 to ALTV0 are updated when the SETI bit in IFR2 is set to 1.
19.3.24 Control Register (CTLR) This register sets functions for bits ASCE, PWMD, RSME, and, PWUPS.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 RWUPS 0 R 3 RSME 0 R/W 2 PWMD 0 R/W 1 ASCE 0 R/W 0 0 R
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Section 19 USB Function Module (USB)
Bit 7 6 5 4
Bit Name RWUPS
Initial Value 0 0 0 0
R/W R R R R
Description Reserved These bits are always read as 0. The write value should always be 0. Remote Wakeup Status This status bit indicates remote wakeup command from USB host is enabled or disabled. This bit is set to 0 when remote wakeup command from UBM host is disabled by Device_Remote_Wakeup due to Set Feature or Clear Feature request. This bit is set to 1 when remote wakeup command is enabled.
3
RSME
0
R/W
Resume Enable This bit releases the suspend state (or executes remote wakeup). When RSME is set to 1, resume request starts. If RSME is once set to 1, clear this bit to 0 again afterwards. In this case, the value 1 set to RSME must be kept for at least one clock period of 12-MHz clock.
2
PWMD
0
R/W
Bus Power Mode This bit specifies the USB power mode. When PWMD is set to 0, the self-power mode is selected for this module. When set to 1, the bus-power mode is selected.
1
ASCE
0
R/W
Automatic Stall Clear Enable Setting the ASCE bit to 1 automatically clears the stall setting bit (the EPxSTL (x = 0, 1, 2, or 3) bit in EPSTLR0 or EPSTR1) of the end point that has returned the stall handshake to the host. The automatic stall clear enable is common to the all end points. Thus the individual control of the end point is not possible. When the ASCE bit is set to 0, the stall setting bit is not automatically cleared. This bit must be released by the users. To enable this bit, make sure that the ASCE bit should be set to 1 before the EPxSTL (x = 0, 1, 2, or 3) bit in EPSTL is set to 1.
0
--
0
R
Reserved This bit is always read as 0. The write value should always be 0.
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Section 19 USB Function Module (USB)
19.3.25 Endpoint Information Register (EPIR) This register sets the information for each endpoint. Each endpoint needs five bytes to store the information. Writing data should be done in sequence starting at logical endpoint 0. Do not write data of more than 50 bytes (five bytes multiplied by ten endpoints) to this register. The information should be written to this register only once at a reset and no data should be written after that. Description of writing data for one endpoint is shown below. Although this register consists of one register to which data is written sequentially for one address, the write data for the endpoint 0 is described as EPIR00 to EPIR05 (EPIR endpoint number in write order) to make the explanation understood easier. Write should start at EPIR00.
Bit Bit Name Initial Value R/W 7 D7 Undefined W 6 D6 Undefined W 5 D5 Undefined W 4 D4 Undefined W 3 D3 Undefined W 2 D2 Undefined W 1 D1 Undefined W 0 D0 Undefined W
* EPIR00
Bit 7 to 4 Bit Name D7 to D4 Initial Value Undefined R/W W Description Endpoint Number [Enable setting range] 0 to 3 3, 2 D3, D2 Undefined W Endpoint Configuration Number [Enable setting range] 0 or 1 1, 0 D1, D0 Undefined W Endpoint Interface Number [Enable setting range] 0 to 3
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Section 19 USB Function Module (USB)
* EPIR01
Bit 7, 6 Bit Name D7, D6 Initial Value Undefined R/W W Description Endpoint Alternate Number [Possible setting range] 0 or 1 5, 4 D5, D4 Undefined W Endpoint Transmission [Possible setting range] 0: Control 1: Setting prohibited 2: Bulk 3: Interrupt 3 D3 Undefined W Endpoint Transmission Direction [Possible setting range] 0: Out 1: In 2 to 0 D2 to D0 Undefined W Reserved [Possible setting range] Fixed to 0.
* EPIR02
Bit 7 to 1 Bit Name D7 to D1 Initial Value Undefined R/W W Description Endpoint Maximum Packet Size [Possible setting range] 0 to 64 0 D0 Undefined W Reserved [Possible setting range] Fixed to 0.
* EPIR03
Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W W Description Reserved [Possible setting range] Fixed to 0.
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Section 19 USB Function Module (USB)
* EPIR04
Bit 7 to 0 Bit Name D7 to D0 Initial Value Undefined R/W W Description Endpoint FIFO Number [Possible setting range] 0 to 3
The endpoint number is the endpoint number the USB host uses. The endpoint FIFO number corresponds to the endpoint number described in this manual. Thus data transfer between the USB host and the endpoint FIFO can be enabled by putting the endpoint number and the endpoint FIFO number in one-to-one correspondence. Note that the setting value is subject to a limitation described below. Since each endpoint FIFO number is optimized by the exclusive software that corresponds to the transfer system, direction, and the maximum packet size, make sure to set the endpoint FIFO number to the data described in table 19.2. 1. The endpoint FIFO number 1 cannot designate other than the maximum packet size of 64 bytes, bulk transfer method, and out transfer direction. 2. endpoint number 0 and the endpoint FIFO number must have one-on one relationship. 3. The maximum packet size for the endpoint FIFO number 0 is 8 bytes only. 4. The endpoint FIFO number 0 can specify only the maximum packet size and the data for the rest should be all 0. 5. The maximum packet size for the endpoint FIFO numbers 1 and 2 is limited to 64 bytes. 6. The maximum packet size for the endpoint FIFO numbers 3 is limited to 8 bytes. 7. The maximum number of endpoint information setting is ten. 8. Up to ten endpoint information setting should be made. 9. Write 0 to the endpoints not in use. Table 19.2 shows the example of limitations for the maximum packet size, the transfer method, and the transfer direction. Table 19.2 Example of Limitations for Setting Values
Endpoint FIFO Number 0 1 2 3 Maximum Packet Size 8 bytes 64 bytes 64 bytes 8 bytes Transfer Method Control Bulk Bulk Interrupt Transfer Direction Out In In
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Section 19 USB Function Module (USB)
Table 19.3 shows a specific example of setting. Table 19.3 Example of Setting
Endpoint Number Conf. 0 1 2 3 N 0 1 2 3 4 5 6 7 8 9 1 1 1 1 1 Int. 0 0 0 1 1 Alt. 0 0 0 0 1 Transfer Method Control Bulk Bulk Interrupt Transfer Direction In/Out Out In In EPIR[N]2 10 80 80 10 00 00 00 00 00 00 Maximum Packet Size 8 bytes 64 bytes 64 bytes 8 bytes EPIR[N]3 00 00 00 00 00 00 00 00 00 00 Endpoint FIFO Number 0 1 2 3 EPIR[N]4 00 01 02 03 00 00 00 00 00 00
EPIR[N]0 00 14 24 34 00 00 00 00 00 00
EPIR[N]1 00 20 28 38 00 00 00 00 00 00
Configuration 1
Interface 0
Alternate Setting 0
Endpoint Number 0 1 2 3
Endpoint FIFO Number 0 1 2 3
Attribute Control BulkOut BulkIn InterruptIn
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Section 19 USB Function Module (USB)
19.3.26
Transceiver Test Register 0 (TRNTREG0)
TRNTREG0 controls the on-chip transceiver output signals. Setting the PTSTE bit to 1 specifies the transceiver output signals (USD+ and USD-) arbitrarily. Table 19.4 shows the relationship between TRNTREG0 setting and pin output.
Bit Bit Name Initial Value R/W 7 PTSTE 0 R/W 6 0 R 5 0 R 4 0 R 3 SUSPEND 0 R/W 2 txenl 0 R/W 1 txse0 0 R/W 0 txdata 0 R/W
Bit 7
Bit Name PTSTE
Initial Value 0
R/W R/W
Description Pin Test Enable Enables the test control for the on-chip transceiver output pins (USD+ and USD-).
6 to 4
All 0
R
Reserved These bits are always read as 0. The write value should always be 0.
3 2 1 0
SUSPEND txenl txse0 txdata
0 0 0 0
R/W R/W R/W R/W
On-Chip Transceiver Output Signal Setting SUSPEND: Sets the (SUSPEND) signal of the on-chip transceiver. txenl: txse0: txdata: Sets the output enable (txenl) signal of the on-chip transceiver. Sets the Signal-ended 0 (txse0) signal of the on-chip transceiver. Sets the (txdata) signal of the on-chip transceiver.
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Section 19 USB Function Module (USB)
Table 19.4 Relationship between TRNTREG0 Setting and Pin Output
Pin Input VBUS 0 1 1 1 1 1 PTSTE X 0 1 1 1 1 Register Setting txenl X X 0 0 0 1 txse0 X X 0 0 1 X txdata X X 0 1 x X USD+ Hi-Z 0 1 0 Hi-Z Pin Output USDHi-Z 1 0 0 Hi-Z
[Legend] X: Don't care. : Cannot be controlled. Indicates state in normal operation according to the USB operation and port settings.
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Section 19 USB Function Module (USB)
19.3.27 Transceiver Test Register 1 (TRNTREG1) TRNTREG1 is a test register that can monitor the on-chip transceiver input signal. Setting bits PTSTE and txenl in TRNTREG0 to 1 enables monitoring the on-chip transceiver input signal. Table 19.5 shows the relationship between pin input and TRNTREG1 monitoring value.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 xver_data * R 1 dpls * R 0 dmns * R
Bit 7 to 3
Bit Name
Initial Value All 0
R/W R
Description Reserved These bits are always read as 0. The write value should always be 0.
2 1 0
xver_data dpls dmns
* * *
R R R
On-Chip Transceiver Input Signal Monitor xver_data: Monitors the differential input level (xver_data) signal of the on-chip transceiver. dpls: dmns: Monitors the USD+ (dpls) signal of the onchip transceiver. Monitors the USD- (dmns) signal of the onchip transceiver.
Note:
*
Determined by the state of pins, VBUS, USD+, and USD-
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Section 19 USB Function Module (USB)
Table 19.5 Relationship between Pin Input and TRNTREG1 Monitoring Value
Register Setting Pin Input TRNTREG1 Monitoring Value
PTSTE
SUSPEND
VBUS
USD+
USD-
xver_data dpls 0 X 0 1 X 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1
dmns Remarks 0 0 1 0 1 0 1 0 1 1
Can be monitored when VBUS = 0 Cannot be monitored when PTSTE = 0 Can be monitored when PTSTE = 1
0 1 1 1 1 1 1 1 1 1
X 0 0 0 0 1 1 1 1 X
X 1 1 1 1 1 1 1 1 0
X 0 0 1 1 0 0 1 1 X
X 0 1 0 1 0 1 0 1 X
[Legend] X: Don't care.
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Section 19 USB Function Module (USB)
19.4
Interrupt Sources
This module has five interrupt signals. Table 19.6 shows the interrupt sources and their corresponding interrupt request signals. The USBINTN interrupt signals are activated at low level. The USBINTN interrupt requests can only be detected at low level (specified as level sensitive). Table 19.6 Interrupt Sources
Transfer Mode Control transfer (EP0) Interrupt Source EP0i_TS* EP0i_TR* EP0o_TS* SETUP_TS* Bulk_in transfer (EP2) EP2_EMPTY Interrupt Request Signal DTC Activation DMAC Activation x x x x USBINTN1
Register IFR0
Bit 0 1 2 3 4
Description EP0i transfer complete EP0i transfer request EP0o receive complete Setup command receive complete EP2 FIFO empty
USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 -- -- x --
5 6 Bulk_out transfer (EP1) Status Status
EP2_TR EP1_FULL
EP2 transfer request EP1 FIFO Full
x USBINTN0
7 IFR1 0
BRST VBUSF
Bus reset USB disconnection detection EP3 transfer complete EP3 transfer request VBUS connection status --
x x
1 2 3 4 5 6 7
Interrupt_in EP3_TS transfer (EP3) EP3_TR Status -- VBUSMN Reserved
x x x --
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Section 19 USB Function Module (USB) Interrupt Request Signal
Register IFR2
Bit 0 1 2 3 4
Transfer Mode Status
Interrupt Source SETI SETC
Description Set_Interface command detection Set_Configuration command detection Endpoint information load end Suspend/resume detection
DMAC DTC Activation Activation x x -- x x
USBINTN2 or x USBINTN3 USBINTN2 or x USBINTN3 -- --
-- Status
Reserved CFDN SURSF
USBINTN2 or x USBINTN3 x USBINTN2, USBINTN3, or RESUME -- -- x --
5 6 7 --
SURSS Reserved
Suspend/resume status --
x --
Note:
*
EP0 interrupts must be assigned to the same interrupt request signal.
* USBINTN0 signal DMAC start interrupt signal only EP1. See section 19.8, DMA Transfer. * USBINTN1 signal DMAC start interrupt signal only EP2. See section 19.8, DMA Transfer. * USBINTN2 signal The USBINTN2 signal requests interrupt sources for which the corresponding bits in interrupt select registers 0 to 2 (ISR0 to ISR2) are cleared to 0. The USBINTN2 is driven low if a corresponding bit in the interrupt flag register is set to 1. * USBINTN3 signal The USBINTN3 signal requests interrupt sources for which the corresponding bits in interrupt select registers 0 to 2 (ISR0 to ISR2) are cleared to 0. The USBINTN3 is driven low if a corresponding bit in the interrupt flag register is set to 1. * RESUME signal The RESUME signal is a resume interrupt signal for canceling software standby mode and deep software standby mode. The RESUME signal is driven low at the transition to the resume state for canceling software standby mode and deep software standby mode.
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Section 19 USB Function Module (USB)
19.5
19.5.1
Operation
Cable Connection
USB function Cable disconnected VBUS pin = 0 V UDC core reset
Application USB module interrupt setting As soon as preparations are completed, enable D+ pull-up in general output port Initial settings
USB cable connection
No
General output port D+ pull-up enabled? Yes Interrupt request IFR1.VBUSF = 1 USB bus connection interrupt Clear VBUSF flag (IFR1.VBUSF)
UDC core reset release
Firmware preparations for start of USB communication
Bus reset reception IFR0.BRST = 1 Bus reset interrupt
Interrupt request
Clear bus reset flag (IFR0.BRST)
Wait for setup command reception complete interrupt
Clear FIFOs (EP0, EP1, EP2, EP3)
Wait for setup command reception complete interrupt
Figure 19.2 Cable Connection Operation The above flowchart shows the operation in the case of in section 19.9, Example of USB External Circuitry. In applications that do not require USB cable connection to be detected, processing by the USB bus connection interrupt is not necessary. Preparations should be made with the bus-reset interrupt.
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Section 19 USB Function Module (USB)
19.5.2
Cable Disconnection
USB function Cable connected VBUS pin = 1
Application
USB cable disconnection
VBUS pin = 0
UDC core reset
End
Figure 19.3 Cable Disconnection Operation The above flowchart shows the operation in section 19.9, Example of USB External Circuitry. 19.5.3 (1) Suspend and Resume Operations
Suspend Operation
If the USB bus enters the suspend state from the non-suspend state, perform the operation as shown in figure 19.4.
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Section 19 USB Function Module (USB)
USB function USB cable connected
Application Clear SURSF in IFR2 to 0
Bus idle of 3 ms or more occurs
Check if SURSS in IFR2 is set to 1
Suspend/resume interrupt occurs (IFR2/SURSF = 1)
RESUME
Remote wakeup enabled? (CTLR/RWUPS = 1?)
No
Yes Check remote-wakeup function enabled Check remote-wakeup function disabled
System needs to enter power-down mode? Yes
No
Need to enter software standby mode? Yes Need to enter deep software standby mode? Yes Clear SURSE in IER2 to 0
No
No
1 Set STS5 to STS0 in SBYCR 2 Set SSRSME in IER2 to 0 Clear SURSE in IER2 to 0 Set SURSE in IER2 to 1
Clear RAMCUT in DPSTBYCR to 0
Set SSRSME in IER2 to 1
Clear SSRSME in IER2 to 0
Set WTSTS5 to WTSTS0 1 in DPSBWCR
Clear DUSBIF in DPSIFR to 0 Set DUSBIE in DPSIER to 1
Enter deep software standby mode
Enter software standby mode
USB module stop
Wait for suspend/ resume interrupt Notes: 1. For details, see section 27, Power-Down Modes. 2. When the USB enters deep software standby mode, the sources to cancel software standby mode may be conflicted. In this figure, the operation to cancel software standby mode is not performed. For details, see section 27.12, Usage Notes.
Figure 19.4 Suspend Operation
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Section 19 USB Function Module (USB)
(2)
Resume Operation from Up-Stream
If the USB bus enters the non-suspend state from the suspend state by resume signal output from up-stream, perform the operation as shown in figure 19.5.
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Section 19 USB Function Module (USB)
USB function USB cable connected USB bus in suspend state
Application
Resume interrupts is requested from the up-stream. Suspend/resume interrupt occurs. (IFR2/SURSF = 1)
RESUME
Yes
Deep software standby mode ? No
Yes
Software standby mode ? No
Cancel deep software standby mode
Cancel software standby mode
Oscillation stabilization time has passed?
No
Oscillation stabilization time has passed?
No
Yes Execute reset exception handling
Yes
*
USB module stopped? Yes
No
Start USB operating clock oscillation
Cancel USB module stop Cancel USB module stop
Clear SURSF in IFR2 to 0
Clear SURSF in IFR2 to 0
Check if SURSS in IFR2 is cleared to 0
Check if SURSS in IFR2 is cleared to 0
Set SURSE in IER2 to 1
Set SURSE in IER2 to 1
Clear SSRSME in IER2 to 0
Clear SSRSME in IER2 to 0
Clear DUSBIF in DPSIFR to 0
Clear DUSBIE in DPSIER to 0
USB communications can be resumed Note: * For details, see section 27.8, Deep Software Standby Mode.
Return to normal state
Figure 19.5 Resume Operation from Up-Stream
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Section 19 USB Function Module (USB)
(3)
Transition from Suspend State to Software Standby Mode and Canceling Software Standby Mode
If the USB bus enters from the suspend state to software standby mode, perform the operation as shown in figure 19.6. When canceling software standby mode, ensure enough time for the system clock oscillation to be settled.
Transition from suspend state to software standby mode (1) Detect that USB bus is in suspend state (8) Canceling software standby mode
Detect that USB bus is in resume state
(2)
Set SURSF in IFR2 to 1
(9)
RESUME interrupt
(3)
USBINTN interrupt
(10)
Cancel software standby mode Wait for system clock oscillation to be settled
(4)
Clear SURSF in IFR2 to 0 Check if SURSS in IFR2 is set to 1 (11) Clear SURSE in IER2 to 0 Set SSRSME in IER2 to 1 (12) Shift to software standby mode (execute SLEEP instruction)
Clear SURSF in IFR2 to 0 Check if SURSS in IFR2 is cleared to 0
(5)
Set SURSE in IER2 to 1 Clear SSRSME in IER2 to 0
(6)
USB communications can be resumed through USB registers
(7)
Stop all clocks of LSI
Denotation of figures : Operation by firmware setting : Automatic operation by LSI hardware
Figure 19.6 Flow of Transition to and Canceling Software Standby Mode
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Section 19 USB Function Module (USB)
(1) USB bus state Normal (3) USBINTN interrupt Suspend
(8) Resume normal
SURSF
(2)
(4)
(11)
SURSS
(4)
(11)
SSRSME = 1
(5)
(12)
RESUME interrupt
(9)
Software standby
(6)
(10)
Oscillator USB dedicated clock (cku) Module clock (p)
(7)
(7)
Software standby
Oscillation settling time
Figure 19.7 Timing of Transition to and Canceling Software Standby Mode
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Section 19 USB Function Module (USB)
(4)
Transition from Suspend State to Deep Software Standby Mode and Canceling Deep Software Standby Mode
If the USB bus enters from the suspend state to deep software standby mode, perform the operation as shown in figure 19.8. When canceling deep software standby mode, ensure enough time for the system clock oscillation to be settled.
Transition from suspend state to deep software standby mode (1) Detect that USB bus is in suspend state (8) Canceling deep software standby mode
Detect that USB bus is in resume state
(2)
Set SURSF in IFR2 to 1
(9)
RESUME interrupt
(3)
USBINTN interrupt
Cancel deep software standby mode (10) Wait for system clock oscillation to be settled (11)
(4)
Clear SURSF in IFR2 to 0 Check if SURSS in IFR2 is set to 1
Execute reset sequence
(5)
Clear SURSE in IER2 to 0 Clear SSRSME in IER2 to 0* Clear DUSBIF in DPSIFR to 0 Set DUSBIE in DPSIER to 1
(12)
Cancel module stop
(13) (6) Shift to deep software standby mode (execute SLEEP instruction)
Clear SURSF in IFR2 to 0 Check if SURSS in IFR2 is cleared to 0
(7)
Stop all clocks of LSI
(14)
Set SURSE in IER2 to 1 Set SSRSME in IER2 to 0 Clear DUSBIF in DPSIFR to 0 Clear DUSBIE in DPSIER to 0
USB communications can be resumed through USB registers
Denotation of figures : Operation by firmware setting : Automatic operation by LSI hardware Note: * When the USB enters deep software standby mode, the sources to cancel software standby mode may be conflicted. In this figure, the operation to cancel software standby mode is not performed. For details, see section 27.12, Usage Notes.
Figure 19.8 Flow of Transition to and Canceling Deep Software Standby Mode
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Section 19 USB Function Module (USB)
(1) Normal USB bus state Suspend
(8) Resume normal
USBINTN interrupt (3)
SURSF
(2)
(4)
(13)
(4) SURSS (13)
DUSBIF
(5)
(14)
(5) DUSBIE RESUME interrupt (9)
(14)
Deep software standby
(6)
(10)
(7) Oscillator
(7) USB dedicated clock (cku)
Internal reset
(11)
USB module stop (MSTPC11)
(6)
(12)
Module clock (p)
(7) Deep software standby Oscillation Module stop settling period time
Figure 19.9 Timing of Transition to and Canceling Deep Software Standby Mode
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Section 19 USB Function Module (USB)
(5)
Remote-Wakeup Operation
If the USB bus enters the non-suspend (resume) state from the suspend state by the remotewakeup signal output from this function, perform the operation as shown in figure 19.10.
USB function USB cable connected USB bus in suspend state
Application
Remote wakeup enabled? (CTLR/RWUPS = 1?)
No
Yes Bus wakeup source generated Wait for resume from up-stream
Yes Cancel software standby mode
Software standby mode ? No
Oscillation stabilization time has passed?
No
Yes
USB module stopped? Yes Start USB operating clock oscillation Resume output signal Suspend/resume interrupt occurs. (IFR2/SURSF = 1) Cancel USB module stop
No
Remote wakeup execution (CTLR/RSME= 1) RESUME Clear SURSF in IFR2 to 0
Check if SURSS in IFR2 is cleared to 0
Return to normal state
Figure 19.10 Remote-Wakeup
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Section 19 USB Function Module (USB)
19.5.4
Control Transfer
Control transfer consists of three stages: setup, data (not always included), and status (figure 19.11). The data stage comprises a number of bus transactions. Operation flowcharts for each stage are shown below.
Setup stage Control-in SETUP(0)
DATA0
Data stage IN(1)
DATA1
Status stage ... IN(0/1)
DATA0/1
IN(0)
DATA0
OUT(1)
DATA1
Control-out
SETUP(0)
DATA0
OUT(1)
DATA1
OUT(0)
DATA0
...
OUT(0/1)
DATA0/1
IN(1)
DATA1
No data
SETUP(0)
DATA0
IN(1)
DATA1
Figure 19.11 Transfer Stages in Control Transfer
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Section 19 USB Function Module (USB)
(1)
Setup Stage
USB function SETUP token reception
Application
Receive 8-byte command data in EP0s
Command to be processed by application? Yes Set setup command reception complete flag (IFR0.SETUP TS = 1)
No
Automatic processing by this module
Interrupt request
Clear SETUP TS flag (IFR0.SETUP TS = 0) Clear EP0i FIFO (FCLR.EP0iCLR = 1) Clear EP0o FIFO (FCLR.EP0oCLR = 1)
To data stage
Read 8-byte data from EP0s
Decode command data Determine data stage direction*1
Write 1 to EP0s read complete bit (TRG.EP0s RDFN = 1) *2 To control-in data stage To control-out data stage
Notes: 1. In the setup stage, the application analyzes command data from the host requiring processing by the application, and determines the subsequent processing (for example, data stage direction, etc.). 2. When the transfer direction is control-out, the EP0i transfer request interrupt required in the status stage should be enabled here. When the transfer direction is control-in, this interrupt is not required and should be disabled.
Figure 19.12 Setup Stage Operation
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Section 19 USB Function Module (USB)
(2)
Data Stage (Control-In)
USB function IN token reception
Application From setup stage
1 written to TRG.EP0s RDFN? Yes Valid data in EP0i FIFO? Yes Data transmission to host ACK Set EP0i transmission complete flag (IFR0.EP0i TS = 1)
No NACK
Write data to EP0i data register (EPDR0i)
No NACK
Write 1 to EP0i packet enable bit (TRG.EP0i PKTE = 1)
Interrupt request
Clear EP0i transmission complete flag (IFR0.EP0i TS = 0) Write data to EP0i data register (EPDR0i) Write 1 to EP0i packet enable bit (TRG.EP0i PKTE = 1)
Figure 19.13 Data Stage (Control-In) Operation The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is intransfer, one packet of data to be sent to the host is written to the FIFO. If there is more data to be sent, this data is written to the FIFO after the data written first has been sent to the host (EP0iTS bit in IFR0 = 1). The end of the data stage is identified when the host transmits an OUT token and the status stage is entered. Note: If the size of the data transmitted by the function is smaller than the data size requested by the host, the function indicates the end of the data stage by returning to the host a packet shorter than the maximum packet size. If the size of the data transmitted by the function is an integral multiple of the maximum packet size, the function indicates the end of the data stage by transmitting a zero-length packet.
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Section 19 USB Function Module (USB)
(3)
Data Stage (Control-Out)
USB function OUT token reception
Application
1 written to TRG.EP0s RDFN? Yes
No NACK
Data reception from host ACK Set EP0o reception complete flag (IFR0.EP0o TS = 1) Interrupt request Clear EP0o reception complete flag (IFR0.EP0o TS = 0) Read data from EP0o receive data size register (EPSZ0o) No NACK
OUT token reception
1 written to TRG.EP0o RDFN? Yes
Read data from EP0o data register (EPDR0o)
Write 1 to EP0o read complete bit (TRG.EP0o RDFN = 1)
Figure 19.14 Data Stage (Control-Out) Operation The application first analyzes command data from the host in the setup stage, and determines the subsequent data stage direction. If the result of command data analysis is that the data stage is outtransfer, the application waits for data from the host, and after data is received (EP0oTS bit in IFR0 = 1), reads data from the FIFO. Next, the application writes 1 to the EP0o read complete bit, empties the receive FIFO, and waits for reception of the next data. The end of the data stage is identified when the host transmits an IN token and the status stage is entered.
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Section 19 USB Function Module (USB)
(4)
Status Stage (Control-In)
USB function OUT token reception
Application
0-byte reception from host ACK Set EP0o reception complete flag (IFR0.EP0o TS = 1) Interrupt request Clear EP0o reception complete flag (IFR0.EP0o TS = 0) Write 1 to EP0o read complete bit (TRG.EP0o RDFN = 1)
End of control transfer
End of control transfer
Figure 19.15 Status Stage (Control-In) Operation The control-in status stage starts with an OUT token from the host. The application receives 0byte data from the host, and ends control transfer.
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Section 19 USB Function Module (USB)
(5)
Status Stage (Control-Out)
USB function IN token reception
Application
Valid data in EP0i FIFO? Yes 0-byte transmission to host ACK Set EP0i transmission complete flag (IFR0.EP0i TS = 1)
No NACK
Interrupt request
Clear EP0i transfer request flag (IFR0.EP0i TR = 0)
Write 1 to EP0i packet enable bit (TRG.EP0i PKTE = 1)
Interrupt request
Clear EP0i transmission complete flag (IFR0.EP0i TS = 0)
End of control transfer
End of control transfer
Figure 19.16 Status Stage (Control-Out) Operation The control-out status stage starts with an IN token from the host. When an IN-token is received at the start of the status stage, there is not yet any data in the EP0i FIFO, and so an EP0i transfer request interrupt is generated. The application recognizes from this interrupt that the status stage has started. Next, in order to transmit 0-byte data to the host, 1 is written to the EP0i packet enable bit but no data is written to the EP0i FIFO. As a result, the next IN token causes 0-byte data to be transmitted to the host, and control transfer ends. After the application has finished all processing relating to the data stage, 1 should be written to the EP0i packet enable bit.
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Section 19 USB Function Module (USB)
19.5.5
EP1 Bulk-Out Transfer (Dual FIFOs)
USB function OUT token reception
Application
Space in EP1 FIFO? Yes Data reception from host ACK Set EP1 FIFO full status (IFR0.EP1 FULL = 1)
No NACK
Read EP1 receive data size register (EPSZ1) Interrupt request
Read data from EP1 data register (EPDR1)
Write 1 to EP1 read complete bit (TRG.EP1 RDFN = 1)
Both EP1 FIFOs empty? Yes Clear EP1 FIFO full status (IFR0.EP1 FULL = 0)
No Interrupt request
Figure 19.17 EP1 Bulk-Out Transfer Operation EP1 has two 64-byte FIFOs, but the user can receive data and read receive data without being aware of this dual-FIFO configuration. When one FIFO is full after reception is completed, the EP1FULL bit in IFR0 is set. After the first receive operation into one of the FIFOs when both FIFOs are empty, the other FIFO is empty, and so the next packet can be received immediately. When both FIFOs are full, NACK is returned to the host automatically. When reading of the receive data is completed following data reception, 1 is written to the EP1RDFN bit in TRG. This operation empties the FIFO that has just been read, and makes it ready to receive the next packet.
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Section 19 USB Function Module (USB)
19.5.6
EP2 Bulk-In Transfer (Dual FIFOs)
USB function IN token reception
Application
Valid data in EP2 FIFO? Yes Data transmission to host ACK
No NACK
Interrupt request
Clear EP2 transfer request flag (IFR0.EP2 TR = 0)
Enable EP2 FIFO empty interrupt (IER0.EP2 EMPTY = 1)
Space in EP2 FIFO? No
Yes
Set EP2 empty status (IFR0.EP2 EMPTY = 1)
Interrupt request
IFR0.EP2 EMPTY interrupt
Clear EP2 empty status (IFR0.EP2 EMPTY = 0)
Write one packet of data to EP2 data register (EPDR2)
Write 1 to EP2 packet enable bit (TRG.EP2 PKTE = 1)
Figure 19.18 EP2 Bulk-In Transfer Operation EP2 has two 64-byte FIFOs, but the user can transmit data and write transmit data without being aware of this dual-FIFO configuration. However, one data write is performed for one FIFO. For example, even if both FIFOs are empty, it is not possible to perform EP2PKTE at one time after consecutively writing 128 bytes of data. EP2PKTE must be performed for each 64-byte write. When performing bulk-in transfer, as there is no valid data in the FIFOs on reception of the first IN token, an EP2TR bit interrupt in IFR0 is requested. With this interrupt, 1 is written to the EP2EMPTY bit in IER0, and the EP2 FIFO empty interrupt is enabled. At first, both EP2 FIFOs are empty, and so an EP2 FIFO empty interrupt is generated immediately.
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Section 19 USB Function Module (USB)
The data to be transmitted is written to the data register using this interrupt. After the first transmit data write for one FIFO, the other FIFO is empty, and so the next transmit data can be written to the other FIFO immediately. When both FIFOs are full, EP2 EMPTY is cleared to 0. If at least one FIFO is empty, the EP2EMPTY bit in IFR0 is set to 1. When ACK is returned from the host after data transmission is completed, the FIFO used in the data transmission becomes empty. If the other FIFO contains valid transmit data at this time, transmission can be continued. When transmission of all data has been completed, write 0 to the EP2EMPTY bit in IER0 and disable interrupt requests.
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Section 19 USB Function Module (USB)
19.5.7
EP3 Interrupt-In Transfer
USB function
Application
Is there data for transmission to host? IN token reception Yes Write data to EP3 data register (EPDR3) Valid data in EP3FIFO? Yes Data transmission to host ACK Set EP3 transmission complete flag (IFR1.EP3 TS = 1) Interrupt request Clear EP3 transmission complete flag (IFR1.EP3 TS = 0) No NACK Write 1 to EP3 packet enable bit (TRG.EP3 PKTE = 1)
No
Is there data for transmission to host? Yes Write data to EP3 data register (EPDR3) Write 1 to EP3 packet enable bit (TRG.EP3 PKTE = 1)
No
Note: This flowchart shows just one example of interrupt transfer processing. Other possibilities include an operation flow in which, if there is data to be transferred, the EP3 DE bit in the data status register is referenced to confirm that the FIFO is empty, and then data is written to the FIFO.
Figure 19.19 Operation of EP3 Interrupt-In Transfer
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Section 19 USB Function Module (USB)
19.6
Processing of USB Standard Commands and Class/Vendor Commands
Processing of Commands Transmitted by Control Transfer
19.6.1
A command transmitted from the host by control transfer may require decoding and execution of command processing on the application side. Whether command decoding is required on the application side is indicated in table 19.7 below. Table 19.7 Command Decoding on Application Side
Decoding not Necessary on Application Side Clear Feature Get Configuration Get Interface Get Status Set Address Set Configuration Set Feature Set Interface Decoding Necessary on Application Side Get Descriptor Class/Vendor command Set Descriptor Sync Frame
If decoding is not necessary on the application side, command decoding and data stage and status stage processing are performed automatically. No processing is necessary by the user. An interrupt is not generated in this case. If decoding is necessary on the application side, this module stores the command in the EP0s FIFO. After reception is completed successfully, the IFR0/SETUP TS flag is set and an interrupt request is generated. In the interrupt routine, eight bytes of data must be read from the EP0s data register (EPDR0s) and decoded by firmware. The necessary data stage and status stage processing should then be carried out according to the result of the decoding operation.
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Section 19 USB Function Module (USB)
19.7
19.7.1
Stall Operations
Overview
This section describes stall operations in this module. There are two cases in which the USB function module stall function is used: * When the application forcibly stalls an endpoint for some reason * When a stall is performed automatically within the USB function module due to a USB specification violation The USB function module has internal status bits that hold the status (stall or non-stall) of each endpoint. When a transaction is sent from the host, the module references these internal status bits and determines whether to return a stall to the host. These bits cannot be cleared by the application; they must be cleared with a Clear Feature command from the host. However, the internal status bit for EP0 is automatically cleared only when the setup command is received. 19.7.2 Forcible Stall by Application
The application uses the EPSTL register to issue a stall request for the USB function module. When the application wishes to stall a specific endpoint, it sets the corresponding bit in EPSTL (11 in figure 19.20). The internal status bits are not changed at this time. When a transaction is sent from the host for the endpoint for which the EPSTL bit was set, the USB function module references the internal status bit, and if this is not set, references the corresponding bit in EPSTL (1-2 in figure 19.20). If the corresponding bit in EPSTL is set, the USB function module sets the internal status bit and returns a stall handshake to the host (1-3 in figure 19.20). If the corresponding bit in EPSTL is not set, the internal status bit is not changed and the transaction is accepted. Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to the EPSTL register. Even after a bit is cleared by the Clear Feature command (3-1 in figure 19.20), the USB function module continues to return a stall handshake while the bit in EPSTL is set, since the internal status bit is set each time a transaction is executed for the corresponding endpoint (1-2 in figure 19.20). To clear a stall, therefore, it is necessary for the corresponding bit in EPSTL to be cleared by the application, and also for the internal status bit to be cleared with a Clear Feature command (2-1, 2-2, and 2-3 in figure 19.20).
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Section 19 USB Function Module (USB)
(1) Transition from normal operation to stall (1-1) USB Internal status bit 0 EPSTL 01 1. 1 written to EPSTL by application
(1-2) Reference Transaction request Internal status bit 0 EPSTL 1 1. IN/OUT token received from host 2. EPSTL referenced
(1-3) Stall STALL handshake Internal status bit 01 To (2-1) or (3-1) (2) When Clear Feature is sent after EPSTL is cleared (2-1) Transaction request Internal status bit 1 EPSTL 10 EPSTL 1
1. 1 set in EPSTL 2. Internal status bit set to 1 3. Transmission of STALL handshake
1. EPSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. EPSTL not referenced 5. Internal status bit not changed
(2-2) STALL handshake Internal status bit 1 EPSTL 0 1. Transmission of STALL handshake
(2-3) Clear Feature command Internal status bit 10 EPSTL 0 1. Internal status bit cleared to 0
Normal status restored (3) When Clear Feature is sent before EPSTL is cleared to 0 (3-1) Clear Feature command Internal status bit 10 To (1-2) EPSTL 1 1. Internal status bit cleared to 0 2. EPSTL not changed
Figure 19.20 Forcible Stall by Application
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Section 19 USB Function Module (USB)
19.7.3
Automatic Stall by USB Function Module
When a stall setting is made with the Set Feature command, or in the event of a USB specification violation, the USB function module automatically sets the internal status bit for the relevant endpoint without regard to the EPSTL register, and returns a stall handshake (1-1 in figure 19.21). Once an internal status bit is set, it remains set until cleared by a Clear Feature command from the host, without regard to the EPSTL register. After a bit is cleared by the Clear Feature command, EPSTL is referenced (3-1 in figure 19.21). The USB function module continues to return a stall handshake while the internal status bit is set, since the internal status bit is set even if a transaction is executed for the corresponding endpoint (2-1 and 2-2 in figure 19.21). To clear a stall, therefore, the internal status bit must be cleared with a Clear Feature command (3-1 in figure 19.21). If set by the application, EPSTL should also be cleared (2-1 in figure 19.21).
(1) Transition from normal operation to stall (1-1) STALL handshake Internal status bit 01 To (2-1) or (3-1) EPSTL 0 1. In case of USB specification violation, etc., USB function module stalls endpoint automatically
(2) When transaction is performed when internal status bit is set, and Clear Feature is sent (2-1) Transaction request Internal status bit 1 EPSTL 0 1. EPSTL cleared to 0 by application 2. IN/OUT token received from host 3. Internal status bit already set to 1 4. EPSTL not referenced 5. Internal status bit not changed 1. Transmission of STALL handshake
(2-2) STALL handshake Internal status bit 1 EPSTL 0
Stall status maintained (3) When Clear Feature is sent before transaction is performed (3-1) Clear Feature command Internal status bit 10 EPSTL 0 1. Internal status bit cleared to 0 2. EPSTL not changed
Normal status restored
Figure 19.21 Automatic Stall by USB Function Module
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Section 19 USB Function Module (USB)
19.8
19.8.1
DMA Transfer
Overview
DMA transfer can be performed for endpoints 1 and 2 in this module. Note that word or longword data cannot be transferred. When endpoint 1 holds at least one byte of valid receive data, a DMA request for endpoint 1 is generated. When endpoint 2 holds no valid data, a DMA request for endpoint 2 is generated. If the DMA transfer is enabled by setting the EP1DMAE bit in the DMA transfer setting register to 1, zero-length data reception at endpoint 1 is ignored. When the DMA transfer is enabled, the RDFN bit for EP1 and PKTE bit for EP2 do not need to be set to 1 in TRG (note that the PKTE bit must be set to 1 when the transfer data is less than the maximum number of bytes). When all the data received at EP1 is read, the FIFO automatically enters the EMPTY state. When the maximum number of bytes (64 bytes) are written to the EP2 FIFO, the FIFO automatically enters the FULL state, and the data in the FIFO can be transmitted (see figures 19.22 and 19.23). 19.8.2 DMA Transfer for Endpoint 1
When the data received at EP1 is transferred by the DMA, the USB function module automatically performs the same processing as writing 1 to the RDFN bit in TRG if the currently selected FIFO becomes empty. Accordingly, in DMA transfer, do not write 1 to the RDFN bit for EP1 in TRG. If the user writes 1 to the RDFN bit in DMA transfer, correct operation cannot be guaranteed. Figure 19.22 shows an example of receiving 150 bytes of data from the host. In this case, internal processing which is the same as writing 1 to the RDFN bit in TRG is automatically performed three times. This internal processing is performed when the currently selected data FIFO becomes empty. Accordingly, this processing is automatically performed both when 64-byte data is sent and when data less than 64 bytes is sent.
64 bytes
64 bytes
22 bytes
RDFN (Automatically performed)
RDFN RDFN (Automatically (Automatically performed) performed)
Figure 19.22 RDFN Bit Operation for EP1
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Section 19 USB Function Module (USB)
19.8.3
DMA Transfer for Endpoint 2
When the transmit data at EP2 is transferred by the DMA, the USB function module automatically performs the same processing as writing 1 to the PKTE bit in TRG if the currently selected FIFO (64 bytes) becomes full. Accordingly, to transfer data of a multiple of 64 bytes, the user need not write 1 to the PKTE bit in TRG. To transfer data of less than 64 bytes, the user must write 1 to the PKTE bit using the DMA transfer end interrupt of the on-chip DMAC. If the user writes 1 to the PKTE bit when the maximum number of bytes (64 bytes) are transferred, correct operation cannot be guaranteed. Figure 19.23 shows an example for transmitting 150 bytes of data to the host. In this case, internal processing which is the same as writing 1 to the PKTE bit in TRG is automatically performed twice. This internal processing is performed when the currently selected data FIFO becomes full. Accordingly, this processing is automatically performed only when 64-byte data is sent. When the last 22 bytes are sent, the internal processing for writing 1 to the PKTE bit in TRG is not performed, and the user must write 1 to the PKTE bit by software. In this case, the application has no more data to transfer but the USB function module continues to output DMA requests for EP2 as long as the FIFO has an empty space. When all data has been transferred, write 0 to the EP2DMAE bit in DMAR to cancel DMA requests for EP2.
64 bytes
64 bytes
22 bytes
PKTE (Automatically performed)
PKTE is PKTE (Automatically not performed performed) Execute by DMA transfer end interrupt (user)
Figure 19.23 PKTE Bit Operation for EP2
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Section 19 USB Function Module (USB)
19.9
Example of USB External Circuitry
1. USB Transceiver This module supports the on-chip transceiver only, not the external transceiver. 2. D+ Pull-Up Control The general output port (PM4) is used for D+ pull-up control pin. The PM4 pin is driven high by the PULLUP_E bit of DMA when the USB cable VBUS is connected. Thus, USB host/hub connection notification (D+ pull-up) is enabled. 3. Detection of USB Cable Connection/Disconnection As USB states, etc., are managed by hardware in this module, a VBUS signal that recognizes connection/disconnection is necessary. The power supply signal (VBUS) in the USB cable is used for this purpose. However, if the cable is connected to the USB host/hub when the function (system installing this LSI) power is off, a voltage (5 V) will be applied from the USB host/hub. Therefore, an IC (such as an HD74LV1G08A or 2G08A) that allows voltage application when the system power is off should be connected externally.
USB Vcc PULLUP_E
On-chip transceiver Vcc (3.3 V) DrVcc (3.3 V)
PM4
VBUS*3
USD+
USD-
DrVss
Vss
Vcc (3.3 V) Regulator*1 Vcc
*2 External pull-up control circuit supporting full-speed Notes:
1.5 k
VBUS (5 V)
D+
D-
GND
USB connector
1. Reduce voltage to the operating voltage (Vcc) of this LSI (3.3 V). 2. To protect this LSI from being damaged, use the IC (such as HD74LV-A Series) which can be applied voltage even when the system power is turned off. 3. Prevent noise from the VBUS pin while the USB is performing communication.
Figure 19.24 Example of Circuitry in Bus Power Mode
Rev. 2.00 Sep. 25, 2008 Page 926 of 1340 REJ09B0413-0200
Section 19 USB Function Module (USB)
USB Vcc PULLUP_E
On-chip transceiver Vcc (3.3 V) DrVcc (3.3 V)
PM4
VBUS*2
USD+
USD-
DrVss
Vss
Vcc
3.3 V
*1 Vcc
*1 External pull-up control circuit supporting full-speed
1.5 k
VBUS (5 V)
D+
D-
GND
USB connector
Notes:
1. To protect this LSI from being damaged, use the IC (such as HD74LV-A Series) which can be applied voltage even when the system power is turned off. 2. Prevent noise from the VBUS pin while the USB is performing communication.
Figure 19.25 Example of Circuitry in Self Power Mode
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Section 19 USB Function Module (USB)
19.10
Usage Notes
19.10.1 Receiving Setup Data Note the following for EPDR0s that receives 8-byte setup data: 1. As a latest setup command must be received in high priority, the write from the USB bus takes priority over the read from the CPU. If the next setup command reception is started while the CPU is reading data after the data is received, the read from the CPU is forcibly terminated. Therefore, the data read after reception is started becomes invalid. 2. EPDR0s must always be read in 8-byte units. If the read is terminated at a midpoint, the data received at the next setup cannot be read correctly. 19.10.2 Clearing the FIFO If a USB cable is disconnected during data transfer, the data being received or transmitted may remain in the FIFO. When disconnecting a USB cable, clear the FIFO. While a FIFO is transferring data, it must not be cleared. 19.10.3 Overreading and Overwriting the Data Registers Note the following when reading or writing to a data register of this module. (1) Receive data registers
The receive data registers must not be read exceeding the valid amount of receive data, that is, the number of bytes indicated by the receive data size register. Even for EPDR1 which has double FIFO buffers, the maximum data to be read at one time is 64 bytes. After the data is read from the current valid FIFO buffer, be sure to write 1 to EP1RDFN in TRG, which switches the valid buffer, updates the receive data size to the new number of bytes, and enables the next data to be received. (2) Transmit data registers
The transmit data registers must not be written to exceeding the maximum packet size. Even for EPDR2 which has double FIFO buffers, write data within the maximum packet size at one time. After the data is written, write 1 to PKTE in TRG to switch the valid buffer and enable the next data to be written. Data must not be continuously written to the two FIFO buffers.
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Section 19 USB Function Module (USB)
19.10.4 Assigning Interrupt Sources to EP0 The EP0-related interrupt sources indicated by the interrupt source bits (bits 0 to 3) in IFR0 must be assigned to the same interrupt signal with ISR0. The other interrupt sources have no limitations. 19.10.5 Clearing the FIFO When DMA Transfer is Enabled The endpoint 1 data register (EPDR1) cannot be cleared when DMA transfer for endpoint 1 is enabled (EP1 DMAE in DMAR = 1). Cancel DMA transfer before clearing the register. 19.10.6 Notes on TR Interrupt Note the following when using the transfer request interrupt (TR interrupt) for IN transfer to EP0i, EP2, or EP3. The TR interrupt flag is set if the FIFO for the target EP has no data when the IN token is sent from the USB host. However, at the timing shown in figure 19.26, multiple TR interrupts occur successively. Take appropriate measures against malfunction in such a case. Note: This module determines whether to return NAKC if the FIFO of the target EP has no data when receiving the IN token, but the TR interrupt flag is set after a NAKC handshake is sent. If the next IN token is sent before PKTE of TRG is written to, the TR interrupt flag is set again.
TR interrupt routine CPU Clear Writes TRG. TR flag transmit data PKTE
TR interrupt routine
Host
IN token
IN token
IN token
USB
Determines whether to return NACK NACK Sets TR flag
Determines whether to return NACK NACK
Transmits data ACK
Sets TR flag (Sets the flag again)
Figure 19.26 TR Interrupt Flag Set Timing
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Section 19 USB Function Module (USB)
19.10.7 Restrictions on Peripheral Module Clock (P) Operating Frequency Specify the peripheral module clock (P) for the USB at 14 MHz or more. To set the USB dedicated clock (cku) at 48 MHz, specify the peripheral module clock (P) as shown in table 19.8. Operation cannot be guaranteed if any frequency other than in the following table is specified. Table 19.8 Selection of Peripheral Clock (P) when USB is Connected
MD_CLK 0 1 EXTAL Input Clock Frequency 12 MHz 16 MHz USB Dedicated Clock (cku: 48 MHz) EXTAL x 4 EXTAL x 3 P EXTAL x 2 (24 MHz) EXTAL x 1 (16 MHz) EXTAL x 2 (32 MHz)
19.10.8 Notes on Deep Software Standby Mode when USB is Used 1. Unlike software standby mode, deep standby software mode is canceled from the reset state. For details, see section 27.8, Deep Software Standby Mode. 2. If the RAMCUT bit is set to 1 when the USB enters deep software standby mode, the register states of the USB cannot be retained. When USB is used, set the RAMCUT bit to 1, and then, make the USB enter deep software standby mode. 3. Set the USB module stop (MSTPC11) bit to 0 after canceling deep software standby mode. 4. If the DUSBIE bit is set to 0 when the USB enters deep software standby mode, software standby mode cannot be canceled through USB RESUME interrupt. Set the DUSBIE bit to 1, and then, make the USB enter deep software standby mode.
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Section 20 I C Bus Interface 2 (IIC2)
2
Section 20 I2C Bus Interface 2 (IIC2)
This LSI has a two-channel I2C bus interface. The I2C bus interface conforms to and provides a subset of the Philips I2C bus (inter-IC bus) interface functions. The register configuration that controls the I2C bus differs partly from the Philips configuration, however. Figure 20.1 shows the block diagram of the I2C bus interface 2. Figure 20.2 shows an example of I/O pin connections to external circuits.
20.1
Features
* Continuous transmission/reception Since the shift register, transmit data register, and receive data register are independent from each other, the continuous transmission/reception can be performed. * Start and stop conditions generated automatically in master mode * Selection of acknowledge output levels when receiving * Automatic loading of acknowledge bit when transmitting * Bit synchronization/wait function In master mode, the state of SCL is monitored per bit, and the timing is synchronized automatically. If transmission or reception is not yet possible, drive the SCL signal low until preparations are completed * Six interrupt sources Transmit-data-empty (including slave-address match), transmit-end, receive-data-full (including slave-address match), arbitration lost, NACK detection, and stop condition detection * Direct bus drive Two pins, the SCL and SDA pins function as NMOS open-drain outputs. * Module stop state can be set.
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Section 20 I C Bus Interface 2 (IIC2)
2
Transfer clock generator
SCL
Output control
Transmission/ reception control circuit
ICCRA ICCRB ICMR
Noise canceler ICDRT SAR
Internal data bus
SDA
Output control
ICDRS
Noise canceler
Address comparator ICDRR Bus state decision circuit Arbitration decision circuit ICEIR Interrupt generator
ICSR
[Legend] ICCRA: ICCRB: ICMR: ICSR: ICIER: ICDRT: ICDRR: ICDRS: SAR: bus control register A I2C bus control register B I2C mode register I2C status register I2C interrupt enable register I2C transmit data register I2C receive data register I2C bus shift register Slave address register I2C
Interrupt request
Figure 20.1 Block Diagram of I2C Bus Interface 2
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Section 20 I C Bus Interface 2 (IIC2)
2
Vcc
Vcc
SCL in SCL out
SCL
SCL
SDA in SDA out
SDA
SDA
SCL SDA
(Master)
SCL in SCL out
SCL in SCL out
SDA in SDA out (Slave 1)
SDA in SDA out (Slave 2)
Figure 20.2 Connections to the External Circuit by the I/O Pins
20.2
Input/Output Pins
Table 20.1 shows the pin configuration of the I2C bus interface 2. Table 20.1 Pin Configuration of the I2C Bus Interface 2
Channel 0 Abbreviation SCL0 SDA0 1 SCL1 SDA1 I/O I/O I/O I/O I/O Function Channel 0 serial clock I/O pin Channel 0 serial data I/O pin Channel 1 serial clock I/O pin Channel 1 serial data I/O pin
Note: The pin symbols are represented as SCL and SDA; channel numbers are omitted in this manual.
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SCL SDA
Section 20 I C Bus Interface 2 (IIC2)
2
20.3
Register Descriptions
The I2C bus interface 2 has the following registers. Channel 0: * * * * * * * * * I2C bus control register A_0 (ICCRA_0) I2C bus control register B_0 (ICCRB_0) I2C bus mode register_0 (ICMR_0) I2C bus interrupt enable register_0 (ICIER_0) I2C bus status register_0 (ICSR_0) Slave address register_0 (SAR_0) I2C bus transmit data register_0 (ICDRT_0) I2C bus receive data register_0 (ICDRR_0) I2C bus shift register_0 (ICDRS_0)
Channel 1: * * * * * * * * * I2C bus control register A_1 (ICCRA_1) I2C bus control register B_1 (ICCRB_1) I2C bus mode register_1 (ICMR_1) I2C bus interrupt enable register_1 (ICIER_1) I2C bus status register_1 (ICSR_1) Slave address register_1 (SAR_1) I2C bus transmit data register_1 (ICDRT_1) I2C bus receive data register_1 (ICDRR_1) I2C bus shift register_1 (ICDRS_1)
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Section 20 I C Bus Interface 2 (IIC2)
2
20.3.1
I2C Bus Control Register A (ICCRA)
ICCRA enables or disables I2C bus interface, controls transmission or reception, and selects master or slave mode, transmission or reception, and transfer clock frequency in master mode.
Bit Bit Name Initial Value R/W 7 ICE 0 R/W 6 RCVD 0 R/W 5 MST 0 R/W 4 TRS 0 R/W 3 CKS3 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W
Bit 7
Bit Name ICE
Initial Value 0
R/W R/W
Description I C Bus Interface Enable 0: This module is halted 1: This bit is enabled for transfer operations (SCL and SDA pins are bus drive state)
2
6
RCVD
0
R/W
Reception Disable This bit enables or disables the next operation when TRS is 0 and ICDRR is read. 0: Enables next reception 1: Disables next reception
5 4
MST TRS
0 0
R/W R/W
Master/Slave Select Transmit/Receive Select When arbitration is lost in master mode, MST and TRS are both reset by hardware, causing a transition to slave receive mode. Modification of the TRS bit should be made between transfer frames. Operating modes are described below according to MST and TRS combination. 00: Slave receive mode 01: Slave transmit mode 10: Master receive mode 11: Master transmit mode
3 2 1 0
CKS3 CKS2 CKS1 CKS0
0 0 0 0
R/W R/W R/W R/W
Transfer Clock Select 3 to 0 These bits are valid only in master mode. Make setting according to the required transfer rate. For details on the transfer rate, see table 20.2.
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Section 20 I C Bus Interface 2 (IIC2)
2
Table 20.2 Transfer Rate
Bit 3 CKS3 0 Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 Clock 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 P/28 P/40 P/48 P/64 P/168 P/100 P/112 P/128 P/56 P/80 P/96 P/128 P/336 P/200 P/224 P/256 P = 8 MHz 286 kHz 200 kHz 167 kHz 125 kHz P = 10 MHz 357 kHz 250 kHz 208 kHz 156 kHz Transfer Rate P = 20 MHz 714 kHz 500 kHz 417 kHz 313 kHz P = 25 MHz 893 kHz 625 kHz 521 kHz 391 kHz 149 kHz 250 kHz 223 kHz 195 kHz 446 kHz 313 kHz 260 kHz 195 kHz 74.4 kHz 125 kHz 112 kHz 97.7 kHz P = 33 MHz 1179 kHz 825 kHz 688 kHz 516 kHz 196 kHz 330 kHz 295 kHz 258 kHz 589 kHz 413 kHz 344 kHz 258 kHz 98.2 kHz 165 kHz 147 kHz 129 kHz P = 35 MHz 1250 kHz 875 kHz 729 kHz 546 kHz 208 kHz 350 kHz 312 kHz 273 kHz 625 kHz 437 kHz 364 kHz 273 kHz 104 kHz 175 kHz 156 kHz 136 kHz
47.6 kHz 59.5 kHz 119 kHz 80.0 kHz 100 kHz 200 kHz
71.4 kHz 89.3 kHz 179 kHz 62.5 kHz 78.1 kHz 156 kHz 143 kHz 100 kHz 179 kHz 125 kHz 357 kHz 250 kHz 208 kHz
83.3 kHz 104 kHz
62.5 kHz 78.1 kHz 156 kHz 23.8 kHz 29.8 kHz 59.5 kHz 40.0 kHz 50.0 kHz 100 kHz 35.7 kHz 44.6 kHz 89.3 kHz 31.3 kHz 39.1 kHz 78.1 kHz
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Section 20 I C Bus Interface 2 (IIC2)
2
20.3.2
I2C Bus Control Register B (ICCRB)
ICCRB issues start/stop condition, manipulates the SDA pin, monitors the SCL pin, and controls reset in the I2C control module.
Bit Bit Name Initial Value R/W 7 BBSY 0 R/W 6 SCP 1 R/W 5 SDAO 1 R 4 1 R/W 3 SCLO 1 R 2 1 1 IICRST 0 R/W 0 1
Bit 7
Initial Bit Name Value BBSY 0
R/W R/W
Description Bus Busy This bit indicates whether the I C bus is occupied or released and to issue start and stop conditions in master mode. This bit is set to 1 when the SDA level changes from high to low under the condition of SCL = high, assuming that the start condition has been issued. This bit is cleared to 0 when the SDA level changes from low to high under the condition of SDA = high, assuming that the stop condition has been issued. Follow this procedure also when re-transmitting a start condition. To issue a start or stop condition, use the MOV instruction.
2
6
SCP
1
R/W
Start/Stop Condition Issue This bit controls the issuance of start or stop condition in master mode. To issue a start condition, write 1 to BBSY and 0 to SCP. A re-transmit start condition is issued in the same way. To issue a stop condition, write 0 to BBSY and 0 to SCP. This bit is always read as 1. If 1 is written, the data is not stored.
5
SDAO
1
R
This bit monitors the output level of SDA. 0: When reading, the SDA pin outputs a low level 1: When reading the SDA pin outputs a high level
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Section 20 I C Bus Interface 2 (IIC2)
2
Bit 4 3
Initial Bit Name Value SCLO 1 1
R/W R/W R
Description Reserved The write value should always be 1. This bit monitors the SCL output level. When reading and SCLO is 1, the SCL pin outputs a high level. When reading and SCLO is 0, the SCL pin outputs a low level.
2 1
IICRST
1 0
R/W
Reserved This bit is always read as 0. IIC Control Module Reset This bit reset the IIC control module except the I2C registers. If hang-up occurs because of communication failure during I2C operation, by setting this bit to 1, the I2C control module can be reset without initializing the registers.
0
1
Reserved This bit is always read as 1.
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Section 20 I C Bus Interface 2 (IIC2)
2
20.3.3
I2C Bus Mode Register (ICMR)
ICMR selects MSB first or LSB first, controls the master mode wait and selects the number of transfer bits.
Bit Bit Name Initial Value R/W 7 0 R/W 6 WAIT 0 R/W 5 1 4 1 3 BCWP 1 R/W 2 BC2 0 R/W 1 BC1 0 R/W 0 BC0 0 R/W
Bit 7 6
Bit Name WAIT
Initial Value 0 0
R/W R/W R/W
Description Reserved The write value should always be 0. Wait Insertion This bit selects whether to insert a wait after data transfer except for the acknowledge bit. When this bit is set to 1, after the falling of the clock for the last data bit, the low period is extended for two transfer clocks. When this bit is cleared to 0, data and the acknowledge bit are transferred consecutively with no waits inserted. The setting of this bit is invalid in slave mode.
5 4 3
BCWP
1 1 1
R/W
Reserved These bits are always read as 1. BC Write Protect This bit controls the modification of the BC2 to BC0 bits. When modifying, this bit should be cleared to 0 and the MOV instruction should be used. 0: When writing, the values of BC2 to BC0 are set 1: When reading, 1 is always read When writing, the settings of BC2 to BC0 are invalid.
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Section 20 I C Bus Interface 2 (IIC2)
2
Bit 2 1 0
Bit Name BC2 BC1 BC0
Initial Value 0 0 0
R/W R/W R/W R/W
Description Bit Counter 2 to 0 These bits specify the number of bits to be transferred next. The settings of these bits should be made during intervals between transfer frames. When setting these bits to a value other than 000, the setting should be made while the SCL line is low. The value return to 000 automatically at the end of a data transfer including the acknowledge bit. 000: 9 001: 2 010: 3 011: 4 100: 5 101: 6 110: 7 111: 8
20.3.4
I2C Bus Interrupt Enable Register (ICIER)
ICIER enables or disables interrupt sources and the acknowledge bits, sets the acknowledge bits to be transferred, and confirms the acknowledge bit to be received.
Bit Bit Name Initial Value R/W 7 TIE 0 R/W 6 TEIE 0 R/W 5 RIE 0 R/W 4 NAKIE 0 R/W 3 STIE 0 R/W 2 ACKE 0 R/W 1 ACKBR 0 R 0 ACKBT 0 R/W
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Section 20 I C Bus Interface 2 (IIC2)
2
Bit 7
Initial Bit Name Value TIE 0
R/W R/W
Description Transmit Interrupt Enable When the TDRE bit in ICSR is set to 1, this bit enables or disables the transmit data empty interrupt (TXI) request. 0: Transmit data empty interrupt (TXI) request is disabled 1: Transmit data empty interrupt (TXI) request is enabled
6
TEIE
0
R/W
Transmit End Interrupt Enable This bit enables or disables the transmit end interrupt (TEI) request at the rising of the ninth clock while the TDRE bit in ICSR is set to 1. The TEI request can be canceled by clearing the TEND bit or the TEIE bit to 0. 0: Transmit end interrupt (TEI) request is disabled 1: Transmit end interrupt (TEI) request is enabled
5
RIE
0
R/W
Receive Interrupt Enable This bit enables or disables the receive full interrupt (RXI) request when receive data is transferred from ICDRS to ICDRR and the RDRF bit in ICSR is set to 1. The RXI request can be canceled by clearing the RDRF or RIE bit to 0. 0: Receive data full interrupt (RXI) request is disabled 1: Receive data full interrupt (RXI) request is enabled
4
NAKIE
0
R/W
NACK Receive Interrupt Enable This bit enables or disables the NACK receive interrupt (NAKI) request when the NACKF and AL bits in ICSR are set to 1. The NAKI request can be canceled by clearing the NACKF or AL bit, or the NAKIE bit to 0. 0: NACK receive interrupt (NAKI) request is disabled 1: NACK receive interrupt (NAKI) request is enabled
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Section 20 I C Bus Interface 2 (IIC2)
2
Bit 3
Initial Bit Name Value STIE 0
R/W R/W
Description Stop Condition Detection Interrupt Enable 0: Stop condition detection interrupt (STPI) request is disabled 1: Stop condition detection interrupt (STPI) request is enabled
2
ACKE
0
R/W
Acknowledge Bit Decision Select 0: The value of the acknowledge bit is ignored and continuous transfer is performed 1: If the acknowledge bit is 1, continuous transfer is suspended
1
ACKBR
0
R
Receive Acknowledge In transmit mode, this bit stores the acknowledge data that are returned by the receive device. This bit cannot be modified. 0: Receive acknowledge = 0 1: Receive acknowledge = 1
0
ACKBT
0
R/W
Transmit Acknowledge In receive mode, this bit specifies the bit to be sent at the acknowledge timing. 0: 0 is sent at the acknowledge timing 1: 1 is sent at the acknowledge timing
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Section 20 I C Bus Interface 2 (IIC2)
2
20.3.5
I2C Bus Status Register (ICSR)
ICSR confirms the interrupt request flags and status.
Bit Bit Name Initial Value R/W 7 TDRE 0 R/W 6 TEND 0 R/W 5 RDRF 0 R/W 4 NACKF 0 R/W 3 STOP 0 R/W 2 AL 0 R/W 1 AAS 0 R/W 0 ADZ 0 R/W
Bit 7
Bit Name TDRE
Initial Value 0
R/W R/W
Description Transmit Data Register Empty [Setting condition] * * * * When data is transferred from ICDRT to ICDRS and ICDRT becomes empty When the TRS bits are set When the start (re-transmit included) condition has been issued When switched from reception to transmission in slave mode When 0 is written to this bit after reading TDRE = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When data is written to ICDRT
[Clearing conditions] *
6
TEND
0
R/W
Transmit End [Setting condition] * When the ninth clock of SCL rises while the TDRE flag is 1 When 0 is written to this bit after reading TEND = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When data is written to ICDRT
[Clearing conditions] *
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Section 20 I C Bus Interface 2 (IIC2)
2
Bit 5
Bit Name RDRF
Initial Value 0
R/W R/W
Description Receive Data Register Full [Setting condition] * When receive data is transferred from ICDRS to ICDRR When 0 is written to this bit after reading RDRF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * When data is read from ICDRR
[Clearing conditions] *
4
NACKF
0
R/W
No Acknowledge Detection Flag [Setting condition] * When no acknowledge is detected from the receive device in transmission while the ACKE bit in ICIER is set to 1 When 0 is written to this bit after reading NACKF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
[Clearing condition] *
3
STOP
0
R/W
Stop Condition Detection Flag [Setting condition] * When a stop condition is detected after frame transfer When 0 is written to this bit after reading STOP = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
[Clearing condition] *
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Section 20 I C Bus Interface 2 (IIC2)
2
Bit 2
Bit Name AL
Initial Value 0
R/W R/W
Description Arbitration Lost Flag This flag indicates that arbitration was lost in master mode. When two or more master devices attempt to seize the bus at nearly the same time, the I2C bus monitors SDA, and if the I2C bus interface detects data differing from the data it sent, it sets AL to 1 to indicate that the bus has been taken by another master. [Setting conditions] * When the internal SDA and the SDA pin level disagree at the rising of SCL in master transmit mode When the SDA pin outputs a high level in master mode while a start condition is detected When 0 is written to this bit after reading AL = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
*
[Clearing condition] *
1
AAS
0
R/W
Slave Address Recognition Flag In slave receive mode, this flag is set to 1 when the first frame following a start condition matches bits SVA6 to SVA0 in SAR. [Setting conditions] * * When the slave address is detected in slave receive mode When the general call address is detected in slave receive mode When 0 is written to this bit after reading AAS = 1
[Clearing condition] *
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Section 20 I C Bus Interface 2 (IIC2)
2
Bit 0
Bit Name ADZ
Initial Value 0
R/W R/W
Description General Call Address Recognition Flag This bit is valid in slave receive mode. [Setting condition] * When the general call address is detected in slave receive mode When 0 is written to this bit after reading ADZ = 1
[Clearing condition] *
20.3.6
Slave Address Register (SAR)
SAR is sets the slave address. In slave mode, if the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition, the LSI operates as the slave device.
Bit Bit Name Initial Value R/W 7 SVA6 0 R/W 6 SVA5 0 R/W 5 SVA4 0 R/W 4 SVA3 0 R/W 3 SVA2 0 R/W 2 SVA1 0 R/W 1 SVA0 0 R/W 0 0 R/W
Bit 7 to 1
Initial Bit Name Value SVA6 to SVA0 0
R/W R/W
Description Slave Address 6 to 0 These bits set a unique address differing from the 2 addresses of other slave devices connected to the I C bus.
0
0
R/W
Reserved Although this bit is readable/writable, only 0 should be written to.
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Section 20 I C Bus Interface 2 (IIC2)
2
20.3.7
I2C Bus Transmit Data Register (ICDRT)
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects a space in the I2C bus shift register, it transfers the transmit data which has been written to ICDRT to ICDRS and starts transmitting data. If the next data is written to ICDRT during transmitting data to ICDRS, continuous transmission is possible.
Bit Bit Name Initial Value R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 7 6 5 4 3 2 1 0
20.3.8
I2C Bus Receive Data Register (ICDRR)
ICDRR is an 8-bit read-only register that stores the receive data. When one byte of data has been received, ICDRR transfers the receive data from ICDRS to ICDRR and the next data can be received. ICDRR is a receive-only register; therefore, this register cannot be written to by the CPU.
Bit Bit Name Initial Value R/W 1 R 1 R 1 R 1 R 1 R 1 R 1 R 1 R 7 6 5 4 3 2 1 0
20.3.9
I2C Bus Shift Register (ICDRS)
ICDRS is an 8-bit write-only register that is used to transmit/receive data. In transmission, data is transferred from ICDRT to ICDRS and the data is sent from the SDA pin. In reception, data is transferred from ICDRS to ICDRR after one by of data is received. This register cannot be read from or write to by the CPU.
Bit Bit Name Initial Value R/W 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0
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Section 20 I C Bus Interface 2 (IIC2)
2
20.4
20.4.1
Operation
I2C Bus Format
Figure 20.3 shows the I2C bus formats. Figure 20.4 shows the I2C bus timing. The first frame following a start condition always consists of 8 bits.
(a) I2C bus format S 1 SLA 7 1 R/W 1 A 1 DATA n A 1 m A/A 1 P 1 n: Transfer bit count (n = 1 to 8) m: Transfer frame count (m 1)
(b) I2C bus format (start condition retransmission) S 1 SLA 7 1 R/W 1 A 1 DATA n1 m1 A/A 1 S 1 SLA 7 1 R/W 1 A 1 DATA n2 m2 A/A 1 P 1
n1 and n2: Transfer bit count (n1 and n2 = 1 to 8) m1 and m2: Transfer frame count (m1 and m2 1)
Figure 20.3 I2C Bus Formats
SDA
SCL 1-7 S SLA 8 R/W 9 A 1-7 DATA 8 9 A 1-7 DATA 8 9 A P
Figure 20.4 I2C Bus Timing [Legend] S: Start condition. The master device drives SDA from high to low while SCL is high. SLA: Slave address R/W: Indicates the direction of data transfer; from the slave device to the master device when R/W is 1, or from the master device to the slave device when R/W is 0. A: Acknowledge. The receive device drives SDA low. DATA: Transferred data P: Stop condition. The master device drives SDA from low to high while SCL is high.
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Section 20 I C Bus Interface 2 (IIC2)
2
20.4.2
Master Transmit Operation
In I2C bus format master transmit mode, the master device outputs the transmit clock and transmit data, and the slave device return an acknowledge signal. Figures 20.5 and 20.6 show the operating timings in master transmit mode. The transmission procedure and operations in master transmit mode are described below. 1. Set the ICR bit in the corresponding register to 1. Set the ICE bit in ICCRA to 1. Set the WAIT bit in ICMR and the CKS3 to CKS0 bits in ICCRA to 1. (initial setting) 2. Read the BSSY flag in ICCRB to confirm that the bus is free. Set the MST and TRS bits in ICCRA to select master transmit mode. Then, write 1 to BBSY and 0 to SCP using the MOV instruction. (The start condition is issued.) This generates the start condition. 3. After confirming that TDRE in ICSR has been set, write the transmit data (the first byte shows the slave address and R/W) to ICDRT. After this, when TDRE is automatically cleared to 0, data is transferred from ICDRT to ICDRS. TDRE is set again. 4. When transmission of one byte data is completed while TDRE is 1, TEND in ICSR is set to 1 at the rising of the ninth transmit clock pulse. Read the ACKBR bit in ICIER to confirm that the slave device has been selected. Then, write the second byte data to ICDRT. When ACKBR is 1, the slave device has not been acknowledged, so issue a stop condition. To issue the stop condition, write 0 to BBSY and SCP using the MOV instruction. SCL is fixed to a low level until the transmit data is prepared or the stop condition is issued. 5. The transmit data after the second byte is written to ICDRT every time TDRE is set. 6. Write the number of bytes to be transmitted to ICDRT. Wait until TEND is set (the end of last byte data transmission) while TDRE is 1, or wait for NACK (NACKF in ICSR is 1) from the receive device while ACKE in ICIER is 1. Then, issue the stop condition to clear TEND or NACKF. 7. When the STOP bit in ICSR is set to 1, the operation returns to the slave receive mode.
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Section 20 I C Bus Interface 2 (IIC2)
2
SCL (Master output) SDA (Master output)
1
2
3
4
5
6
7
8
9
1
2
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 R/W A
Bit 7
Bit 6
Slave address SDA (Slave output) TDRE
TEND
ICDRT
Address + R/W
Data 1
Data 2
ICDRS
Address + R/W
Data 1
User processing
[2] Instruction of start condition issuance
[4] Write data to ICDRT (second byte) [3] Write data to ICDRT (first byte) [5] Write data to ICDRT (third byte)
Figure 20.5 Master Transmit Mode Operation Timing 1
SCL (Master output) SDA (Master output) SDA (Slave output) TDRE
9
1
2
3
4
5
6
7
8
9
Bit 7 A
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 A/A
TEND
ICDRT
Data n
ICDRS User processing
Data n
[5] Write data to ICDRT
[6] Issue stop condition. Clear TEND. [7] Set slave receive mode
Figure 20.6 Master Transmit Mode Operation Timing 2
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Section 20 I C Bus Interface 2 (IIC2)
2
20.4.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data from the slave device, and returns an acknowledge signal. Figures 20.7 and 20.8 show the operation timings in master receive mode. The reception procedure and operations in master receive mode are shown below. 1. Clear the TEND bit in ICSR to 0, then clear the TRS bit in ICCRA to 0 to switch from master transmit mode to master receive mode. Then, clear the TDRE bit to 0. 2. When ICDDR is read (dummy read), reception is started, the receive clock pulse is output, and data is received, in synchronization with the internal clock. The master mode outputs the level specified by the ACKBT in ICIER to SDA, at the ninth receive clock pulse. 3. After the reception of the first frame data is completed, the RDRF bit in ICSR is set to 1 at the rising of the ninth receive clock pulse. At this time, the received data is read by reading ICDRR. At the same time, RDRF is cleared. 4. The continuous reception is performed by reading ICDRR and clearing RDRF to 0 every time RDRF is set. If the eighth receive clock pulse falls after reading ICDRR by other processing while RDRF is 1, SCL is fixed to a low level until ICDRR is read. 5. If the next frame is the last receive data, set the RCVD bit in ICCRA before reading ICDRR. This enables the issuance of the stop condition after the next reception. 6. When the RDRF bit is set to 1 at the rising of the ninth receive clock pulse, the stop condition is issued. 7. When the STOP bit in ICSR is set to 1, read ICDRR and clear RCVD to 0. 8. The operation returns to the slave receive mode.
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Section 20 I C Bus Interface 2 (IIC2)
2
Master transmit mode SCL (Master output) SDA (Master output) SDA (Slave output) TDRE A Bit 7 9 1
Master receive mode 2 3 4 5 6 7 8 9 A 1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TEND
TRS
RDRF
ICDRS
Data 1
ICDRR
Data 1
User processing
[1] Clear TEND and TRS, then TDRE
[2] Read ICDRR (dummy read)
[3] Read ICDRR
Figure 20.7 Master Receive Mode Operation Timing 1
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Section 20 I C Bus Interface 2 (IIC2)
2
SCL (Master output) SDA (Master output) SDA (Slave output) RDRF
9 A
1
2
3
4
5
6
7
8
9 A/A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
RCVD
ICDRS
Data n-1
Data n
ICDRR User processing
Data n-1
Data n
[5] Set RCVD then read ICDRR
[6] Issue stop condition
[7] Read ICDRR and clear RCVD [8] Set slave receive mode
Figure 20.8 Master Receive Mode Operation Timing 2 20.4.4 Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, and the master device outputs the receive clock pulse and returns an acknowledge signal. Figures 20.9 and 20.10 show the operation timings in slave transmit mode. The transmission procedure and operations in slave transmit mode are described below. 1. Set the ICR bit in the corresponding register to 1, then set the ICE bit in ICCRA to 1. Set the WAIT in ICMR and CKS3 to CKS0 in ICCRA (initial setting). Set the MST and TRS bits in ICCRA to select slave receive mode, and wait until the slave address matches. 2. When the slave address matches in the first frame following the detection of the start condition, the slave device outputs the level specified by ACKBT in ICIER to SDA, at the rising of the ninth clock pulse. At this time, if the eighth bit data (R/W) is 1, TRS in ICCRA and TDRE in ICSR are set to 1, and the mode changes to slave transmit mode automatically. The continuous transmission is performed by writing the transmit data to ICDRT every time TDRE is set. 3. If TDRE is set after writing the last transmit data to ICDRT, wait until TEND in ICSR is set to 1, with TDRE = 1. When TEND is set, clear TEND. 4. Clear TRS for end processing, and read ICDRR (dummy read) to release SCL. 5. Clear TDRE.
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Section 20 I C Bus Interface 2 (IIC2)
2
Slave receive mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE A 9
Slave transmit mode 1 2 3 4 5 6 7 8 9 A 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
TEND
TRS
ICDRT
Data 1
Data 2
Data 3
ICDRS
Data 1
Data 2
ICDRR User processing [2] Write data (data 1) to ICDRT [2] Write data (data 2) to ICDRT [2] Write data (data 3) to ICDRT
Figure 20.9 Slave Transmit Mode Operation Timing 1
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Section 20 I C Bus Interface 2 (IIC2)
2
Slave transmit mode SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) TDRE Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 9 A 1 2 3 4 5 6 7 8 9 A/A
Slave receive mode
TEND TRS
ICDRT
ICDRS
Data n
ICDRR
User processing
[3] Clear TEND
[4] Clear TRS and read ICDRR (dummy read)
[5] Clear TDRE
Figure 20.10 Slave Transmit Mode Operation Timing 2
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Section 20 I C Bus Interface 2 (IIC2)
2
20.4.5
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and the transmit data, and the slave device returns an acknowledge signal. Figures 20.11 and 20.12 show the operation timings in slave receive mode. The reception procedure and operations in slave receive mode are described below. 1. Set the ICR bit in the corresponding register to 1. Then, set the ICE bit in ICCRA to 1. Set the WAIT bit in ICMR or CKS3 to CKS0 in ICCRA (initial setting). Set the MST and TRS bits in ICCRA to select slave receive mode and wait until the slave address matches. 2. When the slave address matches in the first frame following detection of the start condition, the slave address outputs the level specified by ACKBT in ICIER to SDA, at the rising of the ninth clock pulse. At the same time, RDRF in ICSR is set to read ICDRR (dummy read). (Since the read data shows the slave address and R/W, it is not used). 3. Read ICDRR every time RDRF is set. If the eighth clock pulse falls while RDRF is 1, SCL is fixed to a low level until ICDRR is read. The change of the acknowledge (ACKBT) setting before reading ICDRR to be returned to the master device is reflected in the next transmit frame. 4. The last byte data is read by reading ICDRR.
SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output) RDRF A A
9
1
2
3
4
5
6
7
8
9
1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Bit 7
ICDRS
Data 1
Data 2
ICDRR
User processing
Data 1
[2] Read ICDRR (dummy read)
[2] Read ICDRR
Figure 20.11 Slave Receive Mode Operation Timing 1
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Section 20 I C Bus Interface 2 (IIC2)
2
SCL (Master output) SDA (Master output) SCL (Slave output) SDA (Slave output)
9
1
2
3
4
5
6
7
8
9
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
A
A
RDRF
ICDRS
Data 1
Data 2
ICDRR
User processing
[3] Set ACKBT [3] Read ICDRR
Data 1
[4] Read ICDRR
Figure 20.12 Slave Receive Mode Operation Timing 2 20.4.6 Noise Canceler
The logic levels at the SCL and SDA pins are routed through the noise cancelers before being latched internally. Figure 20.13 shows a block diagram of the noise canceler circuit. The noise canceler consists of two cascaded latches and a match detector. The signal input to SCL (or SDA) is sampled on the system clock, but is not passed forward to the next circuit unless the outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock Sampling clock
SCL input or SDA input
C D Q D
C Q
Latch
Latch
Compare match detection circuit
Internal SCL or internal SDA
System clock period
Sampling clock
Figure 20.13 Block Diagram of Noise Canceler
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Section 20 I C Bus Interface 2 (IIC2)
2
20.4.7
Example of Use
Sample flowcharts in respective modes that use the I2C bus interface are shown in figures 20.14 to 20.17.
Start Initial settings Read BBSY in ICCRB No [1] BBSY = 0? Yes Set MST = 1 and TRS = 1 in ICCRA Write BBSY = 1 and SCP = 0 Write the transmit data in ICDRT Read TEND in ISCR No [5] TEND = 1? [2] [3]
[1] [2] [3] [4] [5] [6] [7]
Detect the state of the SCL and SDA lines Set to master transmit mode Issue the start condition Set the transmit data for the first byte (slave address + R/W) Wait for 1 byte of data to be transmitted Detect the acknowledge bit, transferred from the specified slave device Set the transmit data for the second and subsequent data (except for the last byte) Wait for ICDRT empty Set the last byte of transmit data
[4]
Yes Read ACKBR in ICIER [6] ACKBR = 0? Yes Transmit mode? Yes No No
[8] [9]
Master receive mode
Write the transmit data to ICDRT Read TDRE in ICSR TDRE = 1? Yes No Last byte? Yes
[7]
[10] Wait for the completion of transmission of the last byte
[8]
[11] Clear the TEND flag [12] Clear the STOP flag
[9]
[13] Issue the stop condition [14] Wait for the creation of the stop condition
Write the transmit data to ICDRT Read TEND in ICSR No [10] TEND = 1? Yes Clear TEND in ICSR Clear STOP in ICSR Write BBSY = 0 and SCP = 0 Read STOP in ICSR No [14] STOP = 1? Yes Set MST = 0 and TRS = 0 in ICCRA Clear TRDE in ICSR End [11] [12] [13]
[15] Set to slave receive mode. Clear TDRE.
[15]
Figure 20.14 Sample Flowchart of Master Transmit Mode
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Section 20 I C Bus Interface 2 (IIC2)
2
Master receive mode Clear TEND in ICSR Set TRS = 0 (ICCRA) Clear TDRE in ICSR Set ACKBT = 0 (ICIER) Dummy read ICDRR Dummy read ICSR
No RDRF = 1? Yes [4] [2] [3] [1]
[1] [2] [3] [4] [5] [6] [7]
Clear TEND, set to master receive mode, then clear TDRE*1*2 Set acknowledge to the transmitting device*1*2 Dummy read ICDRR*1*2 Wait for 1 byte of data to be received*2 Check if (last receive -1)*2 Read the receive data*2 Set acknowledge of the last byte. Disable continuous reception (RCVD = 1).*2 Read receive data of (last byte -1).*2 Wait for the last byte to be received
Last receive -1?
No
Yes
[5]
[8]
[6]
Read ICDRR
[9]
[10] Clear the STOP flag Set ACKBT = 1 (ICIER)
[7]
[11] Issue the stop condition [12] Wait for the creation of stop condition
Set RCVD = 1 (ICCRA) Read ICDRR Read RDRF in ICSR
No [9] RDRF = 1? Yes [8]
[13] Read the receive data of the last byte [14] Clear RCVD to 0 [15] Set to slave receive mode
Clear STOP in ICSR Write BBSY = 0 and SCP = 0 Read STOP in ICSR
No
[10]
[11]
[12] STOP = 1? Yes
Read ICDRR Set RCVD = 0 (ICCRA) Set MST = 0 (ICCRA) End Note: 1. 2.
[13] [14] [15]
Do not generate an interrupt during steps [1] to [3]. For one-byte reception, steps [2] to [6] do not need to be executed. After step [1], execute step [7]. In step [8], read ICDRR (dummy read).
Figure 20.15 Sample Flowchart for Master Receive Mode
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Section 20 I C Bus Interface 2 (IIC2)
2
Slave transmit mode Clear AAS in ICSR [1] [1] Clear the AAS flag. [2] Set the transmit data for ICDRT (except the last byte). [2] [3] Wait for ICDRT empty. [4] Set the last byte of transmit data. [3] TDRE = 1? Yes No Last byte? Yes Write the transmit data to ICDRT Read TEND in ICSR No [5] TEND = 1? Yes Clear TEND in ICSR Set TRS = 0 (ICCRA) Dummy read ICDRR Clear TDRE in ICSR End [4] [6] Clear the TEND flag. [7] Set to slave receive mode. [8] Dummy read ICDRR to free the SCL line. [9] Clear the TDRE flag. [5] Wait for the last byte of data to be transmitted.
Write the transmit data to ICDRT Read TRD in ICSR No
[6] [7] [8] [9]
Figure 20.16 Sample Flowchart for Slave Transmit Mode
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Section 20 I C Bus Interface 2 (IIC2)
2
Slave receive mode Clear AAS in ICSR Set ACKBT = 0 in ICIER Dummy read ICDRR Read RDRF in ICSR
[1] [2] [3]
[1] Clear the AAS flag.* [2] Set the acknowledge for the transmit device.* [3] Dummy read ICDRR* [4] Wait for 1 byte of data to be received* [5] Detect (last reception -1)*
No RDRF = 1? Yes
The last reception -1?
[4]
[6] Read the receive data.* [7] Set the acknowledge for the last byte.*
Yes
[5]
[8] Read the receive data of (last byte -1).* [9] Wait for the reception of the last byte to be completed.
No Read ICDRR
[6]
[10] Read the last byte of receive data.
Set ACKBT = 1 in ICIER
[7]
Read ICDRR Read RDRF in ICSR
[8]
No
[9] RDRF = 1? Yes
Read ICDRR End
[10]
Note: * For one-byte reception, steps [2] to [6] do not need to be executed. After step [1], execute step [7]. In step [8], read ICDRR (dummy read).
Figure 20.17 Sample Flowchart for Slave Receive Mode
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Section 20 I C Bus Interface 2 (IIC2)
2
20.5
Interrupt Request
There are six interrupt requests in this module; transmit data empty, transmit end, receive data full, NACK detection, STOP recognition, and arbitration lost. Table 20.3 shows the contents of each interrupt request. Table 20.3 Interrupt Requests
Interrupt Request Transmit Data Empty Transmit End Receive Data Full Stop Recognition NACK Detection Arbitration Lost Abbreviation TXI TEI RXI STPI NAKI Interrupt Condition (TDRE = 1) (TIE = 1) (TEND = 1) (TEIE = 1) (RDRF = 1) (RIE = 1) (STOP = 1) (STIE = 1) {(NACKF = 1) + (AL = 1)} (NAKIE = 1)
When one of the interrupt conditions in table 20.3 is 1 and the I bit in CCR is 0, the CPU executes interrupt exception handling. Clear the interrupt sources during interrupt exception handling. Note that the TDRE and TEND bits are automatically cleared to 0 by writing data to ICDRT, and the RDRF bit is cleared to 0 by reading ICDRR. In particular, the TDRE bit can be set again at the same time as data are for transmission written to ICDRT, and 1 extra byte can be transmitted if the TDRE is again cleared to 0.
20.6
Bit Synchronous Circuit
This module has a possibility that the high-level period is shortened in the two states described below. In master mode, * When SCL is driven low by the slave device * When the rising speed of SCL is lowered by the load on the SCL line (load capacitance or pull-up resistance) Therefore, this module monitors SCL and communicates bit by bit in synchronization. Figure 20.18 shows the timing of the bit synchronous circuit, and table 20.4 shows the time when SCL output changes from low to Hi-Z and the period which SCL is monitored.
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Section 20 I C Bus Interface 2 (IIC2)
2
SCL monitor timing reference clock
SCL
VIH
Internal SCL
Figure 20.18 Timing of the Bit Synchronous Circuit Table 20.4 Time for Monitoring SCL
CKS3 0 CKS2 0 1 1 0 1 Time for Monitoring SCL 7.5 tcyc 19.5 tcyc 17.5 tcyc 41.5 tcyc
20.7
Usage Notes
1. Confirm the ninth falling edge of the clock before issuing a stop or a repeated start condition. The ninth falling edge can be confirmed by monitoring the SCLO bit in the I2C bus control register B (ICCRB). If a stop or a repeated start condition is issued at certain timing in either of the following cases, the stop or repeated start condition may be issued incorrectly. The rising time of the SCL signal exceeds the time given in section 20.6, Bit Synchronous Circuit, because of the load on the SCL bus (load capacitance or pull-up resistance). The bit synchronous circuit is activated because a slave device holds the SCL bus low during the eighth clock. 2. The WAIT bit in the I2C bus mode register (ICMR) must be held 0. If the WAIT bit is set to 1, when a slave device holds the SCL signal low more than one transfer clock cycle during the eighth clock, the high level period of the ninth clock may be shorter than a given period.
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Section 20 I C Bus Interface 2 (IIC2)
2
3. Restriction in transfer rate setting value in multi-master mode When the transfer rate of I2C transfer of this LSI is slower than that of other master, the SCL signal the width of which is unexpected may be output. To avoid this phenomenon, set a transfer rate of 1/1.8 or more of the fastest rate of other master to the transfer rate of I2C transfer rate. For example, if the fastest rate of other masters is 400 kbps, the I2C transfer rate of this LSI should be 223 kbps (= 400/1.8) or more. 4. Restriction in bit manipulation when the MST and TRS bits are set in multi-master mode When the MST and TRS bits are set to master slave mode by manipulating these bits sequentially, the conflict state occurs as follows according to the timing that arbitration is lost; The AL bit in ICSR is set to 0, and set to master mode (MST = 1, TRS = 1). There are the following methods to avoid this phenomenon. * In multi-master mode, set the MST and TRS bits by MOV instruction. * When arbitration is lost, confirm that the MST and TRS bits are set to 0. If these bits are set to other than 0, set these bits to 0. 5. Notes on master receive mode In master receive mode, the RDRF bit is set to 0 at the eighth rising clock, the SCL signal is pulled to "Low" state. When ICDRR is read near at the eighth falling clock, the SCL signal level is released and the ninth clock is outputted by fixing the eighth clock of receive data to "Low" state. Reading ICDRR is not required. As a result, the failure to receive data occurs. There are the following methods to avoid this phenomenon. * In master receive mode, read ICDRR by the eighth rising clock. * In master receive mode, set the RCVD bit to 1 and process the bit by the communication of every one byte. 6. Setting of the module stop function Operation of the IIC2 can be disabled or enabled using the module stop control register. The initial setting is for operation of the IIC2 to be halted. Register access is enabled by clearing module stop state. For details, see section 27, Power-Down Modes.
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Section 21 A/D Converter
Section 21 A/D Converter
This LSI includes two units (units 0 and 1) of successive approximation type 10-bit A/D converter. The A/D converter unit 0 allows up to eight analog input channels to be selected while the A/D converter unit 1 allows up to four analog input channels to be selected. Figures 21.1 and 21.2 show block diagrams of the A/D converter units 0 and 1, respectively.
21.1
Features
* 10-bit resolution * Eight or four input channels (total eight input channels for the two units) Four channels x two units (for unit 0 and unit 1) Eight channels x one unit (for unit 0) * Conversion time: Unit 0: (2.7 s per channel) Unit 1: (2.7 s per channel) * Two kinds of operating modes Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels, or 1 to 8 channels * Eight data registers for the A/D converter unit 0 and four data registers for unit 1 (total eight data registers for the two units) Results of A/D conversion are held in a 16-bit data register for each channel. * Sample and hold functionality * Three types of conversion start Conversion can be started by software, a conversion start trigger by the 16-bit timer pulse unit (TPU)*1 or 8-bit timer (TMR)*2, or an external trigger signal. * Function of starting units simultaneously A/D conversion for multiple units can be started by external trigger (ADTRG0). * Interrupt source A/D conversion end interrupt (ADI) request can be generated. * Module stop state specifiable Notes: 1. Only supported in the A/D converter unit 0. 2. For unit 0, A/D conversion can be started by a conversion start trigger by the TMR units 0 and 1 whereas for unit 1 A/D conversion can be started by a conversion start trigger by the TMR units 2 and 3.
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Section 21 A/D Converter
Module data bus
Bus interface ADDRG_0 ADDRC_0 ADDRD_0 ADDRH_0 ADDRA_0 ADDRB_0 ADDRE_0 ADCSR_0 ADDRF_0
Internal data bus
AVCC 10-bit A/D
Successive approximation register
Vref
AVSS
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7
Multiplexer
+ - Comparator Sample-andhold circuit Control circuit
ADCR_0
ADTRG0 Synchronization circuit [Legend] ADCR_0: ADCSR_0: ADDRA_0: ADDRB_0: ADDRC_0: A/D control register_0 A/D control/status register_0 A/D data register A_0 A/D data register B_0 A/D data register C_0 ADDRD_0: ADDRE_0: ADDRF_0: ADDRG_0: ADDRH_0: A/D data register D_0 A/D data register E_0 A/D data register F_0 A/D data register G_0 A/D data register H_0
ADI0 interrupt signal Conversion start trigger from the TPU or TMR (units 0, 1)
Figure 21.1 Block Diagram of A/D Converter Unit 0 (AD_0)
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Section 21 A/D Converter
Module data bus
Bus interface ADDRG_1 ADDRC_1 ADDRD_1 ADDRH_1 ADDRA_1 ADDRB_1 ADDRE_1 ADCSR_1 ADDRF_1
Internal data bus
AVCC 10-bit A/D
Successive approximation register
Vref
AVSS
AN4
+ -
Multiplexer
AN5
Comparator Sample-andhold circuit
Control circuit
AN6
AN7
ADCR_1
ADI1 interrupt signal ADTRG1 ADTRG0 Synchronization circuit Conversion start trigger from the TMR (units 2, 3)
[Legend] ADCR_1: A/D control register_1 ADCSR_1: A/D control/status register_1 ADDRA_1: A/D data register A_1 ADDRB_1: A/D data register B_1 ADDRC_1: A/D data register C_1
ADDRD_1: ADDRE_1: ADDRF_1: ADDRG_1: ADDRH_1:
A/D data register D_1 A/D data register E_1 A/D data register F_1 A/D data register G_1 A/D data register H_1
Figure 21.2 Block Diagram of A/D Converter Unit 1 (AD_1)
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Section 21 A/D Converter
21.2
Input/Output Pins
Table 21.1 shows the pin configuration of the A/D converter. Table 21.1 Pin Configuration
Unit 0 Abbr. AD_0 Pin Name Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin 0 1 AD_1 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 A/D external trigger input pin 0 A/D external trigger input pin 1 Common Analog power supply pin Analog ground pin Reference voltage pin Note: * Symbol AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 ADTRG0 AN4 AN5 AN6 AN7 ADTRG0 ADTRG1 AVCC AVSS Vref I/O Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input External trigger input pin for starting A/D conversion* External trigger input pin for starting A/D conversion* Analog block power supply Analog block ground A/D conversion reference voltage External trigger input for starting A/D conversion* Analog inputs Function Analog inputs
Selectable by setting of the TRGS1, TRGS0, and EXTRGS bits in ADCR.
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Section 21 A/D Converter
21.3
Register Descriptions
The A/D converter has the following registers. Unit 0 (A/D_0) registers * * * * * * * * * * A/D data register A_0 (ADDRA_0) A/D data register B_0 (ADDRB_0) A/D data register C_0 (ADDRC_0) A/D data register D_0 (ADDRD_0) A/D data register E_0 (ADDRE_0) A/D data register F_0 (ADDRF_0) A/D data register G_0 (ADDRG_0) A/D data register H_0 (ADDRH_0) A/D control/status register_0 (ADCSR_0) A/D control register_0 (ADCR_0)
Unit 1 (A/D_1) registers * * * * * * * * * * A/D data register A_1 (ADDRA_1) A/D data register B_1 (ADDRB_1) A/D data register C_1 (ADDRC_1) A/D data register D_1 (ADDRD_1) A/D data register E_1 (ADDRE_1) A/D data register F_1 (ADDRF_1) A/D data register G_1 (ADDRG_1) A/D data register H_1 (ADDRH_1) A/D control/status register_1 (ADCSR_1) A/D control register_1 (ADCR_1)
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Section 21 A/D Converter
21.3.1
A/D Data Registers A to H (ADDRA to ADDRH)
There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of A/D conversion. The ADDR registers, which store a conversion result for each channel, are shown in table 21.2. The converted 10-bit data is stored in bits 15 to 6. The lower 6-bit data is always read as 0. The data bus between the CPU and the A/D converter has a 16-bit width. The data can be read directly from the CPU. ADDR must not be accessed in 8-bit units and must be accessed in 16-bit units.
Bit Bit Name Initial Value R/W 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 0 R 15 14 13 12 11 10 9 8 7 6 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R
Table 21.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A/D Data Register Storing Conversion Result Unit 0 ADDRA_0 (Unit 0) ADDRB_0 (Unit 0) ADDRC_0 (Unit 0) ADDRD_0 (Unit 0) ADDRE_0 (Unit 0)*
1
Unit 1*
2
ADDRE_1 (Unit 1)*1 ADDRF_1 (Unit 1)*1 ADDRG_1 (Unit 1)*1 ADDRH_1 (Unit 1)*1
ADDRF_0 (Unit 0)*1 ADDRG_0 (Unit 0)*1 ADDRH_0 (Unit 0)*1
Notes: 1. A/D conversion should not be performed on the same channel by multiple units. 2. The ADDRA_1 to ADDRD_1 registers for unit 1 are not used.
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Section 21 A/D Converter
21.3.2
A/D Control/Status Register for Unit 0 (ADCSR_0)
ADCSR_0 controls A/D conversion operations.
Bit Bit Name Initial Value R/W 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 0 R/W 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W
Note: * Only 0 can be written to this bit, to clear the flag.
Bit 7
Bit Name ADF
Initial Value 0
R/W
Description
6 5
ADIE ADST
0 0
R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * Completion of A/D conversion in single mode * Completion of A/D conversion on all specified channels in scan mode [Clearing conditions] * Writing of 0 after reading ADF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * Reading from ADDR after activation of the DMAC or DTC by an ADI interrupt R/W A/D Interrupt Enable Setting this bit to 1 enables ADI interrupts by ADF. R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when A/D conversion on the specified channel ends. In scan mode, A/D conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or hardware standby mode. Note: Do not write to ADST when activation is by an external trigger. For details, see section 21.7.3, Notes on A/D activation by an External Trigger. R/W Reserved This bit is always read as 0. The write value should always be 0.
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4
0
Section 21 A/D Converter
Bit 3 2 1 0
Bit Name CH3 CH2 CH1 CH0
Initial Value 0 0 0 0
R/W R/W R/W R/W R/W
Description Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR. * When SCANE = 0 and SCANS = x 0000: AN0 0001: AN1 0010: AN2 0011: AN3 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1xxx: Setting prohibited * When SCANE = 1 and SCANS = 0 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN4 0101: AN4 and AN5 0110: AN4 to AN6 0111: AN4 to AN7 1xxx: Setting prohibited * When SCANE = 1 and SCANS = 1 0000: AN0 0001: AN0 and AN1 0010: AN0 to AN2 0011: AN0 to AN3 0100: AN0 to AN4 0101: AN0 to AN5 0110: AN0 to AN6 0111: AN0 to AN7 1xxx: Setting prohibited
[Legend] x: Don't care Note: * Only 0 can be written to this bit, to clear the flag.
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Section 21 A/D Converter
21.3.3
A/D Control/Status Register for Unit 1 (ADCSR_1)
ADCSR_1 controls A/D conversion operations.
Bit Bit Name Initial Value R/W 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 EXCKS 0 R/W 3 CH3 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W
Note: * Only 0 can be written to this bit, to clear the flag.
Bit 7
Bit Name ADF
Initial Value 0
R/W
Description
6 5
ADIE ADST
0 0
R/(W)* A/D End Flag A status flag that indicates the end of A/D conversion. [Setting conditions] * Completion of A/D conversion in single mode * Completion of A/D conversion on all specified channels in scan mode [Clearing conditions] * Writing of 0 after reading ADF = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.) * Reading from ADDR after activation of the DMAC or DTC by an ADI interrupt R/W A/D Interrupt Enable Setting this bit to 1 enables ADI interrupts by ADF. R/W A/D Start Clearing this bit to 0 stops A/D conversion, and the A/D converter enters wait state. Setting this bit to 1 starts A/D conversion. In single mode, this bit is cleared to 0 automatically when A/D conversion on the specified channel ends. In scan mode, A/D conversion continues sequentially on the specified channels until this bit is cleared to 0 by software, a reset, or hardware standby mode. Note: Do not write to ADST when activation is by an external trigger. For details, see section 21.7.3, Notes on A/D activation by an External Trigger.
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Section 21 A/D Converter
Bit 4
Bit Name EXCKS
Initial Value 0
R/W R/W
Description Clock Extension Select Specifies the A/D conversion time in combination with the CKS1 and CKS0 bits in ADCR. Be sure to set these three bits at one time. For details, see section 21.3.5, A/D Control Register for Unit 1 (ADCR_1). Channel Select 3 to 0 Selects analog input together with bits SCANE and SCANS in ADCR. * When SCANE = 0 and SCANS = X 00XX: Setting prohibited 0100: AN4 0101: AN5 0110: AN6 0111: AN7 1XXX: Setting prohibited * When SCANE = 1 and SCANS = 0 00XX: Setting prohibited 0100: AN4 0101: AN4 and AN5 0110: AN4 to AN6 0111: AN4 to AN7 1XXX: Setting prohibited * When SCANE = 1 and SCANS = 1 XXXX: Setting prohibited
3 2 1 0
CH3 CH2 CH1 CH0
0 0 0 0
R/W R/W R/W R/W
[Legend] x: Don't care Note: * Only 0 can be written to this bit, to clear the flag.
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Section 21 A/D Converter
21.3.4
A/D Control Register for Unit 0 (ADCR_0)
ADCR enables A/D conversion to be started by an external trigger input.
Bit Bit Name Initial Value R/W 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 SCANE 0 R/W 4 SCANS 0 R/W 3 CKS1 0 R/W 2 CKS0 0 R/W 1 0 R/W 0 EXTRGS 0 R/W
Bit 7 6 0
Bit Name TRGS1 TRGS0 EXTRGS
Initial Value 0 0 0
R/W R/W R/W R/W
Description Timer Trigger Select 1 and 0, extended trigger select These bits select enabling or disabling of the start of A/D conversion by a trigger signal. 000: Disables A/D conversion start by external trigger 010: Enables A/D conversion start by external trigger from TPU (unit 0) 100: Enables A/D conversion start by external trigger from TMR (units 0 and 1) 110: Enables A/D conversion start by the ADTRG0 pin* 001: External trigger disabled 011: Setting prohibited 101: Setting prohibited 111: Enables A/D conversion start by the ADTRG0 pin* (starts units simultaneously)
1 1
Note: Do not write to ADST when activation is by an external trigger. For details, see section 21.7.3, Notes on A/D activation by an External Trigger. 5 4 SCANE SCANS 0 0 R/W R/W Scan Mode These bits select the A/D conversion operating mode. 0x: Single mode 10: Scan mode. A/D conversion is performed continuously for channels 1 to 4. 11: Scan mode. A/D conversion is performed continuously for channels 1 to 8.
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Section 21 A/D Converter
Bit 3 2
Bit Name CKS1 CKS0
Initial Value 0 0
R/W R/W R/W
Description Clock Select 1 and 0 These bits set the A/D conversion time. First select the A/D conversion time by setting bits CKS1 and CKS0 while ADST = 0 and then set the mode of A/D conversion. CKS1, and CKS0
2 00: A/D conversion time = 528 states* (max.) 2 01: A/D conversion time = 268 states* (max.) 2 10: A/D conversion time = 138 states* (max.) 2 11: A/D conversion time = 73 states* (max.)
1
0
R/W
Reserved This bit is always read as 0. The write value should always be 0.
[Legend] x: Don't care Notes: 1. To set A/D conversion to start by the ADTRG pin, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 13, I/O Ports. 2. P criterion
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Section 21 A/D Converter
21.3.5
A/D Control Register for Unit 1 (ADCR_1)
ADCR enables A/D conversion to be started by an external trigger input.
Bit Bit Name Initial Value R/W 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 SCANE 0 R/W 4 SCANS 0 R/W 3 CKS1 0 R/W 2 CKS0 0 R/W 1 ADSTCLR 0 R/W 0 EXTRGS 0 R/W
Bit 7 6 0
Bit Name TRGS1 TRGS0 EXTRGS
Initial Value 0 0 0
R/W R/W R/W R/W
Description Timer Trigger Select 1 and 0, extended trigger select These bits select enabling or disabling of the start of A/D conversion by a trigger signal. 000: Disables A/D conversion start by external trigger 010: Setting prohibited 100: Setting prohibited 110: Enables A/D conversion start by the ADTRG1 pin* 001: Setting prohibited 011: External trigger disabled 101: Enables A/ D conversion start by external trigger from TMR (units 2 and 3) 111: Enables A/D conversion start by the ADTRG0 pin*1 (starts units simultaneously) Note: Do not write to ADST when activation is by an external trigger. For details, see section 21.7.3, Notes on A/D activation by an External Trigger.
1
5 4
SCANE SCANS
0 0
R/W R/W
Scan Mode These bits select the A/D conversion operating mode. 0x: Single mode 10: Scan mode. A/D conversion is performed continuously for channels 1 to 4. 11: Setting prohibited
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Section 21 A/D Converter
Bit 3 2
Bit Name CKS1 CKS0
Initial Value 0 0
R/W R/W R/W
Description Clock Select 1 and 0 These bits set the A/D conversion time in combination with the EXCKS bit. First select the A/D conversion time by setting bits CKS1 and CKS0 while ADST = 0 and then set the mode of A/D conversion. EXCKS, CKS1, and CKS0
2 000: A/D conversion time = 528 states* (max.) 2 001: A/D conversion time = 268 states* (max.) 2 010: A/D conversion time = 138 states* (max.) 2 011: A/D conversion time = 73 states* (max.) 2 100: A/D conversion time = 336 states* (max.) 2 101: A/D conversion time = 172 states* (max.) 2 110: A/D conversion time = 90 states* (max.) 2 111: A/D conversion time = 49 states* (max.)
1
ADSTCLR 0
R/W
A/D Start Clear This bit enables or disables automatic clearing of the ADST bit in scan mode. 0: The ADST bit is not automatically cleared to 0 in scan mode. 1: Clears the ADST bit to 0 upon completion of the A/D conversion for all of the selected channels in scan mode.
[Legend] x: Don't care Notes: 1. To set A/D conversion to start by the ADTRG pin, the DDR bit and ICR bit for the corresponding pin should be set to 0 and 1, respectively. For details, see section 13, I/O Ports. 2. P criterion
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Section 21 A/D Converter
21.4
Operation
The A/D converter has two operating modes: single mode and scan mode. First select the clock for A/D conversion (ADCLK). When changing the operating mode or analog input channel, to prevent incorrect operation, first clear the ADST bit in ADCSR to 0. The ADST bit can be set to 1 at the same time as the operating mode or analog input channel is changed. 21.4.1 Single Mode
In single mode, A/D conversion is to be performed only once on the analog input of the specified single channel. 1. A/D conversion for the selected channel is started when the ADST bit in ADCSR is set to 1 by software, TPU*1, TMR*2, or an external trigger input. 2. When A/D conversion is completed, the A/D conversion result is transferred to the corresponding A/D data register of the channel. 3. When A/D conversion is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 4. The ADST bit remains at 1 during A/D conversion, and is automatically cleared to 0 when A/D conversion ends. The A/D converter enters wait state. If the ADST bit is cleared to 0 during A/D conversion, A/D conversion stops and the A/D converter enters a wait state. Notes: 1. Only possible in unit 0. 2. As conversion start trigger, units 0 and 1 of TMR, and units 2 and 3 of TMR are available in unit 0, and unit 1, respectively.
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Section 21 A/D Converter
Set* ADIE Set* ADST A/D conversion start Clear* ADF Clear* Set*
Channel 0 (AN0) operation state Channel 1 (AN1) operation state Channel 2 (AN2) operation state Channel 3 (AN3) operation state ADDRA
Waiting for conversion Waiting for conversion
A/D conversion 1
Waiting for conversion
A/D conversion 2
Waiting for conversion
Waiting for conversion
Waiting for conversion
Reading A/D conversion result
Reading A/D conversion result A/D conversion result 2
ADDRB ADDRC
A/D conversion result 1
ADDRD
Note: * indicates the timing of instruction execution by software.
Figure 21.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 21.4.2 Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the analog inputs of the specified channels up to four or eight*1 channels. Two types of scan mode are provided, that is , continuous scan mode where A/D conversion is repeatedly performed and one-cycle scan mode where A/D conversion is performed for the specified channels for one cycle. (1) Continuous Scan Mode
1. When the ADST bit in ADCSR is set to 1 by software, TPU*1, TMR*2, or an external trigger input, A/D conversion starts on the first channel in the specified channel group. Consecutive A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) or on a maximum of eight channels*1 (SCANE and SCANS = B'11) can be selected. When consecutive A/D conversion is performed on four channels, A/D conversion starts on AN0 when CH3 and CH2 of unit 0 = B'00, on AN4 when CH3 and CH2 of units 0 and 1 = B'01.
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Section 21 A/D Converter
When consecutive A/D conversion is performed on eight channels*1, A/D conversion starts on AN0 when CH3 = B'0. 2. When A/D conversion for each channel is completed, the A/D conversion result is sequentially transferred to the corresponding ADDR of each channel. 3. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. A/D conversion of the first channel in the group starts again. 4. The ADST bit is not cleared automatically, and steps 2 to 3 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again from the first channel in the group. Notes: 1. Consecutive A/D conversion on eight channels is only possible in unit 0. 2. As conversion start trigger, units 0 and 1 of TMR, and units 2 and 3 of TMR are available in unit 0, and unit 1, respectively.
A/D conversion consecutive execution Set*1 ADST Clear*1 Clear*1
ADF Channel 0 (AN0) operation state Channel 1 (AN1) operation state Channel 2 (AN2) operation state Channel 3 (AN3) operation state ADDRA Waiting for conversion A/D conversion 1 A/D conversion time Waiting for conversion A/D conversion 2 A/D conversion 4 Waiting for conversion A/D conversion 5 Waiting for conversion
Waiting for conversion
Waiting for conversion A/D conversion 3
*2
Waiting for conversion
Waiting for conversion
Waiting for conversion Transfer A/D conversion result 1 A/D conversion result 4
ADDRB
A/D conversion result 2
ADDRC
A/D conversion result 3
ADDRD
Notes: 1. indicates the timing of instruction execution by software. 2. Data being converted is ignored.
Figure 21.4 Example of A/D Conversion (Continuous Scan Mode, Three Channels (AN0 to AN2) Selected)
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Section 21 A/D Converter
(2)
One-Cycle Scan Mode (only enabled in unit 1)
1. Set the ADSTCLR bit in ADCR to 1. 2. When the ADST bit in ADCSR is set to 1 by software, TMR (units 2 and 3), or an external trigger input, A/D conversion starts on the first channel in the specified channel group. Consecutive A/D conversion on a maximum of four channels (SCANE and SCANS = B'10) can be selected. For unit 1, A/D conversion starts on AN4 when CH3 and CH2 = B'01. 3. When A/D conversion for each channel is completed, the A/D conversion result is sequentially transferred to the corresponding ADDR of each channel. 4. When A/D conversion of all selected channels is completed, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. 5. The ADST bit is automatically cleared when A/D conversion is completed for all of the channels that have been selected. A/D conversion stops and the A/D converter enters a wait state.
A/D conversion one-cycle execution
Set * ADST Clear* ADF A/D conversion time Channel 4 (AN4) Waiting for conversion operation state A/D conversion 1 Waiting for conversion
Channel 5 (AN5) operation state Channel 6 (AN6) operation state Channel 7 (AN7) operation state
Waiting for conversion
A/D conversion 2
Waiting for conversion
Waiting for conversion
A/D conversion 3
Waiting for conversion
Waiting for conversion Transfer
ADDRE
A/D conversion result 1
ADDRF
A/D conversion result 2
ADDRG
A/D conversion result 3
ADDRH Note: indicates the timing of instruction execution by software.
Figure 21.5 Example of A/D Conversion (One-Cycle Scan Mode, Three Channels (AN4 to AN6) Selected)
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Section 21 A/D Converter
21.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input when the A/D conversion start delay time (tD) passes after the ADST bit in ADCSR is set to 1, then starts A/D conversion. Figure 21.6 shows the A/D conversion timing. Tables 21.3 and 21.4 show the A/D conversion time. As shown in figure 21.6, the A/D conversion time (tCONV) includes the A/D conversion start delay time (tD) and the input sampling time (tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in tables 21.3 and 21.4. In scan mode, the values given in tables 21.3 and 21.4 apply to the first conversion time. The values given in table 21.5 apply to the second and subsequent conversions. In either case, bits CKS1 and CKS0 in ADCR should be set so that the conversion time is within the ranges indicated by the A/D conversion characteristics.
(1) P Address (2)
Write signal Input sampling timing
ADF tD tSPL tCONV [Legend] (1): ADCSR write cycle (2): ADCSR address A/D conversion start delay time tD: tSPL: Input sampling time tCONV: A/D conversion time
Figure 21.6 A/D Conversion Timing
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Section 21 A/D Converter
Table 21.3 A/D Conversion Characteristics (EXCKS1 = 0)
CKS1 = 0 CKS = 0 Item A/D conversion start delay time Input sampling time A/D conversion time tSPL tCONV 518 312 528 262 156 268 134 78 138 69 39 73 Symbol tD Min. 4 Typ. Max. 14 Min. 4 CKS = 1 Typ. Max. 10 Min. 4 CKS = 0 Typ. Max. 8 Min. 3 CKS1 = 1 CKS = 1 Typ. Max. 7
Note: Values in the table are the number of states.
Table 21.4 A/D Conversion Characteristics (EXCKS1 = 1: Unit 1)
CKS1 = 0 CKS = 0 Item A/D conversion start delay time Input sampling time A/D conversion time tSPL tCONV 326 120 336 166 60 172 86 30 90 45 15 49 Symbol tD Min. 4 Typ. Max. 14 Min. 4 CKS = 1 Typ. Max. 10 Min. 4 CKS = 0 Typ. Max. 8 Min. 3 CKS1 = 1 CKS = 1 Typ. Max. 7
Note: Values in the table are the number of states.
Table 21.5 A/D Conversion Time (Scan Mode) (Unit 0)
CKS1 0 CKS0 0 1 1 0 1 Conversion Time (Number of States) 512 (fixed) 256 (fixed) 128 (fixed) 64 (fixed)
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Section 21 A/D Converter
Table 21.6 A/D Conversion Time (Scan Mode) (Unit 1)
EXCKS 0 CKS1 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Conversion Time (Number of States) 512 (fixed) 256 (fixed) 128 (fixed) 64 (fixed) 320 (fixed) 160 (fixed) 80 (fixed) 40 (fixed)
21.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. For unit 0, an external trigger is input from the ADTRG0 pin when the TRGS1, TRGS0, and EXTRGS bits are set to B'110 in ADCR_0. For unit 1, an external trigger is input from the ADTRG1 pin when the TRGS1, TRGS0, and EXTRGS bits are set to B'110 in ADCR_1. A/D conversion starts when the ADST bit in ADCSR is set to 1 on the falling edge of the ADTRG pin. Other operations, in both single and scan modes, are the same as when the ADST bit has been set to 1 by software. Figure 21.7 shows the timing. Also, A/D conversion for multiple units can be externally triggered (multiple units can start simultaneously). For units 0 and 1, an external trigger is input from the ADTRG0 pin when the TRGS1, TRGS0, and EXTRGS bits are set to B'111 in ADCR_0 and ADCR_1. A/D conversion starts when the ADST bit in ADCSR is set to 1 on the falling edge of the ADTRG pin. The timing is different from the one when multiple units do not start simultaneously. Figure 21.8 shows the timing.
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Section 21 A/D Converter
P
ADTRG0
Internal trigger signal
ADST A/D conversion
Figure 21.7 External Trigger Input Timing (TRGS1, TRGS0, and EXTRGS B'111)
P
ADTRG0
Internal trigger signal
ADST A/D conversion
Figure 21.8 External Trigger Input Timing when Multiple Units Start Simultaneously (TRSG1, TRGS0, and EXTRGS = B'111)
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Section 21 A/D Converter
21.5
Interrupt Source
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. Setting the ADIE bit to 1 when the ADF bit in ADCSR is set to 1 after A/D conversion is completed enables ADI interrupt requests. The data transfer controller (DTC)* and DMA controller (DMAC) can be activated by an ADI interrupt. Having the converted data read by the DTC* or DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. Note: * Only possible in unit 0. Table 21.7 A/D Converter Interrupt Source
Name ADI0 Note: * Interrupt Source A/D conversion end Only possible in unit 0. Interrupt Flag ADF DTC Activation Possible* DMAC Activation Possible
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Section 21 A/D Converter
21.6
A/D Conversion Accuracy Definitions
This LSI's A/D conversion accuracy definitions are given below. * Resolution The number of A/D converter digital output codes. * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 21.9). * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 21.10). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 21.10). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error (see figure 21.10). * Absolute accuracy The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error.
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Section 21 A/D Converter
Digital output
111 110 101 100 011 010 001 000
Ideal A/D conversion characteristic
Quantization error
1 2 1024 1024
1022 1023 FS 1024 1024 Analog input voltage
Figure 21.9 A/D Conversion Accuracy Definitions
Full-scale error
Digital output
Ideal A/D conversion characteristic
Nonlinearity error Actual A/D conversion characteristic FS Analog input voltage
Offset error
Figure 21.10 A/D Conversion Accuracy Definitions
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Section 21 A/D Converter
21.7
21.7.1
Usage Notes
Module Stop Function Setting
Operation of the A/D converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the A/D converter to be halted. Register access is enabled by clearing the module stop state. Set the CKS1 and CKS2 bits to 1 and clear the ADST, TRGS1, TRGS0, and EXTRGS bits all to 0 to disable A/D conversion when entering module stop state after operation of the A/D converter. After that, set the module stop control register after executing a dummy read by one word. For details, see section 27, Power-Down Modes. 21.7.2 A/D Input Hold Function in Software Standby Mode
When this LSI enters software standby mode with A/D conversion enabled, the analog inputs are retained, and the analog power supply current is equal to as during A/D conversion. If the analog power supply current needs to be reduced in software standby mode, set the CKS1 and CKS2 bits to 1 and clear the ADST, TRGS1, TRGS0, and EXTRGS bits all to 0 to disable A/D conversion. After that, enter software standby mode after executing a dummy read by one word. 21.7.3 Notes on A/D Activation by an External Trigger
If any of actions (1 to 3 below) is performed while activation by an external trigger* is in use, stopping A/D conversion may be impossible. Note: * External trigger refers to input on the ADTRG pin or the conversion trigger from a peripheral module (TMR or TPU). 1. When the setting for activation by an external trigger is in use, writing to change the value of the ADST bit in ADCSR from 0 to 1. 2. Changing the setting from activation by an external trigger to prohibition of external triggers. 3. Changing the scan mode (SCANE and ADSTLCR bits; from continuous scan mode to single mode or single-cycle scan mode) while the setting is for activation by an external trigger. If any of the above points apply, make the corresponding settings listed below. 1. If point 1 is applicable Do not perform writing to change the value of the ADST bit in ADCSR from 0 to 1 when the setting for activation by an external trigger is in use.
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Section 21 A/D Converter
2. If points 2 or 3 is applicable Only execute switching from activation by an external trigger to prohibition of external triggers or changing of the scan mode (ADSTLCR and SCANE bits) when the setting for activation by an external trigger is in use after external trigger input has been disabled. External trigger input can be disabled by writing specific values to bits TRGS1, TRGS0, and EXTRGS. For details on the procedure in cases where point 1 or 3 is applicable, see figure 21.11
Unit 0
Yes
Unit 1
Yes
External trigger halted?
External trigger halted?
No ADCR.TRGS1 = 0 ADCR.TRGS0 = 0 ADCR.EXTRGS = 1 (External trigger disabled)*2
No ADCR.TRGS1 = 0 ADCR.TRGS0 = 1 ADCR.EXTRGS = 1 (External trigger disabled)*1, *2
ADCSR.ADST = 0
ADCSR.ADST = 0
Change the scan mode
Change the scan mode
Change the setting by an external trigger*2
Change the setting by an external trigger*2
Notes: 1. 2.
The TTGE bit in TIER of the TPU unit must be held 0. For details, see section 14.3.4, Timer Interrupt Enable Register (TIER). Rewrite TRGS1, TRGS0, and EXTRGS bits in ADCR simultaneously (in byte unit)
Figure 21.11 Procedure for Changing the Mode When the Setting for Activation by an External Trigger is in Use 21.7.4 Permissible Signal Source Impedance
This LSI's analog input is designed so that the conversion accuracy is guaranteed for an input signal for which the signal source impedance is 5 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k, charging may be insufficient and it
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Section 21 A/D Converter
may not be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is provided externally for conversion in single mode, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater) (see figure 21.11). When converting a high-speed analog signal or conversion in scan mode, a low-impedance buffer should be inserted.
This LSI Sensor output impedance R 5 k Sensor input Low-pass filter C 0.1 F Cin = 15 pF 20 pF Equivalent circuit of the A/D converter 10 k
Figure 21.12 Example of Analog Input Circuit 21.7.5 Influences on Absolute Accuracy
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute accuracy. Be sure to make the connection to an electrically stable GND such as AVss. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, acting as antennas. 21.7.6 Setting Range of Analog Power Supply and Other Pins
If the conditions shown below are not met, the reliability of the LSI may be adversely affected. * Analog input voltage range The voltage applied to analog input pin ANn during A/D conversion should be in the range AVss VAN Vref. * Relation between AVcc, AVss and Vcc, Vss As the relationship between AVcc, AVss and Vcc, Vss, set AVcc = Vcc 0.3 V and AVss = Vss. If the A/D converter is not used, set AVcc = Vcc and AVss = Vss.
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Section 21 A/D Converter
* Vref setting range The reference voltage at the Vref pin should be set in the range Vref AVcc. 21.7.7 Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. Digital circuitry must be isolated from the analog input pins (AN0 to AN7), analog reference power supply (Vref), and analog power supply (AVcc) by the analog ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable ground (Vss) on the board. 21.7.8 Notes on Noise Countermeasures
A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) should be connected between AVcc and AVss as shown in figure 21.13. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to the AN0 to AN7 pins must be connected to AVss. If a filter capacitor is connected, the input currents at the AN0 to AN7 pins are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants.
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Section 21 A/D Converter
AVCC
Vref Rin* 2 *1 *1 0.1 F AVSS Notes: Values are reference values. 1. 10 F 0.01 F 100 AN0 to AN7
2. Rin: Input impedance
Figure 21.13 Example of Analog Input Protection Circuit Table 21.8 Analog Pin Specifications
Item Analog input capacitance Permissible signal source impedance Min. Max. 20 5 Unit pF k
5 k AN0 to AN7 To A/D converter 20 pF
Note: Values are reference values.
Figure 21.14 Analog Input Pin Equivalent Circuit
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Section 22 D/A Converter
Section 22 D/A Converter
22.1
* * * * * *
Features
8-bit resolution Two output channels Maximum conversion time of 10 s (with 20 pF load) Output voltage of 0 V to Vref D/A output hold function in software standby mode Module stop state specifiable
Module data bus
Internal data bus
Vref 8-bit D/A
DA1 DA0 AVSS
Control circuit [Legend] DADR0: D/A data register 0 DADR1: D/A data register 1 DACR01: D/A control register 01
Figure 22.1 Block Diagram of D/A Converter
DACR01
DADR0
DADR1
AVCC
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Bus interface
Section 22 D/A Converter
22.2
Input/Output Pins
Table 22.1 shows the pin configuration of the D/A converter. Table 22.1 Pin Configuration
Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog output pin 0 Analog output pin 1 Symbol AVCC AVSS Vref DA0 DA1 I/O Input Input Input Output Output Function Analog block power supply Analog block ground D/A conversion reference voltage Channel 0 analog output Channel 1 analog output
22.3
Register Descriptions
The D/A converter has the following registers. * D/A data register 0 (DADR0) * D/A data register 1 (DADR1) * D/A control register 01 (DACR01) 22.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)
DADR0 and DADR1 are 8-bit readable/writable registers that store data to which D/A conversion is to be performed. Whenever an analog output is enabled, the values in DADR are converted and output to the analog output pins.
Bit Bit Name Initial Value R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 7 6 5 4 3 2 1 0
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Section 22 D/A Converter
22.3.2
D/A Control Register 01 (DACR01)
DACR01 controls the operation of the D/A converter.
Bit Bit Name Initial Value R/W 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 1 R 3 1 R 2 1 R 1 1 R 0 1 R
Bit 7
Bit Name DAOE1
Initial Value 0
R/W R/W
Description D/A Output Enable 1 Controls D/A conversion and analog output. 0: Analog output of channel 1 (DA1) is disabled 1: D/A conversion of channel 1 is enabled. Analog output of channel 1 (DA1) is enabled.
6
DAOE0
0
R/W
D/A Output Enable 0 Controls D/A conversion and analog output. 0: Analog output of channel 0 (DA0) is disabled 1: D/A conversion of channel 0 is enabled. Analog output of channel 0 (DA0) is enabled.
5
DAE
0
R/W
D/A Enable Used together with the DAOE0 and DAOE1 bits to control D/A conversion. When this bit is cleared to 0, D/A conversion is controlled independently for channels 0 and 1. When this bit is set to 1, D/A conversion for channels 0 and 1 is controlled together. Output of conversion results is always controlled by the DAOE0 and DAOE1 bits. For details, see Table 22.2, Control of D/A Conversion.
4 to 0
All 1
R
Reserved These are read-only bits and cannot be modified.
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Section 22 D/A Converter
Table 22.2 Control of D/A Conversion
Bit 5 DAE 0 Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Description D/A conversion is disabled. D/A conversion of channel 0 is enabled and D/A conversion of channel 1 is disabled. Analog output of channel 0 (DA0) is enabled and analog output of channel 1 (DA1) is disabled. 1 0 D/A conversion of channel 0 is disabled and D/A conversion of channel 1 is enabled. Analog output of channel 0 (DA0) is disabled and analog output of channel 1 (DA1) is enabled. 1 D/A conversion of channels 0 and 1 is enabled. Analog output of channels 0 and 1 (DA0 and DA1) is enabled. 1 0 0 D/A conversion of channels 0 and 1 is enabled. Analog output of channels 0 and 1 (DA0 and DA1) is disabled. 1 D/A conversion of channels 0 and 1 is enabled. Analog output of channel 0 (DA0) is enabled and analog output of channel 1 (DA1) is disabled. 1 0 D/A conversion of channels 0 and 1 is enabled. Analog output of channel 0 (DA0) is disabled and analog output of channel 1 (DA1) is enabled. 1 D/A conversion of channels 0 and 1 is enabled. Analog output of channels 0 and 1 (DA0 and DA1) is enabled.
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Section 22 D/A Converter
22.4
Operation
The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. When the DAOE bit in DACR01 is set to 1, D/A conversion is enabled and the conversion result is output. An operation example of D/A conversion on channel 0 is shown below. Figure 22.2 shows the timing of this operation. 1. Write the conversion data to DADR0. 2. Set the DAOE0 bit in DACR01 to 1 to start D/A conversion. The conversion result is output from the analog output pin DA0 after the conversion time tDCONV has elapsed. The conversion result continues to be output until DADR0 is written to again or the DAOE0 bit is cleared to 0. The output value is expressed by the following formula:
Contents of DADR/256 x Vref
3. If DADR0 is written to again, the conversion is immediately started. The conversion result is output after the conversion time tDCONV has elapsed. 4. If the DAOE0 bit is cleared to 0, analog output is disabled.
DADR0 write cycle DACR01 write cycle DADR0 write cycle DACR01 write cycle
P
Address
DADR0
Conversion data 1
Conversion data 2
DAOE0
DA0 High-impedance state tDCONV
Conversion result 1 tDCONV
Conversion result 2
[Legend] tDCONV: D/A conversion time
Figure 22.2 Example of D/A Converter Operation
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Section 22 D/A Converter
22.5
22.5.1
Usage Notes
Module Stop State Setting
Operation of the D/A converter can be disabled or enabled using the module stop control register. The initial setting is for operation of the D/A converter to be halted. Register access is enabled by clearing the module stop state. For details, refer to section 27, Power-Down Modes. 22.5.2 D/A Output Hold Function in Software Standby Mode
When this LSI makes a transition to software standby mode with D/A conversion enabled, the D/A outputs are retained, and the analog power supply current is equal to as during D/A conversion. If the analog power supply current needs to be reduced in software standby mode, clear the DAOE0, DAOE1, and DAE bits all to 0 to disable D/A conversion. 22.5.3 Notes on Deep Software Standby Mode
When this LSI makes a transition to deep software standby mode, the D/A outputs enter highimpedance state.
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Section 23 RAM
Section 23 RAM
This LSI has a high-speed static RAM. The RAM is connected to the CPU by a 32-bit data bus, enabling one-state access by the CPU to all byte data, word data, and longword data. The RAM can be enabled or disabled by means of the RAME bit in the system control register (SYSCR). For details on SYSCR, refer to section 3.2.2, System Control Register (SYSCR). The RAM size is 56 Kbytes in the H8SX/1658R and H8SX/1658M, and 40 Kbytes in the H8SX/1654R, H8SX/1654M, H8SX/1653R, and H8SX/1653M.
Product Classification Flash memory version H8SX/1653R H8SX/1653M H8SX/1654R H8SX/1654M H8SX/1658R H8SX/1658M 56 Kbytes H'FEE000 to H'FFBFFF 40 Kbytes H'FF2000 to H'FFBFFF RAM Size 40 Kbytes RAM Addresses H'FF2000 to H'FFBFFF
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Section 23 RAM
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Section 24 Flash Memory
Section 24 Flash Memory
The flash memory has the following features. Figure 24.1 is a block diagram of the flash memory.
24.1
Features
* ROM size
Product Classification H8SX/1653 H8SX/1654 H8SX/1658 Part No. R5F61653R R5F61653M R5F61654R R5F61654M R5F61658R R5F61658M ROM Size 384 Kbytes 512 Kbytes 1 Mbyte ROM Address H'000000 to H'05FFFF (modes 1, 2, 3, 6, and 7) H'000000 to H'07FFFF (modes 1, 2, 3, 6, and 7) H'000000 to H'0FFFFF (modes 1, 2, 3, 6, and 7)
* Two memory MATs The start addresses of two memory spaces (memory MATs) are allocated to the same address. The mode setting in the initiation determines which memory MAT is initiated first. The memory MATs can be switched by using the bank-switching method after initiation. User MAT initiated at a reset in user mode: 384 Kbytes/512 Kbytes/1 Mbyte User boot MAT is initiated at reset in user boot mode: 16 Kbytes * Programming/erasing interface by the download of on-chip program This LSI has a programming/erasing program. After downloading this program to the on-chip RAM, programming/erasure can be performed by setting the parameters. * Programming/erasing time Programming time: 1 ms (typ.) for 128-byte simultaneous programming Erasing time: 600 ms (typ.) per 1 block (64 Kbytes) * Number of programming The number of programming can be up to 100 times at the minimum. (1 to 100 times are guaranteed.) * Three on-board programming modes SCI boot mode: Using the on-chip SCI_4, the user MAT and user boot MAT can be programmed/erased. In SCI boot mode, the bit rate between the host and this LSI can be adjusted automatically. USB boot mode: Using the on-chip USB module, the user MAT can be programmed/erased. User programming mode: Using a desired interface, the user MAT can be programmed/erased.
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Section 24 Flash Memory
User boot mode: Using a desired interface, the user boot program can be made and the user MAT can be programmed/erased. * Off-board programming mode Programmer mode: Using a PROM programmer, the user MAT and user boot MAT can be programmed/erased. * Programming/erasing protection Protection against programming/erasure of the flash memory can be set by hardware protection, software protection, or error protection. * Flash memory emulation function using the on-chip RAM Realtime emulation of the flash memory programming can be performed by overlaying parts of the flash memory (user MAT) area and the on-chip RAM.
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Section 24 Flash Memory
Internal address bus
Internal data bus (32 bits)
FCCS FPCS
Module bus
Memory MAT unit User MAT: 384 Kbytes (H8SX/1653) 512 Kbytes (H8SX/1654) 1 Mbyte (H8SX/1658) User boot MAT: 16 Kbytes
FECS FKEY FMATS FTDAR RAMER Control unit
Flash memory
Mode pins
Operating mode
[Legend] FCCS: FPCS: FECS: FKEY: FMATS: FTDAR: RAMER:
Flash code control/status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register RAM emulation register
Figure 24.1 Block Diagram of Flash Memory
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Section 24 Flash Memory
24.2
Mode Transition Diagram
When the mode pins are set in the reset state and reset start is performed, this LSI enters each operating mode as shown in figure 24.2. Although the flash memory can be read in user mode, it cannot be programmed or erased. The flash memory can be programmed or erased in boot mode, user programming mode, user boot mode, and programmer mode. The differences between boot mode, user programming mode, user boot mode, and programmer mode are shown in table 24.1.
RES = 0 RES = 0
ROM disabled mode
ROM disabled mode setting
Reset state
Programmer mode setting
Programmer mode
RE S
0 g ttin S= se RE de mo er Us
SC I
=0
bo o
RE S
tm od
=0 S RE ot g bo ttin er se Us ode m
=0
ett
US B
es
ing
RE S= boo 0 tm ode set tin
g
USB boot mode
*2
User mode
*1
User program mode
User boot mode
SCI boot mode
RAM emulation can be available On-board programming mode Notes: 1. Programming and erasure is started. 2. Programing and erasure is completed.
Figure 24.2 Mode Transition of Flash Memory
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Section 24 Flash Memory
Table 24.1 Differences between Boot Mode, User Programming Mode, User Boot Mode, and Programmer Mode
SCI Boot Mode On-board programming User MAT User boot MAT Command O (Automatic) O*
1
Item Programming/ erasing environment
USB Boot Mode On-board programming * User MAT
User Programming Mode On-board programming * User MAT
Programmer User Boot Mode Mode On-board programming * User MAT Off-board programming * * User MAT User boot MAT
Programming/ * erasing enable * MAT
Programming/ Command erasing control All erasure Block division erasure Program data transfer O (Automatic) O*
1
Programming/ Programming/ erasing interface erasing interface O O O O From desired device via RAM O User boot MAT*
2
Command O (Automatic) x Via programmer x
From host via SCI From host via USB From desired device via RAM x Embedded program storage area Changing mode and reset O User MAT
RAM emulation x Reset initiation Embedded MAT program storage area Transition to user mode Changing mode and reset
Completing Programming/ 3 erasure*
Changing mode and reset
Notes: 1. All-erasure is performed. After that, the specified block can be erased. 2. First, the reset vector is fetched from the embedded program storage area. After the flash memory related registers are checked, the reset vector is fetched from the user boot MAT. 3. In this LSI, the user programming mode is defined as the period from the timing when a program concerning programming and erasure is started to the timing when the program is completed. For details on a program concerning programming and erasure, see section 24.8.3, User Programming Mode.
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Section 24 Flash Memory
24.3
Memory MAT Configuration
The memory MATs of flash memory in this LSI consists of the 384-Kbyte/512-Kbyte/1-Mbyte user MAT and 16-Kbyte user boot MAT. The start addresses of the user MAT and user boot MAT are allocated to the same address. Therefore, when the program execution or data access is performed between the two memory MATs, the memory MATs must be switched by the flash MAT select register (FMATS). The user MAT or user boot MAT can be read in all modes. However, the user boot MAT can be programmed or erased only in boot mode and programmer mode. The size of the user MAT is different from that of the user boot MAT. Addresses which exceed the size of the 16-Kbyte user boot MAT should not be accessed. If an attempt is made, data is read as an undefined value.
User MAT H'000000
H'000000
16 Kbytes
User boot MAT
H'003FFF
512 Kbytes*1
H'07FFFF*2 Notes: 1. 384 Kbytes in the H8SX/1653. 1 Mbyte in the H8SX/1658. 2. H'05FFFF in the H8SX/1653. H'0FFFFF in the H8SX/1658.
Figure 24.3 Memory MAT Configuration (H8SX/1654)
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Section 24 Flash Memory
24.4
24.4.1
Block Structure
Block Diagram of H8SX/1653
Figure 24.4 (1) shows the block structure of the 384-kbyte user MAT. The heavy-line frames indicate the erase blocks. The thin-line frames indicate the programming units and the values inside the frames stand for the addresses. The user MAT is divided into five 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. The user MAT can be erased in these divided block units. Programming is done in 128-byte units starting from where the lower address is H'00 or H'80. RAM emulation can be performed in the eight 4-kbyte blocks.
Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes -------------- Programming unit: 128 bytes
EB0 Erase unit: 4 kbytes EB1 Erase unit: 4 kbytes EB2 Erase unit: 4 kbytes EB3 Erase unit: 4 kbytes EB4 Erase unit: 4 kbytes EB5 Erase unit: 4 kbytes EB6 Erase unit: 4 kbytes EB7 Erase unit: 4 kbytes EB8 Erase unit: 32 kbytes EB9 Erase unit: 64 kbytes EB10
H'000000 H'000001 H'000002 H'000F80 H'000F81 H'000F82 H'001000 H'001001 H'001002 H'001F80 H'001F81 H'001F82 H'002000 H'002001 H'002002 H'002F80 H'002F81 H'002F82 H'003000 H'003001 H'003002 H'003F80 H'003F81 H'003F82 H'004000 H'004001 H'004002 H'004F80 H'004F81 H'004F82 H'005000 H'005001 H'005002 H'005F80 H'005F81 H'005F82 H'006000 H'006001 H'006002 H'006F80 H'006F81 H'006F82 H'007000 H'007001 H'007002 H'007F80 H'007F81 H'007F82 H'008000 H'008001 H'008002 H'00FF80 H'00FF81 H'00FF82 H'010000 H'010001 H'010002 H'01FF80 H'01FF81 H'01FF82 H'020000 H'020001 H'020002 H'0AFF80 H'0AFF81 H'0AFF82 H'050000 H'050001 H'050002 H'05FF80 H'05FF81 H'05FF82
H'00007F H'000FFF H'00107F H'001FFF H'00207F H'002FFF H'00307F H'003FFF H'00407F H'004FFF H'00507F H'005FFF H'00607F H'006FFF H'00707F H'007FFF H'00807F H'00FFFF H'01007F H'01FFFF H'02007F
EB13 Erase unit: 64 kbytes
- - - - - - - - - - - - - - H'0AFFFF Programming unit: 128 bytes H'05007F -------------- H'05FFFF
Figure 24.4 (1) User MAT Block Structure of H8SX/1653
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Section 24 Flash Memory
24.4.2
Block Diagram of H8SX/1654
Figure 24.4 (2) shows the block structure of the 512-Kbyte user MAT. The heavy-line frames indicate the erase blocks. The thin-line frames indicate the programming units and the values inside the frames stand for the addresses. The user MAT is divided into seven 64-Kbyte blocks, one 32-Kbyte block, and eight 4-Kbyte blocks. The user MAT can be erased in these divided block units. Programming is done in 128-byte units starting from where the lower address is H'00 or H'80. RAM emulation can be performed in the eight 4-Kbyte blocks.
EB0 Erase unit: 4 Kbytes EB1 Erase unit: 4 Kbytes EB2 Erase unit: 4 Kbytes EB3 Erase unit: 4 Kbytes EB4 Erase unit: 4 Kbytes EB5 Erase unit: 4 Kbytes EB6 Erase unit: 4 Kbytes EB7 Erase unit: 4 Kbytes EB8 Erase unit: 32 Kbytes EB9 Erase unit: 64 Kbytes
EB10
H'000000 H'000001 H'000002 H'000F80 H'000F81 H'000F82 H'001000 H'001001 H'001002 H'001F80 H'001F81 H'001F82 H'002000 H'002001 H'002002 H'002F80 H'002F81 H'002F82 H'003000 H'003001 H'003002 H'003F80 H'003F81 H'003F82 H'004000 H'004001 H'004002 H'004F80 H'004F81 H'004F82 H'005000 H'005001 H'005002 H'005F80 H'005F81 H'005F82 H'006000 H'006001 H'006002 H'006F80 H'006F81 H'006F82 H'007000 H'007001 H'007002 H'007F80 H'007F81 H'007F82 H'008000 H'008001 H'008002 H'00FF80 H'00FF81 H'00FF82 H'010000 H'010001 H'010002 H'01FF80 H'01FF81 H'01FF82 H'020000 H'020001 H'020002
Programming unit: 128 bytes
----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes
H'00007F H'000FFF H'00107F H'001FFF H'00207F H'002FFF H'00307F H'003FFF H'00407F H'004FFF H'00507F H'005FFF H'00607F H'006FFF H'00707F H'007FFF H'00807F H'00FFFF H'01007F H'01FFFF H'02007F
EB15 Erase unit: 64 Kbytes
----------- H'0AFF80 H'0AFF81 H'0AFF82 H'070000 H'070001 H'070002 Programming unit: 128 bytes
H'07007F H'07FFFF
H'07FF80 H'07FF81 H'07FF82
-----------
Figure 24.4 (2) User MAT Block Structure of H8SX/1654
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Section 24 Flash Memory
24.4.3
Block Diagram of H8SX/1658
Figure 24.4 (3) shows the block structure of the 1-Mbyte user MAT. The heavy-line frames indicate the erase blocks. The thin-line frames indicate the programming units and the values inside the frames stand for the addresses. The user MAT is divided into fifteen 64-Kbyte blocks, one 32-Kbyte block, and eight 4-Kbyte blocks. The user MAT can be erased in these divided block units. Programming is done in 128-byte units starting from where the lower address is H'00 or H'80. RAM emulation can be performed in the eight 4-Kbyte blocks.
EB0 Erase unit: 4 Kbytes EB1 Erase unit: 4 Kbytes EB2 Erase unit: 4 Kbytes EB3 Erase unit: 4 Kbytes EB4 Erase unit: 4 Kbytes EB5 Erase unit: 4 Kbytes EB6 Erase unit: 4 Kbytes EB7 Erase unit: 4 Kbytes EB8 Erase unit: 32 Kbytes EB9 Erase unit: 64 Kbytes EB10 Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes ----------- Programming unit: 128 bytes
H'000000 H'000001 H'000002 H'000F80 H'000F81 H'000F82 H'001000 H'001001 H'001002 H'001F80 H'001F81 H'001F82 H'002000 H'002001 H'002002 H'002F80 H'002F81 H'002F82 H'003000 H'003001 H'003002 H'003F80 H'003F81 H'003F82 H'004000 H'004001 H'004002 H'004F80 H'004F81 H'004F82 H'005000 H'005001 H'005002 H'005F80 H'005F81 H'005F82 H'006000 H'006001 H'006002 H'006F80 H'006F81 H'006F82 H'007000 H'007001 H'007002 H'007F80 H'007F81 H'007F82 H'008000 H'008001 H'008002 H'00FF80 H'00FF81 H'00FF82 H'010000 H'010001 H'010002 H'01FF80 H'01FF81 H'01FF82 H'020000 H'020001 H'020002
H'00007F H'000FFF H'00107F H'001FFF H'00207F H'002FFF H'00307F H'003FFF H'00407F H'004FFF H'00507F H'005FFF H'00607F H'006FFF H'00707F H'007FFF H'00807F H'00FFFF H'01007F H'01FFFF H'02007F
EB23 Erase unit: 64 Kbytes
----------- H'0EFF80 H'0EFF81 H'0EFF82 H'0F0000 H'0F0001 H'0F0002 Programming unit: 128 bytes H'0FFF80 H'0FFF81 H'0FFF82 -----------
H'0F007F H'0FFFFF
Figure 24.4 (3) User MAT Block Structure of H8SX/1658
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Section 24 Flash Memory
24.5
Programming/Erasing Interface
Programming/erasure of the flash memory is done by downloading an on-chip programming/ erasing program to the on-chip RAM and specifying the start address of the programming destination, the program data, and the erase block number using the programming/erasing interface registers and programming/erasing interface parameters. The procedure program for user programming mode and user boot mode is made by the user. Figure 24.5 shows the procedure for creating the procedure program. For details, see section 24.8.3, User Programming Mode.
Start procedure program for programming/erasing Select on-chip program to be downloaded and specify destination Download on-chip program by setting VBR, FKEY, and SCO bit in FCCS
Execute initialization (downloaded program execution)
Programming (in 128-byte units) or erasing (in 1-block units) (downloaded program execution)
Programming/erasing completed? Yes End procedure program
No
Figure 24.5 Procedure for Creating Procedure Program (1) Selection of On-Chip Program to be Downloaded
This LSI has programming/erasing programs which can be downloaded to the on-chip RAM. The on-chip program to be downloaded is selected by the programming/erasing interface registers. The start address of the on-chip RAM where an on-chip program is downloaded is specified by the flash transfer destination address register (FTDAR).
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Section 24 Flash Memory
(2)
Download of On-Chip Program
The on-chip program is automatically downloaded by setting the flash key code register (FKEY) and the SCO bit in the flash code control/status register (FCCS) after initializing the vector base register (VBR). The memory MAT is replaced with the embedded program storage area during download. Since the memory MAT cannot be read during programming/erasing, the procedure program must be executed in a space other than the flash memory (for example, on-chip RAM). Since the download result is returned to the programming/erasing interface parameter, whether download is normally executed or not can be confirmed. The VBR contents can be changed after completion of download. (3) Initialization of Programming/Erasure
A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU needs to be set before programming/erasure. The operating frequency of the CPU is set by the programming/erasing interface parameter. (4) Execution of Programming/Erasure
The start address of the programming destination and the program data are specified in 128-byte units when programming. The block to be erased is specified with the erase block number in erase-block units when erasing. Specifications of the start address of the programming destination, program data, and erase block number are performed by the programming/erasing interface parameters, and the on-chip program is initiated. The on-chip program is executed by using the JSR or BSR instruction and executing the subroutine call of the specified address in the on-chip RAM. The execution result is returned to the programming/erasing interface parameter. The area to be programmed must be erased in advance when programming flash memory. All interrupts are disabled during programming/erasure. (5) When Programming/Erasure is Executed Consecutively
When processing does not end by 128-byte programming or 1-block erasure, consecutive programming/erasure can be realized by updating the start address of the programming destination and program data, or the erase block number. Since the downloaded on-chip program is left in the on-chip RAM even after programming/erasure completes, download and initialization are not required when the same processing is executed consecutively.
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Section 24 Flash Memory
24.6
Input/Output Pins
The flash memory is controlled through the input/output pins shown in table 24.2. Table 24.2 Pin Configuration
Abbreviation RES EMLE MD2 to MD0 PM2 TxD4 RxD4 USD+, USDVBUS PM3 PM4 I/O Input Input Input Input Output Input Input/output Input Input Output Function Reset On-chip emulator enable pin (EMLE = 0 for flash memory programming/erasure) Set operating mode of this LSI SCI boot/USB boot mode setting (valid when boot mode is selected by the MD2 to MD0 pins) Serial transmit data output (used in SCI boot mode) Serial receive data input (used in SCI boot mode) USB data input/output (used in USB boot mode) USB cable connect/disconnect detection (used in USB boot mode) USB bus-power/self-power mode setting (used in USB boot mode) D+ pull-up control (used in USB boot mode)
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Section 24 Flash Memory
24.7
Register Descriptions
The flash memory has the following registers. Programming/Erasing Interface Registers: * * * * * * Flash code control/status register (FCCS) Flash program code select register (FPCS) Flash erase code select register (FECS) Flash key code register (FKEY) Flash MAT select register (FMATS) Flash transfer destination address register (FTDAR)
Programming/Erasing Interface Parameters: * * * * * * Download pass and fail result parameter (DPFR) Flash pass and fail result parameter (FPFR) Flash program/erase frequency parameter (FPEFEQ) Flash multipurpose address area parameter (FMPAR) Flash multipurpose data destination area parameter (FMPDR) Flash erase block select parameter (FEBS)
* RAM emulation register (RAMER) There are several operating modes for accessing the flash memory. Respective operating modes, registers, and parameters are assigned to the user MAT and user boot MAT. The correspondence between operating modes and registers/parameters for use is shown in table 24.3.
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Section 24 Flash Memory
Table 24.3 Registers/Parameters and Target Modes
Register/Parameter Programming/ erasing interface registers FCCS FPCS FECS FKEY FMATS FTDAR Programming/ erasing interface parameters DPFR FPFR Download O O O O O O Initialization O O Programming Erasure O O* O O O
1
Read
RAM Emulation
O O* O O
1
O*
2
O
FPEFEQ FMPAR FMPDR FEBS
RAM emulation
RAMER
Notes: 1. The setting is required when programming or erasing the user MAT in user boot mode. 2. The setting may be required according to the combination of initiation mode and read target memory MAT.
24.7.1
Programming/Erasing Interface Registers
The programming/erasing interface registers are 8-bit registers that can be accessed only in bytes. These registers are initialized by a reset. (1) Flash Code Control/Status Register (FCCS)
FCCS monitors errors during programming/erasing the flash memory and requests the on-chip program to be downloaded to the on-chip RAM.
Bit Bit Name Initial Value R/W 7 1 R 6 0 R 5 0 R 4 FLER 0 R 3 0 R 2 0 R 1 0 R 0 SCO 0 (R)/W*
Note: * This is a write-only bit. This bit is always read as 0.
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Section 24 Flash Memory
Bit 7 6 5 4
Initial Bit Name Value FLER 1 0 0 0
R/W R R R R
Description Reserved These are read-only bits and cannot be modified. Flash Memory Error Indicates that an error has occurred during programming or erasing the flash memory. When this bit is set to 1, the flash memory enters the error protection state. When this bit is set to 1, high voltage is applied to the internal flash memory. To reduce the damage to the flash memory, the reset must be released after the reset input period (period of RES = 0) of at least 100 s. 0: Flash memory operates normally (Error protection is invalid) [Clearing condition] * At a reset 1: An error occurs during programming/erasing flash memory (Error protection is valid) [Setting conditions] * * When an interrupt, such as NMI, occurs during programming/erasure. When the flash memory is read during programming/erasure (including a vector read and an instruction fetch). When the SLEEP instruction is executed during programming/erasure (including software standby mode). When a bus master other than the CPU, such as the DMAC and DTC, obtains bus mastership during programming/erasure.
*
*
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Section 24 Flash Memory
Bit 3 to 1 0
Initial Bit Name Value SCO All 0 0
R/W R (R)/W*
Description Reserved These are read-only bits and cannot be modified. Source Program Copy Operation Requests the on-chip programming/erasing program to be downloaded to the on-chip RAM. When this bit is set to 1, the on-chip program which is selected by FPCS or FECS is automatically downloaded in the on-chip RAM area specified by FTDAR. In order to set this bit to 1, the RAM emulation mode must be canceled, H'A5 must be written to FKEY, and this operation must be executed in the on-chip RAM. Dummy read of FCCS must be executed twice immediately after setting this bit to 1. All interrupts must be disabled during download. This bit is cleared to 0 when download is completed. During program download initiated with this bit, particular processing which accompanies bankswitching of the program storage area is executed. Before a download request, initialize the VBR contents to H'00000000. After download is completed, the VBR contents can be changed. 0: Download of the programming/erasing program is not requested. [Clearing condition] * When download is completed 1: Download of the programming/erasing program is requested. [Setting conditions] (When all of the following conditions are satisfied) * * * Not in RAM emulation mode (the RAMS bit in RAMER is cleared to 0) H'A5 is written to FKEY Setting of this bit is executed in the on-chip RAM
Note:
*
This is a write-only bit. This bit is always read as 0.
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Section 24 Flash Memory
(2)
Flash Program Code Select Register (FPCS)
FPCS selects the programming program to be downloaded.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 PPVS 0 R/W
Bit 7 to 1 0
Initial Bit Name Value PPVS All 0 0
R/W R R/W
Description Reserved These are read-only bits and cannot be modified. Program Pulse Verify Selects the programming program to be downloaded. 0: Programming program is not selected. [Clearing condition] When transfer is completed 1: Programming program is selected.
(3)
Flash Erase Code Select Register (FECS)
FECS selects the erasing program to be downloaded.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 EPVB 0 R/W
Bit 7 to 1 0
Initial Bit Name Value EPVB All 0 0
R/W R R/W
Description Reserved These are read-only bits and cannot be modified. Erase Pulse Verify Block Selects the erasing program to be downloaded. 0: Erasing program is not selected. [Clearing condition] When transfer is completed 1: Erasing program is selected.
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Section 24 Flash Memory
(4)
Flash Key Code Register (FKEY)
FKEY is a register for software protection that enables to download the on-chip program and perform programming/erasure of the flash memory.
Bit Bit Name Initial Value R/W 7 K7 0 R/W 6 K6 0 R/W 5 K5 0 R/W 4 K4 0 R/W 3 K3 0 R/W 2 K2 0 R/W 1 K1 0 R/W 0 K0 0 R/W
Bit 7 6 5 4 3 2 1 0
Initial Bit Name Value K7 K6 K5 K4 K3 K2 K1 K0 0 0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description Key Code When H'A5 is written to FKEY, writing to the SCO bit in FCCS is enabled. When a value other than H'A5 is written, the SCO bit cannot be set to 1. Therefore, the on-chip program cannot be downloaded to the on-chip RAM. Only when H'5A is written can programming/erasure of the flash memory be executed. When a value other than H'5A is written, even if the programming/erasing program is executed, programming/erasure cannot be performed. H'A5: Writing to the SCO bit is enabled. (The SCO bit cannot be set to 1 when FKEY is a value other than H'A5.) H'5A: Programming/erasure of the flash memory is enabled. (When FKEY is a value other than H'A5, the software protection state is entered.) H'00: Initial value
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Section 24 Flash Memory
(5)
Flash MAT Select Register (FMATS)
FMATS selects the user MAT or user boot MAT. Writing to FMATS should be done when a program in the on-chip RAM is being executed.
Bit Bit Name Initial Value R/W
7 MS7 0/1* R/W
6 MS6 0 R/W
5 MS5 0/1* R/W
4 MS4 0 R/W
3 MS3 0/1* R/W
2 MS2 0 R/W
1 MS1 0/1* R/W
0 MS0 0 R/W
Note: * This bit is set to 1 in user boot mode, otherwise cleared to 0.
Bit 7 6 5 4 3 2 1 0
Initial Bit Name Value MS7 MS6 MS5 MS4 MS3 MS2 MS1 MS0 0/1* 0 0/1* 0 0/1* 0 0/1* 0
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Description MAT Select The memory MATs can be switched by writing a value to FMATS. When H'AA is written to FMATS, the user boot MAT is selected. When a value other than H'AA is written, the user MAT is selected. Switch the MATs following the memory MAT switching procedure in section 24.11, Switching between User MAT and User Boot MAT. The user boot MAT cannot be selected by FMATS in user programming mode. The user boot MAT can be selected in boot mode or programmer mode. H'AA: The user boot MAT is selected. (The user MAT is selected when FMATS is a value other than H'AA.) (Initial value when initiated in user boot mode.) H'00: The user MAT is selected. (Initial value when initiated in a mode except for user boot mode.)
Note:
*
This bit is set to 1 in user boot mode, otherwise cleared to 0.
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Section 24 Flash Memory
(6)
Flash Transfer Destination Address Register (FTDAR)
FTDAR specifies the start address of the on-chip RAM at which to download an on-chip program. FTDAR must be set before setting the SCO bit in FCCS to 1.
Bit Bit Name Initial Value R/W 7 TDER 0 R/W 6 TDA6 0 R/W 5 TDA5 0 R/W 4 TDA4 0 R/W 3 TDA3 0 R/W 2 TDA2 0 R/W 1 TDA1 0 R/W 0 TDA0 0 R/W
Bit 7
Initial Bit Name Value TDER 0
R/W R/W
Description Transfer Destination Address Setting Error This bit is set to 1 when an error has occurred in setting the start address specified by bits TDA6 to TDA0. A start address error is determined by whether the value set in bits TDA6 to TDA0 is within the range of H'00 to H'02 when download is executed by setting the SCO bit in FCCS to 1. Make sure that this bit is cleared to 0 before setting the SCO bit to 1 and the value specified by bits TDA6 to TDA0 should be within the range of H'00 to H'02. 0: The value specified by bits TDA6 to TDA0 is within the range. 1: The value specified by bits TDA6 to TDA0 is between H'03 and H'FF and download has stopped.
6 5 4 3 2 1 0
TDA6 TDA5 TDA4 TDA3 TDA2 TDA1 TDA0
0 0 0 0 0 0 0
R/W R/W R/W R/W R/W R/W R/W
Transfer Destination Address Specifies the on-chip RAM start address of the download destination. A value between H'00 and H'02, and up to 4 Kbytes can be specified as the start address of the on-chip RAM. H'00: H'FF9000 is specified as the start address. H'01: H'FFA000 is specified as the start address. H'02: H'FFB000 is specified as the start address. H'03 to H'7F: Setting prohibited. (Specifying a value from H'03 to H'7F sets the TDER bit to 1 and stops download of the on-chip program.)
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Section 24 Flash Memory
24.7.2
Programming/Erasing Interface Parameters
The programming/erasing interface parameters specify the operating frequency, storage place for program data, start address of programming destination, and erase block number, and exchanges the execution result. These parameters use the general registers of the CPU (ER0 and ER1) or the on-chip RAM area. The initial values of programming/erasing interface parameters are undefined at a reset or a transition to software standby mode. Since registers of the CPU except for ER0 and ER1 are saved in the stack area during download of an on-chip program, initialization, programming, or erasing, allocate the stack area before performing these operations (the maximum stack size is 128 bytes). The return value of the processing result is written in R0. The programming/erasing interface parameters are used in download control, initialization before programming or erasing, programming, and erasing. Table 24.4 shows the usable parameters and target modes. The meaning of the bits in the flash pass and fail result parameter (FPFR) varies in initialization, programming, and erasure. Table 24.4 Parameters and Target Modes
Parameter DPFR FPFR FPEFEQ FMPAR FMPDR FEBS Download Initialization Programming Erasure R/W R/W R/W R/W R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined Allocation On-chip RAM* R0L of CPU ER0 of CPU ER1 of CPU ER0 of CPU ER0 of CPU
O O *
O O
O O O
O O
Note:
A single byte of the start address of the on-chip RAM specified by FTDAR
Download Control: The on-chip program is automatically downloaded by setting the SCO bit in FCCS to 1. The on-chip RAM area to download the on-chip program is the 4-Kbyte area starting from the start address specified by FTDAR. Download is set by the programming/erasing interface registers, and the download pass and fail result parameter (DPFR) indicates the return value.
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Section 24 Flash Memory
Initialization before Programming/Erasure: The on-chip program includes the initialization program. A pulse with the specified period must be applied when programming or erasing. The specified pulse width is made by the method in which wait loop is configured by the CPU instruction. Accordingly, the operating frequency of the CPU must be set. The initial program is set as a parameter of the programming/erasing program which has been downloaded to perform these settings. Programming: When the flash memory is programmed, the start address of the programming destination on the user MAT and the program data must be passed to the programming program. The start address of the programming destination on the user MAT must be stored in general register ER1. This parameter is called the flash multipurpose address area parameter (FMPAR). The program data is always in 128-byte units. When the program data does not satisfy 128 bytes, 128-byte program data is prepared by filling the dummy code (H'FF). The boundary of the start address of the programming destination on the user MAT is aligned at an address where the lower eight bits (A7 to A0) are H'00 or H'80. The program data for the user MAT must be prepared in consecutive areas. The program data must be in a consecutive space which can be accessed using the MOV.B instruction of the CPU and is not in the flash memory space. The start address of the area that stores the data to be written in the user MAT must be set in general register ER0. This parameter is called the flash multipurpose data destination area parameter (FMPDR). For details on the programming procedure, see section 24.8.3, User Programming Mode. Erasure: When the flash memory is erased, the erase block number on the user MAT must be passed to the erasing program which is downloaded. The erase block number on the user MAT must be set in general register ER0. This parameter is called the flash erase block select parameter (FEBS). One block is selected from the block numbers of 0 to 19 as the erase block number. For details on the erasing procedure, see section 24.8.3, User Programming Mode.
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Section 24 Flash Memory
(1)
Download Pass and Fail Result Parameter (DPFR: Single Byte of Start Address in OnChip RAM Specified by FTDAR)
DPFR indicates the return value of the download result. The DPFR value is used to determine the download result.
Bit Bit Name 7 6 5 4 3 2 SS 1 FK 0 SF
Bit 7 to 3 2
Initial Bit Name Value SS
R/W R/W
Description Unused These bits return 0. Source Select Error Detect Only one type can be specified for the on-chip program which can be downloaded. When the program to be downloaded is not selected, more than two types of programs are selected, or a program which is not mapped is selected, an error occurs. 0: Download program selection is normal 1: Download program selection is abnormal
1
FK
R/W
Flash Key Register Error Detect Checks the FKEY value (H'A5) and returns the result. 0: FKEY setting is normal (H'A5) 1: FKEY setting is abnormal (value other than H'A5)
0
SF
R/W
Success/Fail Returns the download result. Reads back the program downloaded to the on-chip RAM and determines whether it has been transferred to the on-chip RAM. 0: Download of the program has ended normally (no error) 1: Download of the program has ended abnormally (error occurs)
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Section 24 Flash Memory
(2)
Flash Pass and Fail Parameter (FPFR: General Register R0L of CPU)
FPFR indicates the return values of the initialization, programming, and erasure results. The meaning of the bits in FPFR varies depending on the processing. (a) Initialization before Programming/Erasure
FPFR indicates the return value of the initialization result.
Bit Bit Name 7 6 5 4 3 2 1 FQ 0 SF
Bit 7 to 2 1
Initial Bit Name Value FQ
R/W R/W
Description Unused These bits return 0. Frequency Error Detect Compares the specified CPU operating frequency with the operating frequencies supported by this LSI, and returns the result. 0: Setting of operating frequency is normal 1: Setting of operating frequency is abnormal
0
SF
R/W
Success/Fail Returns the initialization result. 0: Initialization has ended normally (no error) 1: Initialization has ended abnormally (error occurs)
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Section 24 Flash Memory
(b)
Programming
FPFR indicates the return value of the programming result.
Bit Bit Name 7 6 MD 5 EE 4 FK 3 2 WD 1 WA 0 SF
Bit 7 6
Initial Bit Name Value MD
R/W R/W
Description Unused Returns 0. Programming Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS. For conditions to enter the error protection state, see section 24.9.3, Error Protection. 0: Normal operation (FLER = 0) 1: Error protection state, and programming cannot be performed (FLER = 1)
5
EE
R/W
Programming Execution Error Detect Writes 1 to this bit when the specified data could not be written because the user MAT was not erased. If this bit is set to 1, there is a high possibility that the user MAT has been written to partially. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when programming is performed. In this case, both the user MAT and user boot MAT have not been written to. Programming the user boot MAT should be performed in boot mode or programmer mode. 0: Programming has ended normally 1: Programming has ended abnormally (programming result is not guaranteed)
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Section 24 Flash Memory
Bit 4
Initial Bit Name Value FK
R/W R/W
Description Flash Key Register Error Detect Checks the FKEY value (H'5A) before programming starts, and returns the result. 0: FKEY setting is normal (H'5A) 1: FKEY setting is abnormal (value other than H'5A)
3 2
WD

R/W
Unused Returns 0. Write Data Address Detect When an address not in the flash memory area is specified as the start address of the storage destination for the program data, an error occurs. 0: Setting of the start address of the storage destination for the program data is normal 1: Setting of the start address of the storage destination for the program data is abnormal
1
WA
R/W
Write Address Error Detect When the following items are specified as the start address of the programming destination, an error occurs. * * An area other than flash memory The specified address is not aligned with the 128byte boundary (lower eight bits of the address are other than H'00 and H'80)
0: Setting of the start address of the programming destination is normal 1: Setting of the start address of the programming destination is abnormal 0 SF R/W Success/Fail Returns the programming result. 0: Programming has ended normally (no error) 1: Programming has ended abnormally (error occurs)
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Section 24 Flash Memory
(c)
Erasure
FPFR indicates the return value of the erasure result.
Bit Bit Name 7 6 MD 5 EE 4 FK 3 EB 2 1 0 SF
Bit 7 6
Initial Bit Name Value MD
R/W R/W
Description Unused Returns 0. Erasure Mode Related Setting Error Detect Detects the error protection state and returns the result. When the error protection state is entered, this bit is set to 1. Whether the error protection state is entered or not can be confirmed with the FLER bit in FCCS. For conditions to enter the error protection state, see section 24.9.3, Error Protection. 0: Normal operation (FLER = 0) 1: Error protection state, and programming cannot be performed (FLER = 1)
5
EE
R/W
Erasure Execution Error Detect Returns 1 when the user MAT could not be erased or when the flash memory related register settings are partially changed. If this bit is set to 1, there is a high possibility that the user MAT has been erased partially. In this case, after removing the error factor, erase the user MAT. If FMATS is set to H'AA and the user boot MAT is selected, an error occurs when erasure is performed. In this case, both the user MAT and user boot MAT have not been erased. Erasing of the user boot MAT should be performed in boot mode or programmer mode. 0: Erasure has ended normally 1: Erasure has ended abnormally
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Section 24 Flash Memory
Bit 4
Initial Bit Name Value FK
R/W R/W
Description Flash Key Register Error Detect Checks the FKEY value (H'5A) before erasure starts, and returns the result. 0: FKEY setting is normal (H'5A) 1: FKEY setting is abnormal (value other than H'5A)
3
EB
R/W
Erase Block Select Error Detect Checks whether the specified erase block number is in the block range of the user MAT, and returns the result. 0: Setting of erase block number is normal 1: Setting of erase block number is abnormal
2, 1 0
SF

R/W
Unused These bits return 0. Success/Fail Indicates the erasure result. 0: Erasure has ended normally (no error) 1: Erasure has ended abnormally (error occurs)
(3)
Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU)
FPEFEQ sets the operating frequency of the CPU. The operating frequency available in this LSI ranges from 8 MHz to 50 MHz.
Bit Bit Name Bit Bit Name Bit Bit Name Bit Bit Name 31 23 15 F15 7 F7 30 22 14 F14 6 F6 29 21 13 F13 5 F5 28 20 12 F12 4 F4 27 19 11 F11 3 F3 26 18 10 F10 2 F2 25 17 9 F9 1 F1 24 16 8 F8 0 F0
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Section 24 Flash Memory
Bit
Initial Bit Name Value
R/W R/W
Description Unused These bits should be cleared to 0. Frequency Set These bits set the operating frequency of the CPU. When the PLL multiplication function is used, set the multiplied frequency. The setting value must be calculated as follows: 1. The operating frequency shown in MHz units must be rounded in a number of three decimal places and be shown in a number of two decimal places. 2. The value multiplied by 100 is converted to the binary digit and is written to FPEFEQ (general register ER0). For example, when the operating frequency of the CPU is 35.000 MHz, the value is as follows: 1. The number of three decimal places of 35.000 is rounded. 2. The formula of 35.00 x 100 = 3500 is converted to the binary digit and B'0000 1101 1010 1100 (H'0DAC) is set to ER0.
31 to 16 15 to 0
F15 to F0
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Section 24 Flash Memory
(4)
Flash Multipurpose Address Area Parameter (FMPAR: General Register ER1 of CPU)
FMPAR stores the start address of the programming destination on the user MAT. When an address in an area other than the flash memory is set, or the start address of the programming destination is not aligned with the 128-byte boundary, an error occurs. The error occurrence is indicated by the WA bit in FPFR.
Bit Bit Name 31 MOA31 30 MOA30 29 MOA29 28 MOA28 27 MOA27 26 MOA26 25 MOA25 24 MOA24
Bit Bit Name
23 MOA23
22 MOA22
21 MOA21
20 MOA20
19 MOA19
18 MOA18
17 MOA17
16 MOA16
Bit Bit Name
15 MOA15
14 MOA14
13 MOA13
12 MOA12
11 MOA11
10 MOA10
9 MOA9
8 MOA8
Bit Bit Name
7 MOA7
6 MOA6
5 MOA5
4 MOA4
3 MOA3
2 MOA2
1 MOA1
0 MOA0
Bit 31 to 0
Initial Bit Name Value MOA31 to MOA0
R/W R/W
Description These bits store the start address of the programming destination on the user MAT. Consecutive 128-byte programming is executed starting from the specified start address of the user MAT. Therefore, the specified start address of the programming destination becomes a 128-byte boundary, and MOA6 to MOA0 are always cleared to 0.
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Section 24 Flash Memory
(5)
Flash Multipurpose Data Destination Parameter (FMPDR: General Register ER0 of CPU)
FMPDR stores the start address in the area which stores the data to be programmed in the user MAT. When the storage destination for the program data is in flash memory, an error occurs. The error occurrence is indicated by the WD bit in FPFR.
Bit Bit Name 31 MOD31 30 MOD30 29 MOD29 28 MOD28 27 MOD27 26 MOD26 25 MOD25 24 MOD24
Bit Bit Name
23 MOD23
22 MOD22
21 MOD21
20 MOD20
19 MOD19
18 MOD18
17 MOD17
16 MOD16
Bit Bit Name
15 MOD15
14 MOD14
13 MOD13
12 MOD12
11 MOD11
10 MOD10
9 MOD9
8 MOD8
Bit Bit Name
7 MOD7
6 MOD6
5 MOD5
4 MOD4
3 MOD3
2 MOD2
1 MOD1
0 MOD0
Bit 31 to 0
Initial Bit Name Value MOD31 to MOD0
R/W R/W
Description These bits store the start address of the area which stores the program data for the user MAT. Consecutive 128-byte data is programmed to the user MAT starting from the specified start address.
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Section 24 Flash Memory
(6)
Flash Erase Block Select Parameter (FEBS: General Register ER0 of CPU)
* H8SX/1653 FEBS specifies the erase block number. Settable values range from 0 to 13 (H'0000 to H'000D). A value of 0 corresponds to block EB0 and a value of 13 corresponds to block EB13. An error occurs when a value other than 0 to 13 is set. * H8SX/1654 FEBS specifies the erase block number. Settable values range from 0 to 15 (H'0000 to H'000F). A value of 0 corresponds to block EB0 and a value of 15 corresponds to block EB15. An error occurs when a value other than 0 to 15 is set. * H8SX/1658 FEBS specifies the erase block number. Settable values range from 0 to 23 (H'0000 to H'0017). A value of 0 corresponds to block EB0 and a value of 23 corresponds to block EB23. An error occurs when a value other than 0 to 23 is set.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 7 R/W 6 R/W 5 R/W 4 R/W 3 R/W 2 R/W 1 R/W 0 R/W 15 R/W 14 R/W 13 R/W 12 R/W 11 R/W 10 R/W 9 R/W 8 R/W 23 R/W 22 R/W 21 R/W 20 R/W 19 R/W 18 R/W 17 R/W 16 31 30 29 28 27 26 25 24
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Section 24 Flash Memory
24.7.3
RAM Emulation Register (RAMER)
RAMER specifies the user MAT area overlaid with part of the on-chip RAM (H'FFA000 to H'FFAFFF) when performing emulation of programming the user MAT. RAMER should be set in user mode or user programming mode. To ensure dependable emulation, the memory MAT to be emulated must not be accessed immediately after changing the RAMER contents. When accessed at such a timing, correct operation is not guaranteed.
Bit Bit Name Initial Value R/W 7 0 R 6 0 R 5 0 R 4 0 R 3 RAMS 0 R/W 2 RAM2 0 R/W 1 RAM1 0 R/W 0 RAM0 0 R/W
Bit 7 to 4 3
Initial Bit Name Value RAMS 0 0
R/W R R/W
Description Reserved These are read-only bits and cannot be modified. RAM Select Selects the function which emulates the flash memory using the on-chip RAM. 0: Disables RAM emulation function 1: Enables RAM emulation function (all blocks of the user MAT are protected against programming and erasing)
2 1 0
RAM2 RAM1 RAM0
0 0 0
R/W R/W R/W
Flash Memory Area Select These bits select the user MAT area overlaid with the on-chip RAM when RAMS = 1. The following areas correspond to the 4-Kbyte erase blocks. 000: H'000000 to H'000FFF (EB0) 001: H'001000 to H'001FFF (EB1) 010: H'002000 to H'002FFF (EB2) 011: H'003000 to H'003FFF (EB3) 100: H'004000 to H'004FFF (EB4) 101: H'005000 to H'005FFF (EB5) 110: H'006000 to H'006FFF (EB6) 111: H'007000 to H'007FFF (EB7)
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Section 24 Flash Memory
24.8
On-Board Programming Mode
When the mode pins (MD0, MD1, and MD2) are set to on-board programming mode and the reset start is executed, a transition is made to on-board programming mode in which the on-chip flash memory can be programmed/erased. On-board programming mode has four operating modes: user boot mode, SCI boot mode and USB boot mode, which are selected by PM2 setting, and user programming mode. Table 24.5 shows the pin setting for each operating mode. For details on the state transition of each operating mode for flash memory, see figure 24.2. Table 24.5 On-Board Programming Mode Setting
Mode Setting User boot mode SCI boot mode USB boot mode EMLE 0 0 0 MD2 0 0 0 1 1 MD1 0 1 1 1 1 MD0 1 0 0 0 1 PM2 0 1
User programming mode 0 0
24.8.1
SCI Boot Mode
SCI boot mode executes programming/erasing of the user MAT by means of the control command and program data transmitted from the externally connected host via the on-chip SCI_4. In SCI boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. The serial communication mode is set to asynchronous mode. The system configuration in SCI boot mode is shown in figure 24.6. Interrupts are ignored in SCI boot mode. Configure the user system so that interrupts do not occur.
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Section 24 Flash Memory
This LSI
PM2 MD2 to MD0
0 010
Host
Control command, program data
Software for analyzing control commands (on-chip)
Flash memory
Programming tool and program data
Response
RxD4 SCI_4 TxD4
On-chip RAM
Figure 24.6 System Configuration in SCI Boot Mode (1) Serial Interface Setting by Host
The SCI_4 is set to asynchronous mode, and the serial transmit/receive format is set to 8-bit data, one stop bit, and no parity. When a transition to SCI boot mode is made, the boot program embedded in this LSI is initiated. When the boot program is initiated, this LSI measures the low period of asynchronous serial communication data (H'00) transmitted consecutively by the host, calculates the bit rate, and adjusts the bit rate of the SCI_4 to match that of the host. When bit rate adjustment is completed, this LSI transmits 1 byte of H'00 to the host as the bit adjustment end sign. When the host receives this bit adjustment end sign normally, it transmits 1 byte of H'55 to this LSI. When reception is not executed normally, initiate boot mode again. The bit rate may not be adjusted within the allowable range depending on the combination of the bit rate of the host and the system clock frequency of this LSI. Therefore, the transfer bit rate of the host and the system clock frequency of this LSI must be as shown in table 24.6.
Start bit
D0
D1
D2
D3
D4
D5
D6
D7
Stop bit
Measure low period (9 bits) (data is H'00)
High period of at least 1 bit
Figure 24.7 Automatic-Bit-Rate Adjustment Operation
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Section 24 Flash Memory
Table 24.6 System Clock Frequency for Automatic-Bit-Rate Adjustment
Bit Rate of Host 9,600 bps 19,200 bps System Clock Frequency of This LSI 8 to 18 MHz 8 to 18 MHz
(2)
State Transition Diagram
The state transition after SCI boot mode is initiated is shown in figure 24.8.
(Bit rate adjustment) H'00, ..., H'00 reception H'00 transmission (adjustment completed) Bit rate adjustment
H'55 tion recep
Boot mode initiation (reset by boot mode)
1.
2.
Wait for inquiry setting command
Inquiry command reception
Inquiry command response
Processing of inquiry setting command
3.
All user MAT and user boot MAT erasure
4.
Wait for programming/erasing command
Read/check command reception Command response
Processing of read/check command
(Programming completion)
(Erasure completion) (Erasure selection command reception)
(Erasure selection command reception) (Erase-block specification)
Wait for erase-block data
(Program data transmission)
Wait for program data
Figure 24.8 SCI Boot Mode State Transition Diagram
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Section 24 Flash Memory
1. After SCI boot mode is initiated, the bit rate of the SCI_4 is adjusted with that of the host. 2. Inquiry information about the size, configuration, start address, and support status of the user MAT is transmitted to the host. 3. After inquiries have finished, all user MAT and user boot MAT are automatically erased. 4. When the program preparation notice is received, the state of waiting for program data is entered. The start address of the programming destination and program data must be transmitted after the programming command is transmitted. When programming is finished, the start address of the programming destination must be set to H'FFFFFFFF and transmitted. Then the state of waiting for program data is returned to the state of waiting for programming/erasing command. When the erasure preparation notice is received, the state of waiting for erase block data is entered. The erase block number must be transmitted after the erasing command is transmitted. When the erasure is finished, the erase block number must be set to H'FF and transmitted. Then the state of waiting for erase block data is returned to the state of waiting for programming/erasing command. Erasure must be executed when the specified block is programmed without a reset start after programming is executed in SCI boot mode. When programming can be executed by only one operation, all blocks are erased before entering the state of waiting for programming/erasing command or another command. Thus, in this case, the erasing operation is not required. The commands other than the programming/erasing command perform sum check, blank check (erasure check), and memory read of the user MAT/user boot MAT and acquisition of current status information. Memory read of the user MAT/user boot MAT can only read the data programmed after all user MAT/user boot MAT has automatically been erased. No other data can be read.
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Section 24 Flash Memory
24.8.2
USB Boot Mode
USB boot mode executes programming/erasing of the user MAT by means of the control command and program data transmitted from the externally connected host via the USB. In USB boot mode, the tool for transmitting the control command and program data, and the program data must be prepared in the host. The system configuration in USB boot mode is shown in figure 24.9. Interrupts are ignored in USB boot mode. Configure the user system so that interrupts do not occur.
Host or self-power HUB PM4
Software for analyzing control commands (on-chip)
This LSI PM2 MD3 to MD0 1 0010
Flash memory
1.5 k Rs Programming tool and program data Rs Data transmission/ reception VBUS PM3 USB+ USBUSB On-chip RAM
0: Self power setting 1: Bus power setting
Figure 24.9 System Configuration in USB Boot Mode
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Section 24 Flash Memory
(1)
Features
* Bus power mode and self power mode are selectable. * The PM4 pin supports the D+ pull-up control connection. * For enumeration information, refer to table 24.7. Table 24.7 Enumeration Information
USB standard Transfer mode Maximum power consumption Ver.2.0 (Full speed) Transfer mode Control (in, out), Bulk (in, out) For self power mode (PM3 = 0) For bus power mode (PM3 = 1) Endpoint configuration EP0 Control (in out) 8 bytes Configuration 1 InterfaceNumber0 AlternateSetting0 EP1 Bulk (out) 64 bytes EP2 Bulk (in) 64 bytes 100 mA 500 mA
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Section 24 Flash Memory
(2)
State Transition Diagram
The state transition after USB boot mode is initiated is shown in figure 24.10.
Boot mode initiation (reset by boot mode)
r H'55 ecep tion
Enumeration
1.
Inquiry command reception
2.
Wait for inquiry setting command
Processing of inquiry setting command Inquiry command response
3.
All user MAT erasure
4.
Wait for inquiry programming/erasing command
(Era
Read/check command reception
Processing of read/check command
Command response (Er com asure sur s ma e co nd electio mp rec letio ept n n) ion )
(Erase-block specification)
(Programming completion)
(Program selection command reception) (Program data transmission)
Wait for inquiry programming/erasing command
Wait for inquiry programming/erasing command
Figure 24.10 USB Boot Mode State Transition Diagram
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Section 24 Flash Memory
1. After a transition to the USB boot mode is made, the boot program embedded in this LSI is initialized. This LSI performs enumeration to the host after the USB boot program is initialized. 2. Inquiry information about the size, configuration, start address, and support status of the user MAT is transmitted to the host. 3. After inquiries have finished, all user MAT are automatically erased. 4. After all user MAT are automatically erased, the state of waiting for programming/erasing command is entered. When the programming command is received, the state shifts to the state of waiting for programming data. The same applies to erasing. In addition to the commands for programming/erasing, there are commands for performing sum check, blank check (erasure check), and memory read of the user MAT, and acquiring the current status information. (3) Notes on USB Boot Mode Execution
* The clock of 48 MHz needs to be supplied to the USB module. Set the external clock frequency and clock pulse generator so as to supply 48 MHz as the clock for the USB (cku). For details, refer to section 26, Clock Pulse Generator. * Use the PM4 pin for the D+ pull-up control connection. * For the stable supply of the power during the flash memory programming and erasing, the cable should not be connected via the bus powered HUB. * If the bus powered HUB is disconnected during the flash memory programming and erasing, permanent damage to the LSI may result. * If the USB bus in the bus power mode enters the suspend mode, this does not make the transition to the software standby mode in the power-down state.
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Section 24 Flash Memory
24.8.3
User Programming Mode
Programming/erasure of the user MAT is executed by downloading an on-chip program. The user boot MAT cannot be programmed/erased in user programming mode. The programming/erasing flow is shown in figure 24.11. Since high voltage is applied to the internal flash memory during programming/erasure, a transition to the reset state or hardware standby mode must not be made during programming/erasure. A transition to the reset state or hardware standby mode during programming/erasure may damage the flash memory. If a reset is input, the reset must be released after the reset input period (period of RES = 0) of at least 100 s.
Programming/erasing start 1. Exit RAM emulation mode beforehand. Download is not allowed in emulation mode. 2. When the program data is adjusted in emulation mode, select the download destination specified by FTDAR carefully. Make sure that the download area does not overlap the emulation area. 3. Programming/erasing is executed only in the on-chip RAM. 4. After programming/erasing is finished, protect the flash memory by the hardware protection.
When programming, program data is prepared
Programming/erasing procedure program is transferred to the on-chip RAM and executed
Programming/erasing end
Figure 24.11 Programming/Erasing Flow
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Section 24 Flash Memory
(1)
On-Chip RAM Address Map when Programming/Erasure is Executed
Parts of the procedure program that is made by the user, like download request, programming/erasure procedure, and decision of the result, must be executed in the on-chip RAM. Since the on-chip program to be downloaded is embedded in the on-chip RAM, make sure the onchip program and procedure program do not overlap. Figure 24.12 shows the area of the on-chip program to be downloaded.
DPFR (Return value: 1 byte) System use area (15 bytes)
Area to be downloaded (size: 4 kbytes) Unusable area during programming/erasing
FTDAR setting
Programming/erasing program entry
Initialization program entry
Initialization + programming program or Initialization + erasing program
RAM emulation area or area that can be used by user
Area that can be used by user
FTDAR setting + 16 bytes
FTDAR setting + 32 bytes
FTDAR setting + 4 kbytes
H'FFBFFF
Figure 24.12 RAM Map when Programming/Erasure is Executed
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Section 24 Flash Memory
(2)
Programming Procedure in User Programming Mode
The procedures for download of the on-chip program, initialization, and programming are shown in figure 24.13.
Start programming procedure program
1
Select on-chip program to be downloaded and specify download destination by FTDAR
Set FKEY to H'A5
1.
Disable interrupts and bus master operation other than CPU
Set FKEY to H'5A
9.
10.
2.
Set parameters to ER1 and ER0 (FMPAR and FMPDR)
Set SCO to 1 after initializing VBR and execute download
Download
3.
11.
Clear FKEY to 0
4.
Programming
Programming JSR FTDAR setting + 16
FPFR = 0?
12. 13.
DPFR = 0? Yes
Set the FPEFEQ parameter
Initialization
5.
No
Download error processing
No
Clear FKEY and programming error processing
14.
Yes
6. 7.
No
Initialization JSR FTDAR setting + 32
Required data programming is completed?
Yes
8.
FPFR = 0?
No
Initialization error processing
Clear FKEY to 0
15.
Yes
1
End programming procedure program
Figure 24.13 Programming Procedure in User Programming Mode
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Section 24 Flash Memory
The procedure program must be executed in an area other than the flash memory to be programmed. Setting the SCO bit in FCCS to 1 to request download must be executed in the onchip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 24.8.5, On-Chip Program and Storable Area for Program Data. The following description assumes that the area to be programmed on the user MAT is erased and that program data is prepared in the consecutive area. The program data for one programming operation is always 128 bytes. When the program data exceeds 128 bytes, the start address of the programming destination and program data parameters are updated in 128-byte units and programming is repeated. When the program data is less than 128 bytes, invalid data is filled to prepare 128-byte program data. If the invalid data to be added is H'FF, the program processing time can be shortened. 1. Select the on-chip program to be downloaded and the download destination. When the PPVS bit in FPCS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are selected, a download error is returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download destination is specified by FTDAR. 2. Write H'A5 in FKEY. If H'A5 is not written to FKEY, the SCO bit in FCCS cannot be set to 1 to request download of the on-chip program. 3. After initializing VBR to H'00000000, set the SCO bit to 1 to execute download. To set the SCO bit to 1, all of the following conditions must be satisfied. RAM emulation mode has been canceled. H'A5 is written to FKEY. Setting the SCO bit is executed in the on-chip RAM. When the SCO bit is set to 1, download is started automatically. Since the SCO bit is cleared to 0 when the procedure program is resumed, the SCO bit cannot be confirmed to be 1 in the procedure program. The download result can be confirmed by the return value of the DPFR parameter. To prevent incorrect decision, before setting the SCO bit to 1, set one byte of the on-chip RAM start address specified by FTDAR, which becomes the DPFR parameter, to a value other than the return value (e.g. H'FF). Since particular processing that is accompanied by bank switching as described below is performed when download is executed, initialize the VBR contents to H'00000000. Dummy read of FCCS must be performed twice immediately after the SCO bit is set to 1. The user-MAT space is switched to the on-chip program storage area. After the program to be downloaded and the on-chip RAM start address specified by FTDAR are checked, they are transferred to the on-chip RAM. FPCS, FECS, and the SCO bit in FCCS are cleared to 0.
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Section 24 Flash Memory
The return value is set in the DPFR parameter. After the on-chip program storage area is returned to the user-MAT space, the procedure program is resumed. After that, VBR can be set again. The values of general registers of the CPU are held. During download, no interrupts can be accepted. However, since the interrupt requests are held, when the procedure program is resumed, the interrupts are requested. To hold a level-detection interrupt request, the interrupt must continue to be input until the download is completed. Allocate a stack area of 128 bytes at the maximum in the on-chip RAM before setting the SCO bit to 1. If access to the flash memory is requested by the DMAC or DTC during download, the operation cannot be guaranteed. Make sure that an access request by the DMAC or DTC is not generated. 4. FKEY is cleared to H'00 for protection. 5. The download result must be confirmed by the value of the DPFR parameter. Check the value of the DPFR parameter (one byte of start address of the download destination specified by FTDAR). If the value of the DPFR parameter is H'00, download has been performed normally. If the value is not H'00, the source that caused download to fail can be investigated by the description below. If the value of the DPFR parameter is the same as that before downloading, the setting of the start address of the download destination in FTDAR may be abnormal. In this case, confirm the setting of the TDER bit in FTDAR. If the value of the DPFR parameter is different from that before downloading, check the SS bit or FK bit in the DPFR parameter to confirm the download program selection and FKEY setting, respectively. 6. The operating frequency of the CPU is set in the FPEFEQ parameter for initialization. The settable operating frequency of the FPEFEQ parameter ranges from 8 to 50 MHz. When the frequency is set otherwise, an error is returned to the FPFR parameter of the initialization program and initialization is not performed. For details on setting the frequency, see section 24.7.2 (3), Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU).
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Section 24 Flash Memory
7. Initialization is executed. The initialization program is downloaded together with the programming program to the on-chip RAM. The entry point of the initialization program is at the address which is 32 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute initialization by using the following steps.
MOV.L #DLTOP+32,ER2 JSR NOP @ER2 ; Set entry address to ER2 ; Call initialization routine
The general registers other than ER0 and ER1 are held in the initialization program. R0L is a return value of the FPFR parameter. Since the stack area is used in the initialization program, a stack area of 128 bytes at the maximum must be allocated in RAM. Interrupts can be accepted during execution of the initialization program. Make sure the program storage area and stack area in the on-chip RAM and register values are not overwritten. 8. The return value in the initialization program, the FPFR parameter is determined. 9. All interrupts and the use of a bus master other than the CPU are disabled during programming/erasure. The specified voltage is applied for the specified time when programming or erasing. If interrupts occur or the bus mastership is moved to other than the CPU during programming/erasure, causing a voltage exceeding the specifications to be applied, the flash memory may be damaged. Therefore, interrupts are disabled by setting bit 7 (I bit) in the condition code register (CCR) to B'1 in interrupt control mode 0 and by setting bits 2 to 0 (I2 to I0 bits) in the extend register (EXR) to B'111 in interrupt control mode 2. Accordingly, interrupts other than NMI are held and not executed. Configure the user system so that NMI interrupts do not occur. The interrupts that are held must be executed after all programming completes. When the bus mastership is moved to other than the CPU, such as to the DMAC or DTC, the error protection state is entered. Therefore, make sure the DMAC does not acquire the bus. 10. FKEY must be set to H'5A and the user MAT must be prepared for programming. 11. The parameters required for programming are set. The start address of the programming destination on the user MAT (FMPAR parameter) is set in general register ER1. The start address of the program data storage area (FMPDR parameter) is set in general register ER0. Example of FMPAR parameter setting: When an address other than one in the user MAT area is specified for the start address of the programming destination, even if the programming program is executed, programming is not executed and an error is returned to the FPFR parameter. Since the program data for one programming operation is 128 bytes, the lower eight bits of the address must be H'00 or H'80 to be aligned with the 128-byte boundary.
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Section 24 Flash Memory
Example of FMPDR parameter setting: When the storage destination for the program data is flash memory, even if the programming routine is executed, programming is not executed and an error is returned to the FPFR parameter. In this case, the program data must be transferred to the on-chip RAM and then programming must be executed. 12. Programming is executed. The entry point of the programming program is at the address which is 16 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute programming by using the following steps.
MOV.L JSR NOP #DLTOP+16,ER2 @ER2 ; Set entry address to ER2 ; Call programming routine
The general registers other than ER0 and ER1 are held in the programming program. R0L is a return value of the FPFR parameter. Since the stack area is used in the programming program, a stack area of 128 bytes at the maximum must be allocated in RAM. 13. The return value in the programming program, the FPFR parameter is determined. 14. Determine whether programming of the necessary data has finished. If more than 128 bytes of data are to be programmed, update the FMPAR and FMPDR parameters in 128-byte units, and repeat steps 11 to 14. Increment the programming destination address by 128 bytes and update the programming data pointer correctly. If an address which has already been programmed is written to again, not only will a programming error occur, but also flash memory will be damaged. 15. After programming finishes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after programming has finished, secure the reset input period (period of RES = 0) of at least 100 s.
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Section 24 Flash Memory
(3)
Erasing Procedure in User Programming Mode
The procedures for download of the on-chip program, initialization, and erasing are shown in figure 24.14.
Start erasing procedure program Select on-chip program to be downloaded and specify download destination by FTDAR
1
1.
Disable interrupts and bus master operation other than CPU Set FKEY to H'5A
Set FKEY to H'A5
Download
Set SCO to 1 after initializing VBR and execute download
Set FEBS parameter Erasing JSR FTDAR setting + 16 FPFR = 0? Yes
2.
Clear FKEY to 0
3. 4. No
DPFR = 0? Yes Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 FPFR = 0 ? Yes 1
No Download error processing No
Erasing
Clear FKEY and erasing error processing
Required block erasing is completed? Yes Clear FKEY to 0
5.
Initialization
6.
No Initialization error processing
End erasing procedure program
Figure 24.14 Erasing Procedure in User Programming Mode
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Section 24 Flash Memory
The procedure program must be executed in an area other than the user MAT to be erased. Setting the SCO bit in FCCS to 1 to request download must be executed in the on-chip RAM. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 24.8.5, On-Chip Program and Storable Area for Program Data. For the downloaded on-chip program area, see figure 24.12. One erasure processing erases one block. For details on block divisions, refer to figure 24.4. To erase two or more blocks, update the erase block number and repeat the erasing processing for each block. 1. Select the on-chip program to be downloaded and the download destination. When the EPVB bit in FECS is set to 1, the programming program is selected. Several programming/erasing programs cannot be selected at one time. If several programs are selected, a download error is returned to the SS bit in the DPFR parameter. The on-chip RAM start address of the download destination is specified by FTDAR. For the procedures to be carried out after setting FKEY, see section 24.8.3 (2), Programming Procedure in User Programming Mode. 2. Set the FEBS parameter necessary for erasure. Set the erase block number (FEBS parameter) of the user MAT in general register ER0. If a value other than an erase block number of the user MAT is set, no block is erased even though the erasing program is executed, and an error is returned to the FPFR parameter. 3. Erasure is executed. Similar to as in programming, the entry point of the erasing program is at the address which is 16 bytes after #DLTOP (start address of the download destination specified by FTDAR). Call the subroutine to execute erasure by using the following steps.
MOV.L #DLTOP+16, ER2 JSR NOP @ER2 ; Set entry address to ER2 ; Call erasing routine
The general registers other than ER0 and ER1 are held in the erasing program. R0L is a return value of the FPFR parameter. Since the stack area is used in the erasing program, a stack area of 128 bytes at the maximum must be allocated in RAM. 4. The return value in the erasing program, the FPFR parameter is determined. 5. Determine whether erasure of the necessary blocks has finished. If more than one block is to be erased, update the FEBS parameter and repeat steps 2 to 5. 6. After erasure completes, clear FKEY and specify software protection. If this LSI is restarted by a reset immediately after erasure has finished, secure the reset input period (period of RES = 0) of at least 100 s.
* * *
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Section 24 Flash Memory
(4) Procedure of Erasing, Programming, and RAM Emulation in User Programming Mode By changing the on-chip RAM start address of the download destination in FTDAR, the erasing program and programming program can be downloaded to separate on-chip RAM areas. Figure 24.15 shows a repeating procedure of erasing, programming, and RAM emulation.
1 Start procedure program Make a transition to RAM emulation mode and tuning parameters in on-chip RAM
Emulation/Erasing/Programming
Erasing program
download
Set FTDAR to H'00 (specify download destination to H'FF9000)
Exit emulation mode
Download erasing program
Initialize erasing program
Erase relevant block (execute erasing program)
Programming program
download
Set FTDAR to H'02 (specify download destination H'FFB000)
Set FMPDR to H'FFA000 and program relevant block (execute programming program)
Download programming program
Confirm operation
Initialize programming program
End ? Yes
No
1
End procedure program
Figure 24.15 Repeating Procedure of Erasing, Programming, and RAM Emulation in User Programming Mode
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Section 24 Flash Memory
In figure 24.15, since RAM emulation is performed, the erasing/programming program is downloaded to avoid the 4-Kbyte on-chip RAM area (H'FFA000 to H'FFAFFF). Download and initialization are performed only once at the beginning. Note the following when executing the procedure program. * Be careful not to overwrite data in the on-chip RAM with overlay settings. In addition to the programming program area, erasing program area, and RAM emulation area, areas for the procedure programs, work area, and stack area are reserved in the on-chip RAM. Do not make settings that will overwrite data in these areas. * Be sure to initialize both the programming program and erasing program. When the FPEFEQ parameter is initialized, also initialize both the erasing program and programming program. Initialization must be executed for both entry addresses: #DLTOP (start address of download destination for erasing program) + 32 bytes, and #DLTOP (start address of download destination for programming program) + 32 bytes. 24.8.4 User Boot Mode
Branching to a programming/erasing program prepared by the user enables user boot mode which is a user-defined boot mode to be used. Only the user MAT can be programmed/erased in user boot mode. Programming/erasure of the user boot MAT is only enabled in boot mode or programmer mode. (1) Initiation in User Boot Mode
When the reset start is executed with the mode pins set to user boot mode, the built-in check routine runs and checks the user MAT and user boot MAT states. While the check routine is running, NMI and all other interrupts cannot be accepted. Next, processing starts from the execution start address of the reset vector in the user boot MAT. At this point, the user boot MAT is selected (FMATS = H'AA) as the execution memory MAT. (2) User MAT Programming in User Boot Mode
Figure 24.16 shows the procedure for programming the user MAT in user boot mode. The difference between the programming procedures in user programming mode and user boot mode is the memory MAT switching as shown in figure 24.16. For programming the user MAT in user boot mode, additional processing made by setting FMATS is required: switching from the user boot MAT to the user MAT, and switching back to the user boot MAT after programming completes.
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Section 24 Flash Memory
Start programming procedure program
1
Select on-chip program to be downloaded and specify download destination by FTDAR
Set FMATS to value other than H'AA to select user MAT
MAT switchover
Set FKEY to H'A5
Set FKEY to H'A5
Set parameter to ER0 and ER1 (FMPAR and FMPDR)
Set SCO to 1 after initializing VBR and execute download
Download
User-MAT selection state
Clear FKEY to 0
Programming
Programming JSR FTDAR setting + 16
FPFR = 0 ?
User-boot-MAT selection state
DPFR = 0 ? Yes
Yes
No Required data programming is completed?
No
Download error processing
No Clear FKEY and programming error processing
Set the FPEFEQ parameter
Yes
Initialization
Initialization JSR FTDAR setting + 32
Clear FKEY to 0
FPFR = 0 ?
No
Initialization error processing
Set FMATS to H'AA to select user boot MAT
Yes
Disable interrupts and bus master operation other than CPU
User-boot-MAT selection state
1
MAT switchover
End programming procedure program
Note: The MAT must be switched by FMATS to perform the programming error processing in the user boot MAT.
Figure 24.16 Procedure for Programming User MAT in User Boot Mode
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Section 24 Flash Memory
In user boot mode, though the user boot MAT can be seen in the flash memory space, the user MAT is hidden in the background. Therefore, the user MAT and user boot MAT are switched while the user MAT is being programmed. Because the user boot MAT is hidden while the user MAT is being programmed, the procedure program must be executed in an area other than flash memory. After programming completes, switch the memory MATs again to return to the first state. Memory MAT switching is enabled by setting FMATS. However note that access to a memory MAT is not allowed until memory MAT switching is completed. During memory MAT switching, the LSI is in an unstable state, e.g. if an interrupt occurs, from which memory MAT the interrupt vector is read is undetermined. Perform memory MAT switching in accordance with the description in section 24.11, Switching between User MAT and User Boot MAT. Except for memory MAT switching, the programming procedure is the same as that in user programming mode. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 24.8.5, On-Chip Program and Storable Area for Program Data. (3) User MAT Erasing in User Boot Mode
Figure 24.17 shows the procedure for erasing the user MAT in user boot mode. The difference between the erasing procedures in user programming mode and user boot mode is the memory MAT switching as shown in figure 24.17. For erasing the user MAT in user boot mode, additional processing made by setting FMATS is required: switching from the user boot MAT to the user MAT, and switching back to the user boot MAT after erasing completes.
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Section 24 Flash Memory
Start erasing procedure program Select on-chip program to be downloaded and specify download destination by FTDAR
1
Set FMATS to value other than H'AA to select user MAT
MAT switchover
Set FKEY to H'A5 Set SCO to 1 after initializing VBR and execute download Set FKEY to H'A5
Download
Clear FKEY to 0
Set FEBS parameter Erasing JSR FTDAR setting + 16
User-boot-MAT selection state
Yes
Erasing
No Download error processing
User-MAT selection state
DPFR = 0 ?
FPFR = 0 ? Yes No Required block erasing is completed? Yes
Set the FPEFEQ parameter Initialization JSR FTDAR setting + 32 FPFR = 0 ?
No Clear FKEY and erasing error processing
Initialization
No
Clear FKEY to 0
Yes
Initialization error processing Set FMATS to H'AA to select user boot MAT MAT switchover
Disable interrupts and bus master operation other than CPU User-boot-MAT selection state
1
End erasing procedure program
Note:
The MAT must be switched by FMATS to perform the erasing error processing in the user boot MAT.
Figure 24.17 Procedure for Erasing User MAT in User Boot Mode
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Section 24 Flash Memory
Memory MAT switching is enabled by setting FMATS. However note that access to a memory MAT is not allowed until memory MAT switching is completed. During memory MAT switching, the LSI is in an unstable state, e.g. if an interrupt occurs, from which memory MAT the interrupt vector is read is undetermined. Perform memory MAT switching in accordance with the description in section 24.11, Switching between User MAT and User Boot MAT. Except for memory MAT switching, the erasing procedure is the same as that in user programming mode. The area that can be executed in the steps of the procedure program (on-chip RAM, user MAT, and external space) is shown in section 24.8.5, On-Chip Program and Storable Area for Program Data. 24.8.5 On-Chip Program and Storable Area for Program Data
In the descriptions in this manual, the on-chip programs and program data storage areas are assumed to be in the on-chip RAM. However, they can be executed from part of the flash memory which is not to be programmed or erased as long as the following conditions are satisfied. * The on-chip program is downloaded to and executed in the on-chip RAM specified by FTDAR. Therefore, this on-chip RAM area is not available for use. * Since the on-chip program uses a stack area, allocate 128 bytes at the maximum as a stack area. * Download requested by setting the SCO bit in FCCS to 1 should be executed from the on-chip RAM because it will require switching of the memory MATs. * In an operating mode in which the external address space is not accessible, such as single-chip mode, the required procedure programs, NMI handling vector table, and NMI handling routine should be transferred to the on-chip RAM before programming/erasure starts (download result is determined). * The flash memory is not accessible during programming/erasure. Programming/erasure is executed by the program downloaded to the on-chip RAM. Therefore, the procedure program that initiates operation, the NMI handling vector table, and the NMI handling routine should be stored in the on-chip RAM other than the flash memory. * After programming/erasure starts, access to the flash memory should be inhibited until FKEY is cleared. The reset input state (period of RES = 0) must be set to at least 100 s when the operating mode is changed and the reset start executed on completion of programming/erasure. Transitions to the reset state are inhibited during programming/erasure. When the reset signal is input, a reset input state (period of RES = 0) of at least 100 s is needed before the reset signal is released.
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Section 24 Flash Memory
* Switching of the memory MATs by FMATS should be needed when programming/erasure of the user MAT is operated in user boot mode. The program which switches the memory MATs should be executed from the on-chip RAM. For details, see section 24.11, Switching between User MAT and User Boot MAT. Make sure you know which memory MAT is currently selected when switching them. * When the program data storage area is within the flash memory area, an error will occur even when the data stored is normal program data. Therefore, the data should be transferred to the on-chip RAM to place the address that the FMPDR parameter indicates in an area other than the flash memory. In consideration of these conditions, the areas in which the program data can be stored and executed are determined by the combination of the processing contents, operating mode, and bank structure of the memory MATs, as shown in tables 24.8 to 24.12. Table 24.8 Executable Memory MAT
Operating Mode Processing Contents Programming Erasing Note: * User Programming Mode See table 24.9 See table 24.10 Programming/Erasure is possible to the user MAT. User Boot Mode* See table 24.11 See table 24.12
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Section 24 Flash Memory
Table 24.9 Usable Area for Programming in User Programming Mode
Storable/Executable Area Selected MAT Embedded Program User MAT Storage MAT O O O O O O O O O O O O O O O O O O
Item Storage area for program data Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY Execution of writing 1 to SCO bit in FCCS (download) Operation for clearing FKEY Decision of download result Operation for download error Operation for setting initialization parameter Execution of initialization Decision of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupts Operation for writing H'5A to FKEY Operation for setting programming parameter Execution of programming Decision of programming result Operation for programming error Operation for clearing FKEY Note: *
On-Chip RAM O O O O O O O O O O O O O O O O O O O
User MAT x* O O x O O O O x O O x O O x x x x x
Transferring the program data to the on-chip RAM beforehand enables this area to be used.
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Section 24 Flash Memory
Table 24.10 Usable Area for Erasure in User Programming Mode
Storable/Executable Area Selected MAT Embedded Program User MAT Storage MAT O O O O O O O O O O O O O O O O O O
Item Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY Execution of writing 1 to SCO bit in FCCS (download) Operation for clearing FKEY Decision of download result Operation for download error Operation for setting initialization parameter Execution of initialization Decision of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupts Operation for writing H'5A to FKEY Operation for setting erasure parameter Execution of erasure Decision of erasure result Operation for erasure error Operation for clearing FKEY
On-Chip RAM O O O O O O O O O O O O O O O O O O
User MAT O O x O O O O x O O x O O x x x x x
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Section 24 Flash Memory
Table 24.11 Usable Area for Programming in User Boot Mode
Storable/Executable Area On-Chip RAM O O O O O O O O O O O O O User Boot MAT x*1 O O x O O O O x O O x O x x x x x x* x x
2
Selected MAT User MAT User Boot MAT O O O O O O O O O O O O O O O O O O O O Embedded Program Storage MAT
Item Storage area for program data Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY Execution of writing 1 to SCO bit in FCCS (download) Operation for clearing FKEY Decision of download result Operation for download error Operation for setting initialization parameter Execution of initialization Decision of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupts
Switching memory MATs by FMATS O Operation for writing H'5A to FKEY Operation for setting programming parameter Execution of programming Decision of programming result Operation for programming error Operation for clearing FKEY O O O O O O
Switching memory MATs by FMATS O
Notes: 1. Transferring the program data to the on-chip RAM beforehand enables this area to be used. 2. Switching memory MATs by FMATS by a program in the on-chip RAM enables this area to be used.
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Section 24 Flash Memory
Table 24.12 Usable Area for Erasure in User Boot Mode
Storable/Executable Area On-Chip RAM O O O O O O O O O O O O User Boot MAT O O x O O O O x O O x O x x x x x x* x x O O O O O O O O O O O O O O O O O User MAT Selected MAT User Boot MAT O O O Embedded Program Storage MAT
Item Operation for selecting on-chip program to be downloaded Operation for writing H'A5 to FKEY Execution of writing 1 to SCO bit in FCCS (download) Operation for clearing FKEY Decision of download result Operation for download error Operation for setting initialization parameter Execution of initialization Decision of initialization result Operation for initialization error NMI handling routine Operation for disabling interrupts
Switching memory MATs by FMATS O Operation for writing H'5A to FKEY Operation for setting erasure parameter Execution of erasure Decision of erasure result Operation for erasure error Operation for clearing FKEY Note: * O O O O O O
Switching memory MATs by FMATS O
Switching memory MATs by FMATS by a program in the on-chip RAM enables this area to be used.
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Section 24 Flash Memory
24.9
Protection
There are three types of protection against the flash memory programming/erasure: hardware protection, software protection, and error protection. 24.9.1 Hardware Protection
Programming and erasure of the flash memory is forcibly disabled or suspended by hardware protection. In this state, download of an on-chip program and initialization are possible. However, programming or erasure of the user MAT cannot be performed even if the programming/erasing program is initiated, and the error in programming/erasure is indicated by the FPFR parameter. Table 24.13 Hardware Protection
Function to be Protected Item Reset protection Description * The programming/erasing interface registers are initialized in the reset state (including a reset by the WDT) and the programming/erasing protection state is entered. The reset state will not be entered by a reset using the RES pin unless the RES pin is held low until oscillation has settled after a power is initially supplied. In the case of a reset during operation, hold the RES pin low for the RES pulse width given in the AC characteristics. If a reset is input during programming or erasure, data in the flash memory is not guaranteed. In this case, execute erasure and then execute programming again. Download O Programming/ Erasing O
*
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Section 24 Flash Memory
24.9.2
Software Protection
The software protection protects the flash memory against programming/erasure by disabling download of the programming/erasing program, using the key code, and by the RAMER setting. Table 24.14 Software Protection
Function to be Protected Item Description Download Programming/ Erasing O
Protection The programming/erasing protection state is O by SCO bit entered when the SCO bit in FCCS is cleared to 0 to disable download of the programming/erasing programs. Protection by FKEY The programming/erasing protection state is entered because download and programming/erasure are disabled unless the required key code is written in FKEY. O
O
Emulation protection
The programming/erasing protection state is O entered when the RAMS bit in the RAM emulation register (RAMER) is set to 1.
O
24.9.3
Error Protection
Error protection is a mechanism for aborting programming or erasure when a CPU runaway occurs or operations not according to the programming/erasing procedures are detected during programming/erasure of the flash memory. Aborting programming or erasure in such cases prevents damage to the flash memory due to excessive programming or erasing. If an error occurs during programming/erasure of the flash memory, the FLER bit in FCCS is set to 1 and the error protection state is entered. * When an interrupt request, such as NMI, occurs during programming/erasure. * When the flash memory is read from during programming/erasure (including a vector read or an instruction fetch). * When a SLEEP instruction is executed (including software-standby mode) during programming/erasure. * When a bus master other than the CPU, such as the DMAC and DTC, obtains bus mastership during programming/erasure.
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Section 24 Flash Memory
Error protection is canceled by a reset. Note that the reset should be released after the reset input period of at least 100s has passed. Since high voltages are applied during programming/erasure of the flash memory, some voltage may remain after the error protection state has been entered. For this reason, it is necessary to reduce the risk of damaging the flash memory by extending the reset input period so that the charge is released. The state-transition diagram in figure 24.18 shows transitions to and from the error protection state.
Programming/erasing mode Read disabled Programming/erasing enabled FLER = 0
RES = 0
Reset (hardware protection) Read disabled Programming/erasing disabled FLER = 0 Programming/erasing interface register is in its initial state.
Er (S
ror
oc
cu
oft w
rre
d
S= RE
0
are
Error occurrence
sta nd by
RES = 0
)
Error-protection mode Read enabled Programming/erasing disabled FLER = 1
Software standby mode
Error-protection mode (software standby) Read disabled Programming/erasing disabled FLER = 1 Programming/erasing interface register is in its initial state.
Cancel software standby mode
Figure 24.18 Transitions to Error Protection State
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Section 24 Flash Memory
24.10
Flash Memory Emulation Using RAM
For realtime emulation of the data written to the flash memory using the on-chip RAM, the onchip RAM area can be overlaid with several flash memory blocks (user MAT) using the RAM emulation register (RAMER). The overlaid area can be accessed from both the user MAT area specified by RAMER and the overlaid RAM area. The emulation can be performed in user mode and user programming mode. Figure 24.19 shows an example of emulating realtime programming of the user MAT.
Emulation program start
Set RAMER
Write tuning data to overlaid RAM area
Execute application program
No
Tuning OK? Yes Cancel setting in RAMER
Program emulation block in user MAT
Emulation program end
Figure 24.19 RAM Emulation Flow
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Section 24 Flash Memory
Figure 24.20 shows an example of overlaying flash memory block area EB0.
This area can be accessed via both the on-chip RAM and flash memory area. H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 Flash memory user MAT EB8 to EB15*1 H'7FFFF*2 Notes: 1. 2. EB8 to EB13 in the H8SX/1653. EB8 to EB23 in the H8SX/1658. H'05FFFF in the H8SX/1653. H'0FFFFF in the H8SX/1658. On-chip RAM H'FFBFFF EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7 H'FF6000 H'FFA000 H'FFAFFF
Figure 24.20 Address Map of Overlaid RAM Area (H8SX/1654) The flash memory area that can be emulated is the one area selected by bits RAM2 to RAM0 in RAMER from among the eight blocks, EB0 to EB7, of the user MAT. To overlay a part of the on-chip RAM with block EB0 for realtime emulation, set the RAMS bit in RAMER to 1 and bits RAM2 to RAM0 to B'000. For programming/erasing the user MAT, the procedure programs including a download program of the on-chip program must be executed. At this time, the download area should be specified so that the overlaid RAM area is not overwritten by downloading the on-chip program. Since the area in which the tuned data is stored is overlaid with the download area when FTDAR = H'01, the tuned data must be saved in an unused area beforehand.
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Section 24 Flash Memory
Figure 24.21 shows an example of the procedure to program the tuned data in block EB0 of the user MAT.
H'00000 H'01000 H'02000 H'03000 H'04000 H'05000 H'06000 H'07000 H'08000 Flash memory user MAT EB8 to EB15*1 H'7FFFF*2 Notes: 1. 2. Download area Tuned data area
Area for programming/ erasing program etc.
EB0 EB1 EB2 EB3 EB4 EB5 EB6 EB7
(1) Exit RAM emulation mode. (2) Transfer user-created programming/erasing procedure program. (3) Download the on-chip programming/erasing program to the area specified by FTDAR. FTDAR setting should avoid the tuned data area. (4) Program after erasing, if necessary.
Specified by FTDAR H'FFA000 H'FFAFFF H'FFB000 H'FFBFFF
EB8 to EB13 in the H8SX/1653. EB8 to EB23 in the H8SX/1658. H'05FFFF in the H8SX/1653. H'0FFFFF in the H8SX/1658.
Figure 24.21 Programming Tuned Data (H8SX/1654) 1. After tuning program data is completed, clear the RAMS bit in RAMER to 0 to cancel the overlaid RAM. 2. Transfer the user-created procedure program to the on-chip RAM. 3. Start the procedure program and download the on-chip program to the on-chip RAM. The start address of the download destination should be specified by FTDAR so that the tuned data area does not overlay the download area. 4. When block EB0 of the user MAT has not been erased, the programming program must be downloaded after block EB0 is erased. Specify the tuned data saved in the FMPAR and FMPDR parameters and then execute programming. Note: Setting the RAMS bit to 1 makes all the blocks of the user MAT enter the programming/erasing protection state (emulation protection state) regardless of the setting of the RAM2 to RAM0 bits. Under this condition, the on-chip program cannot be downloaded. When data is to be actually programmed and erased, clear the RAMS bit to 0.
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Section 24 Flash Memory
24.11
Switching between User MAT and User Boot MAT
It is possible to switch between the user MAT and user boot MAT. However, the following procedure is required because the start addresses of these MATs are allocated to the same address. Switching to the user boot MAT disables programming and erasing. Programming of the user boot MAT should take place in boot mode or programmer mode. 1. Memory MAT switching by FMATS should always be executed from the on-chip RAM. 2. When accessing the memory MAT immediately after switching the memory MATs by FMATS from the on-chip RAM, similarly execute the NOP instruction in the on-chip RAM for eight times (this prevents access to the flash memory during memory MAT switching). 3. If an interrupt request has occurred during memory MAT switching, there is no guarantee of which memory MAT is accessed. Always mask the maskable interrupts before switching memory MATs. In addition, configure the system so that NMI interrupts do not occur during memory MAT switching. 4. After the memory MATs have been switched, take care because the interrupt vector table will also have been switched. If interrupt processing is to be the same before and after memory MAT switching, transfer the interrupt processing routines to the on-chip RAM and specify VBR to place the interrupt vector table in the on-chip RAM. 5. The size of the user MAT is different from that of the user boot MAT. Addresses which exceed the size of the 16-Kbyte user boot MAT should not be accessed. If an attempt is made, data is read as an undefined value.

Procedure for switching to user boot MAT Procedure for switching to user MAT Procedure for switching to the user boot MAT 1. Inhibit interrupts (mask). 2. Write H'AA to FMATS. 3. Before access to the user boot MAT, execute the NOP instruction for eight times. Procedure for switching to the user MAT 1. Inhibit interrupts (mask). 2. Write other than H'AA to FMATS. 3. Before access to the user MAT, execute the NOP instruction for eight times.
Figure 24.22 Switching between User MAT and User Boot MAT
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Section 24 Flash Memory
24.12
Programmer Mode
Along with its on-board programming mode, this LSI also has a programmer mode as a further mode for the writing and erasing of programs and data. In programmer mode, a general-purpose PROM programmer that supports the device types shown in table 24.15 can be used to write programs to the on-chip ROM without any limitation. Table 24.15 Device Types Supported in Programmer Mode
Target Memory MAT User MAT Product Classification ROM Size H8SX/1653 H8SX/1654 H8SX/1658 User boot MAT H8SX/1653 H8SX/1654 H8SX/1658 384 Kbytes 512 Kbytes 1 Mbyte 16 Kbytes FZTAT1024V3A FZTATUSBT16V3A Device Type FZTAT512V3A
24.13
Standard Serial Communications Interface Specifications for Boot Mode
The boot program initiated in boot mode performs serial communications using the host and onchip SCI_4. The serial communications interface specifications are shown below. The boot program has three states. 1. Bit-rate-adjustment state In this state, the boot program adjusts the bit rate to achieve serial communications with the host. Initiating boot mode enables starting of the boot program and entry to the bit-rateadjustment state. The program receives the command from the host to adjust the bit rate. After adjusting the bit rate, the program enters the inquiry/selection state. 2. Inquiry/selection state In this state, the boot program responds to inquiry commands from the host. The device name, clock mode, and bit rate are selected. After selection of these settings, the program is made to enter the programming/erasing state by the command for a transition to the programming/erasing state. The program transfers the libraries required for erasure to the onchip RAM and erases the user MATs and user boot MATs before the transition.
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Section 24 Flash Memory
3. Programming/erasing state Programming and erasure by the boot program take place in this state. The boot program is made to transfer the programming/erasing programs to the on-chip RAM by commands from the host. Sum checks and blank checks are executed by sending these commands from the host. These boot program states are shown in figure 24.23.
Reset
Bit-rate-adjustment state
Inquiry/response wait
Response Inquiry
Operations for inquiry and selection
Operations for response
Transition to programming/erasing
Operations for erasing user MATs and user boot MATs
Programming/erasing wait
Programming
Operations for programming
Erasing
Operations for erasing
Checking
Operations for checking
Figure 24.23 Boot Program States
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Section 24 Flash Memory
(1)
Bit-Rate-Adjustment State
The bit rate is calculated by measuring the period of transfer of a low-level byte (H'00) from the host. The bit rate can be changed by the command for a new bit rate selection. After the bit rate has been adjusted, the boot program enters the inquiry and selection state. The bit-rate-adjustment sequence is shown in figure 24.24.
Host
Boot program
H'00 (30 times maximum)
Measuring the 1-bit length
H'00 (completion of adjustment)
H'55
H'E6 (boot response)
(H'FF (error))
Figure 24.24 Bit-Rate-Adjustment Sequence (2) Communications Protocol
After adjustment of the bit rate, the protocol for serial communications between the host and the boot program is as shown below. 1. One-byte commands and one-byte responses These one-byte commands and one-byte responses consist of the inquiries and the ACK for successful completion. 2. n-byte commands or n-byte responses These commands and responses are comprised of n bytes of data. These are selections and responses to inquiries. The program data size is not included under this heading because it is determined in another command. 3. Error response The error response is a response to inquiries. It consists of an error response and an error code and comes two bytes. 4. Programming of 128 bytes The size is not specified in commands. The size of n is indicated in response to the programming unit inquiry.
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Section 24 Flash Memory
5. Memory read response This response consists of four bytes of data.
One-byte command or one-byte response n-byte Command or n-byte response Command or response
Data Size Command or response Checksum
Error response Error code Error response
128-byte programming
Address Command
Data (n bytes) Checksum
Memory read response
Size
Response
Data Checksum
Figure 24.25 Communication Protocol Format * Command (one byte): Commands including inquiries, selection, programming, erasing, and checking * Response (one byte): Response to an inquiry * Size (one byte): The amount of data for transmission excluding the command, amount of data, and checksum * Checksum (one byte): The checksum is calculated so that the total of all values from the command byte to the SUM byte becomes H'00. * Data (n bytes): Detailed data of a command or response * Error response (one byte): Error response to a command * Error code (one byte): Type of the error * Address (four bytes): Address for programming * Data (n bytes): Data to be programmed (the size is indicated in the response to the programming unit inquiry.) * Size (four bytes): Four-byte response to a memory read
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Section 24 Flash Memory
(3)
Inquiry and Selection States
The boot program returns information from the flash memory in response to the host's inquiry commands and sets the device code, clock mode, and bit rate in response to the host's selection command. Table 24.16 lists the inquiry and selection commands. Table 24.16 Inquiry and Selection Commands
Command H'20 H'10 H'21 H'11 H'22 Command Name Supported device inquiry Device selection Clock mode inquiry Clock mode selection Multiplication ratio inquiry Description Inquiry regarding device codes Selection of device code Inquiry regarding numbers of clock modes and values of each mode Indication of the selected clock mode Inquiry regarding the number of frequencymultiplied clock types, the number of multiplication ratios, and the values of each multiple Inquiry regarding the maximum and minimum values of the main clock and peripheral clocks Inquiry regarding the number of user boot MATs and the start and last addresses of each MAT Inquiry regarding the a number of user MATs and the start and last addresses of each MAT
H'23 H'24
Operating clock frequency inquiry User boot MAT information inquiry
H'25 H'26 H'27 H'3F H'40 H'4F
User MAT information inquiry
Block for erasing information Inquiry Inquiry regarding the number of blocks and the start and last addresses of each block Programming unit inquiry New bit rate selection Transition to programming/erasing state Boot program status inquiry Inquiry regarding the unit of program data Selection of new bit rate Erasing of user MAT and user boot MAT, and entry to programming/erasing state Inquiry into the operated status of the boot program
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Section 24 Flash Memory
The selection commands, which are device selection (H'10), clock mode selection (H'11), and new bit rate selection (H'3F), should be sent from the host in that order. When two or more selection commands are sent at once, the last command will be valid. All of these commands, except for the boot program status inquiry command (H'4F), will be valid until the boot program receives the programming/erasing transition (H'40). The host can choose the needed commands and make inquiries while the above commands are being transmitted. H'4F is valid even after the boot program has received H'40. (a) Supported Device Inquiry
The boot program will return the device codes of supported devices and the product code in response to the supported device inquiry.
Command H'20
* Command, H'20, (one byte): Inquiry regarding supported devices
Response H'30 Number of characters *** SUM Size Number of devices Product name
Device code
* Response, H'30, (one byte): Response to the supported device inquiry * Size (one byte): Number of bytes to be transmitted, excluding the command, size, and checksum, that is, the amount of data contributes by the number of devices, characters, device codes and product names * Number of devices (one byte): The number of device types supported by the boot program * Number of characters (one byte): The number of characters in the device codes and boot program's name * Device code (four bytes): ASCII code of the supporting product * Product name (n bytes): Type name of the boot program in ASCII-coded characters * SUM (one byte): Checksum The checksum is calculated so that the total number of all values from the command byte to the SUM byte becomes H'00.
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Section 24 Flash Memory
(b)
Device Selection
The boot program will set the supported device to the specified device code. The program will return the selected device code in response to the inquiry after this setting has been made.
Command H'10 Size Device code SUM
* Command, H'10, (one byte): Device selection * Size (one byte): Amount of device-code data This is fixed at 4. * Device code (four bytes): Device code (ASCII code) returned in response to the supported device inquiry * SUM (one byte): Checksum
Response H'06
* Response, H'06, (one byte): Response to the device selection command ACK will be returned when the device code matches.
Error response H'90 ERROR
* Error response, H'90, (one byte): Error response to the device selection command ERROR : (one byte): Error code H'11: Sum check error H'21: Device code error, that is, the device code does not match (c) Clock Mode Inquiry
The boot program will return the supported clock modes in response to the clock mode inquiry.
Command H'21
* Command, H'21, (one byte): Inquiry regarding clock mode
Response H'31 Size Mode *** SUM
* Response, H'31, (one byte): Response to the clock-mode inquiry * Size (one byte): Amount of data that represents the modes * Mode (two bytes): Values of the supported clock modes H'00: MD_CLK = 0 (8 to 18 MHz input) H'01: MD_CLK = 1 (16 MHz input) * SUM (one byte): Checksum
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Section 24 Flash Memory
(d)
Clock Mode Selection
The boot program will set the specified clock mode. The program will return the selected clockmode information after this setting has been made. The clock-mode selection command should be sent after the device-selection commands.
Command H'11 Size Mode SUM
* * * *
Command, H'11, (one byte): Selection of clock mode Size (one byte): Amount of data that represents the modes Mode (one byte): A clock mode returned in reply to the supported clock mode inquiry. SUM (one byte): Checksum
H'06
Response
* Response, H'06, (one byte): Response to the clock mode selection command ACK will be returned when the clock mode matches.
Error Response H'91 ERROR
* Error response, H'91, (one byte) : Error response to the clock mode selection command * ERROR : (one byte): Error code H'11: Checksum error H'22: Clock mode error, that is, the clock mode does not match.
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Section 24 Flash Memory
(e)
Multiplication Ratio Inquiry
The boot program will return the supported multiplication and division ratios.
Command H'22
* Command, H'22, (one byte): Inquiry regarding multiplication ratio
Response H'32 Size Number of types of multipli cation ***
Number of multiplication ratios *** SUM
Multiplication ratio
* Response, H'32, (one byte): Response to the multiplication ratio inquiry * Size (one byte): The amount of data that represents the number of types of multiplication, the number of multiplication ratios, and the multiplication ratios * Number of types of multiplication (one byte): The number of types of multiplication to which the device can be set (e.g. when there are two multiplied clock types, which are the main and peripheral clocks, the number of types will be H'02.) * Number of multiplication ratios (one byte): The number of types of multiplication ratios for each type (e.g. the number of multiplication ratios to which the main clock can be set and the peripheral clock can be set.) * Multiplication ratio (one byte) Multiplication ratio: The value of the multiplication ratio (e.g. when the clock-frequency multiplier is four, the value of multiplication ratio will be H'04.) Division ratio: The inverse of the division ratio, i.e. a negative number (e.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = -2) The number of multiplication ratios returned is the same as the number of multiplication ratios and as many groups of data are returned as there are types of multiplication. * SUM (one byte): Checksum
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Section 24 Flash Memory
(f)
Operating Clock Frequency Inquiry
The boot program will return the number of operating clock frequencies, and the maximum and minimum values.
Command H'23
* Command, H'23, (one byte): Inquiry regarding operating clock frequencies
Response H'33 Size Number of operating clock frequencies Maximum value of operating clock frequency
Minimum value of operating clock frequency *** SUM
* Response, H'33, (one byte): Response to operating clock frequency inquiry * Size (one byte): The number of bytes that represents the minimum values, maximum values, and the number of frequencies. * Number of operating clock frequencies (one byte): The number of supported operating clock frequency types (e.g. when there are two operating clock frequency types, which are the main and peripheral clocks, the number of types will be H'02.) * Minimum value of operating clock frequency (two bytes): The minimum value of the multiplied or divided clock frequency. The minimum and maximum values of the operating clock frequency represent the values in MHz, valid to the hundredths place of MHz, and multiplied by 100. (e.g. when the value is 17.00 MHz, it will be 2000, which is H'07D0.) * Maximum value (two bytes): Maximum value among the multiplied or divided clock frequencies. There are as many pairs of minimum and maximum values as there are operating clock frequencies. * SUM (one byte): Checksum
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Section 24 Flash Memory
(g)
User Boot MAT Information Inquiry
The boot program will return the number of user boot MATs and their addresses.
Command H'24
* Command, H'24, (one byte): Inquiry regarding user boot MAT information
Response H'34 *** SUM Size Number of areas Area-last address
Area-start address
* Response, H'34, (one byte): Response to user boot MAT information inquiry * Size (one byte): The number of bytes that represents the number of areas, area-start addresses, and area-last address * Number of Areas (one byte): The number of consecutive user boot MAT areas When user boot MAT areas are consecutive, the number of areas returned is H'01. * Area-start address (four byte): Start address of the area * Area-last address (four byte): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum (h) User MAT Information Inquiry
The boot program will return the number of user MATs and their addresses.
Command H'25
* Command, H'25, (one byte): Inquiry regarding user MAT information
Response H'35 *** SUM Size Number of areas Last address area
Start address area
* Response, H'35, (one byte): Response to the user MAT information inquiry * Size (one byte): The number of bytes that represents the number of areas, area-start address and area-last address * Number of areas (one byte): The number of consecutive user MAT areas When the user MAT areas are consecutive, the number of areas is H'01. * Area-start address (four bytes): Start address of the area
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Section 24 Flash Memory
* Area-last address (four bytes): Last address of the area There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum (i) Erased Block Information Inquiry
The boot program will return the number of erased blocks and their addresses.
Command H'26
* Command, H'26, (two bytes): Inquiry regarding erased block information
Response H'36 *** SUM Size Number of blocks Block last address
Block start address
* Response, H'36, (one byte): Response to the number of erased blocks and addresses * Size (three bytes): The number of bytes that represents the number of blocks, block-start addresses, and block-last addresses. * Number of blocks (one byte): The number of erased blocks * Block start address (four bytes): Start address of a block * Block last Address (four bytes): Last address of a block There are as many groups of data representing the start and last addresses as there are areas. * SUM (one byte): Checksum (j) Programming Unit Inquiry
The boot program will return the programming unit used to program data.
Command H'27
* Command, H'27, (one byte): Inquiry regarding programming unit
Response H'37 Size Programming unit SUM
* Response, H'37, (one byte): Response to programming unit inquiry * Size (one byte): The number of bytes that indicate the programming unit, which is fixed to 2 * Programming unit (two bytes): A unit for programming This is the unit for reception of programming. * SUM (one byte): Checksum
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Section 24 Flash Memory
(k)
New Bit-Rate Selection
The boot program will set a new bit rate and return the new bit rate. This selection should be sent after sending the clock mode selection command.
Command H'3F Number of types of multiplication SUM Size Multiplication ratio 1 Bit rate Multiplication ratio 2 Input frequency
* Command, H'3F, (one byte): Selection of new bit rate * Size (one byte): The number of bytes that represents the bit rate, input frequency, number of types of multiplication, and multiplication ratio * Bit rate (two bytes): New bit rate One hundredth of the value (e.g. when the value is 19200 bps, it will be 192, which is H'00C0.) * Input frequency (two bytes): Frequency of the clock input to the boot program This is valid to the hundredths place and represents the value in MHz multiplied by 100. (E.g. when the value is 20.00 MHz, it will be 2000, which is H'07D0.) * Number of types of multiplication (one byte): The number of multiplication to which the device can be set. * Multiplication ratio 1 (one byte) : The value of multiplication or division ratios for the main operating frequency Multiplication ratio (one byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) Division ratio: The inverse of the division ratio, as a negative number (e.g. when the clock frequency is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) * Multiplication ratio 2 (one byte): The value of multiplication or division ratios for the peripheral frequency Multiplication ratio (one byte): The value of the multiplication ratio (e.g. when the clock frequency is multiplied by four, the multiplication ratio will be H'04.) (Division ratio: The inverse of the division ratio, as a negative number (E.g. when the clock is divided by two, the value of division ratio will be H'FE. H'FE = D'-2) * SUM (one byte): Checksum
Response H'06
* Response, H'06, (one byte): Response to selection of a new bit rate When it is possible to set the bit rate, the response will be ACK.
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Section 24 Flash Memory
Error Response
H'BF
ERROR
* Error response, H'BF, (one byte): Error response to selection of new bit rate * ERROR: (one byte): Error code H'11: Sum checking error H'24: Bit-rate selection error The rate is not available. H'25: Error in input frequency This input frequency is not within the specified range. H'26: Multiplication-ratio error The ratio does not match an available ratio. H'27: Operating frequency error The frequency is not within the specified range. (4) Receive Data Check
The methods for checking of receive data are listed below. 1. Input frequency The received value of the input frequency is checked to ensure that it is within the range of minimum to maximum frequencies which matches the clock modes of the specified device. When the value is out of this range, an input-frequency error is generated. 2. Multiplication ratio The received value of the multiplication ratio or division ratio is checked to ensure that it matches the clock modes of the specified device. When the value is out of this range, an inputfrequency error is generated. 3. Operating frequency error Operating frequency is calculated from the received value of the input frequency and the multiplication or division ratio. The input frequency is input to the LSI and the LSI is operated at the operating frequency. The expression is given below. Operating frequency = Input frequency x Multiplication ratio, or Operating frequency = Input frequency / Division ratio The calculated operating frequency should be checked to ensure that it is within the range of minimum to maximum frequencies which are available with the clock modes of the specified device. When it is out of this range, an operating frequency error is generated.
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Section 24 Flash Memory
4. Bit rate To facilitate error checking, the value (n) of clock select (CKS) in the serial mode register (SMR), and the value (N) in the bit rate register (BRR), which are found from the peripheral operating clock frequency () and bit rate (B), are used to calculate the error rate to ensure that it is less than 4%. If the error is more than 4%, a bit rate error is generated. The error is calculated using the following expression:
Error (%) = {[
x 106
(N + 1) x B x 64 x 2(2xn - 1)
] - 1} x 100
When the new bit rate is selectable, the rate will be set in the register after sending ACK in response. The host will send an ACK with the new bit rate for confirmation and the boot program will response with that rate.
Confirmation H'06
* Confirmation, H'06, (one byte): Confirmation of a new bit rate
Response H'06
* Response, H'06, (one byte): Response to confirmation of a new bit rate The sequence of new bit-rate selection is shown in figure 24.26.
Host
Setting a new bit rate
H'06 (ACK)
Waiting for one-bit period at the specified bit rate
Boot program
Setting a new bit rate
Setting a new bit rate
H'06 (ACK) with the new bit rate H'06 (ACK) with the new bit rate
Figure 24.26 New Bit-Rate Selection Sequence
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Section 24 Flash Memory
(5)
Transition to Programming/Erasing State
The boot program will transfer the erasing program, and erase the user MATs and user boot MATs in that order. On completion of this erasure, ACK will be returned and will enter the programming/erasing state. The host should select the device code, clock mode, and new bit rate with device selection, clockmode selection, and new bit-rate selection commands, and then send the command for the transition to programming/erasing state. These procedures should be carried out before sending of the programming selection command or program data.
Command H'40
* Command, H'40, (one byte): Transition to programming/erasing state
Response H'06
* Response, H'06, (one byte): Response to transition to programming/erasing state The boot program will send ACK when the user MAT and user boot MAT have been erased by the transferred erasing program.
Error Response H'C0 H'51
* Error response, H'C0, (one byte): Error response for user boot MAT blank check * Error code, H'51, (one byte): Erasing error An error occurred and erasure was not completed. (6) Command Error
A command error will occur when a command is undefined, the order of commands is incorrect, or a command is unacceptable. Issuing a clock-mode selection command before a device selection or an inquiry command after the transition to programming/erasing state command, are examples.
Error Response H'80 H'xx
* Error response, H'80, (one byte): Command error * Command, H'xx, (one byte): Received command
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Section 24 Flash Memory
(7)
Command Order
The order for commands in the inquiry selection state is shown below. 1. A supported device inquiry (H'20) should be made to inquire about the supported devices. 2. The device should be selected from among those described by the returned information and set with a device-selection (H'10) command. 3. A clock-mode inquiry (H'21) should be made to inquire about the supported clock modes. 4. The clock mode should be selected from among those described by the returned information and set. 5. After selection of the device and clock mode, inquiries for other required information should be made, such as the multiplication-ratio inquiry (H'22) or operating frequency inquiry (H'23), which are needed for a new bit-rate selection. 6. A new bit rate should be selected with the new bit-rate selection (H'3F) command, according to the returned information on multiplication ratios and operating frequencies. 7. After selection of the device and clock mode, the information of the user boot MAT and user MAT should be made to inquire about the user boot MATs information inquiry (H'24), user MATs information inquiry (H'25), erased block information inquiry (H'26), and programming unit inquiry (H'27). 8. After making inquiries and selecting a new bit rate, issue the transition to programming/erasing state command (H'40). The boot program will then enter the programming/erasing state.
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Section 24 Flash Memory
(8)
Programming/Erasing State
A programming selection command makes the boot program select the programming method, a 128-byte programming command makes it program the memory with data, and an erasing selection command and block erasing command make it erase the block. Table 24.17 lists the programming/erasing commands. Table 24.17 Programming/Erasing Commands
Command H'42 H'43 H'50 H'48 H'58 H'52 H'4A H'4B H'4C H'4D H'4C H'4D H'4F Command Name Description
User boot MAT programming selection Transfers the user boot MAT programming program User MAT programming selection 128-byte programming Erasing selection Block erasing Memory read User boot MAT sum check User MAT sum check User boot MAT blank check User MAT blank check User boot MAT blank check User MAT blank check Boot program status inquiry Transfers the user MAT programming program Programs 128 bytes of data Transfers the erasing program Erases a block of data Reads the contents of memory Checks the checksum of the user boot MAT Checks the checksum of the user MAT Checks the blank data of the user boot MAT Checks the blank data of the user MAT Checks whether the contents of the user boot MAT are blank Checks whether the contents of the user MAT are blank Inquires into the boot program's status
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Section 24 Flash Memory
* Programming Programming is executed by the programming selection and 128-byte programming commands. Firstly, the host should send the programming selection command and select the programming method and programming MATs. There are two programming selection commands, and selection is according to the area and method for programming. 1. User boot MAT programming selection 2. User MAT programming selection After issuing the programming selection command, the host should send the 128-byte programming command. The 128-byte programming command that follows the selection command represents the data programmed according to the method specified by the selection command. When more than 128-byte data is programmed, 128-byte commands should repeatedly be executed. Sending a 128-byte programming command with H'FFFFFFFF as the address will stop the programming. On completion of programming, the boot program will wait for selection of programming or erasing. Where the sequence of programming operations that is executed includes programming with another method or of another MAT, the procedure must be repeated from the programming selection command. The sequence for the programming selection and 128-byte programming commands is shown in figure 24.27.
Host Programming selection (H'42, H'43)
Boot program
Transfer of the programming program
ACK 128-byte programming (address, data) Repeat ACK 128-byte programming (H'FFFFFFFF) ACK Programming
Figure 24.27 Programming Sequence
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Section 24 Flash Memory
* Erasure Erasure is executed by the erasure selection and block erasure commands. Firstly, erasure is selected by the erasure selection command and the boot program then erases the specified block. The command should be repeatedly executed if two or more blocks are to be erased. Sending a block erasure command from the host with the block number H'FF will stop the erasure operating. On completion of erasing, the boot program will wait for selection of programming or erasing. The sequence for the erasure selection and block erasure commands is shown in figure 24.28
Host Boot program
Preparation for erasure (H'48)
Transfer of erasure program
ACK
Erasure (Erasure block number)
Repeat
Erasure ACK
Erasure (H'FF) ACK
Figure 28.26 Erasure Sequence
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Section 24 Flash Memory
(a)
User Boot MAT Programming Selection
The boot program will transfer a programming program. The data is programmed to the user boot MATs by the transferred programming program.
Command H'42
* Command, H'42, (one byte): User boot MAT programming selection
Response H'06
* Response, H'06, (one byte): Response to user boot MAT programming selection When the programming program has been transferred, the boot program will return ACK.
Error Response H'C2 ERROR
* Error response : H'C2 (1 byte): Error response to user boot MAT programming selection * ERROR : (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed) (b) User MAT Programming Selection
The boot program will transfer a program for user MAT programming selection. The data is programmed to the user MATs by the transferred program for programming.
Command H'43
* Command, H'43, (one byte): User MAT programming selection
Response H'06
* Response, H'06, (one byte): Response to user MAT programming selection When the programming program has been transferred, the boot program will return ACK.
Error Response H'C3 ERROR
* Error response : H'C3 (1 byte): Error response to user MAT programming selection * ERROR : (1 byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed)
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Section 24 Flash Memory
(c)
128-Byte Programming
The boot program will use the programming program transferred by the programming selection to program the user boot MATs or user MATs in response to 128-byte programming.
Command H'50 Data *** SUM Address ***
* Command, H'50, (one byte): 128-byte programming * Programming Address (four bytes): Start address for programming Multiple of the size specified in response to the programming unit inquiry (i.e. H'00, H'01, H'00, H'00 : H'01000000) * Program data (128 bytes): Data to be programmed The size is specified in the response to the programming unit inquiry. * SUM (one byte): Checksum
Response H'06
* Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK.
Error Response H'D0 ERROR
* Error response, H'D0, (one byte): Error response for 128-byte programming * ERROR: (one byte): Error code H'11: Checksum Error H'2A: Address error The address is not in the specified MAT. H'53: Programming error A programming error has occurred and programming cannot be continued. The specified address should match the unit for programming of data. For example, when the programming is in 128-byte units, the lower eight bits of the address should be H'00 or H'80. When there are less than 128 bytes of data to be programmed, the host should fill the rest with H'FF. Sending the 128-byte programming command with the address of H'FFFFFFFF will stop the programming operation. The boot program will interpret this as the end of the programming and wait for selection of programming or erasing.
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Section 24 Flash Memory
Command
H'50
Address
SUM
* Command, H'50, (one byte): 128-byte programming * Programming Address (four bytes): End code is H'FF, H'FF, H'FF, H'FF. * SUM (one byte): Checksum
Response H'06
* Response, H'06, (one byte): Response to 128-byte programming On completion of programming, the boot program will return ACK.
Error Response H'D0 ERROR
* Error Response, H'D0, (one byte): Error response for 128-byte programming * ERROR: (one byte): Error code H'11: Checksum error H'53: Programming error An error has occurred in programming and programming cannot be continued. (d) Erasure Selection
The boot program will transfer the erasure program. User MAT data is erased by the transferred erasure program.
Command H'48
* Command, H'48, (one byte): Erasure selection
Response H'06
* Response, H'06, (one byte): Response for erasure selection After the erasure program has been transferred, the boot program will return ACK.
Error Response H'C8 ERROR
* Error Response, H'C8, (one byte): Error response to erasure selection * ERROR: (one byte): Error code H'54: Selection processing error (transfer error occurs and processing is not completed)
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Section 24 Flash Memory
(e)
Block Erasure
The boot program will erase the contents of the specified block.
Command H'58 Size Block number SUM
* Command, H'58, (one byte): Erasure * Size (one byte): The number of bytes that represents the erase block number This is fixed to 1. * Block number (one byte): Number of the block to be erased * SUM (one byte): Checksum
Response H'06
* Response, H'06, (one byte): Response to Erasure After erasure has been completed, the boot program will return ACK.
Error Response H'D8 ERROR
* Error Response, H'D8, (one byte): Response to Erasure * ERROR (one byte): Error code H'11: Sum check error H'29: Block number error Block number is incorrect. H'51: Erasure error An error has occurred during erasure. On receiving block number H'FF, the boot program will stop erasure and wait for a selection command.
Command H'58 Size Block number SUM
* Command, H'58, (one byte): Erasure * Size, (one byte): The number of bytes that represents the block number This is fixed to 1. * Block number (one byte): H'FF Stop code for erasure * SUM (one byte): Checksum
Response H'06
* Response, H'06, (one byte): Response to end of erasure (ACK) When erasure is to be performed after the block number H'FF has been sent, the procedure should be executed from the erasure selection command.
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Section 24 Flash Memory
(f)
Memory Read
The boot program will return the data in the specified address.
Command H'52 Size Area Read address SUM
Read size
* Command: H'52 (1 byte): Memory read * Size (1 byte): Amount of data that represents the area, read address, and read size (fixed at 9) * Area (1 byte) H'00: User boot MAT H'01: User MAT An address error occurs when the area setting is incorrect. * Read address (4 bytes): Start address to be read from * Read size (4 bytes): Size of data to be read * SUM (1 byte): Checksum
Response H'52 Data SUM Read size ***
* * * *
Response: H'52 (1 byte): Response to memory read Read size (4 bytes): Size of data to be read Data (n bytes): Data for the read size from the read address SUM (1 byte): Checksum
H'D2 ERROR
Error Response
* Error response: H'D2 (1 byte): Error response to memory read * ERROR: (1 byte): Error code H'11: Sum check error H'2A: Address error The read address is not in the MAT. H'2B: Size error The read size exceeds the MAT.
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Section 24 Flash Memory
(g)
User Boot MAT Sum Check
The boot program will return the byte-by-byte total of the contents of the bytes of the user-boot program, as a four-byte value.
Command H'4A
* Command, H'4A, (one byte): Sum check for user-boot program
Response H'5A Size Checksum of user boot program SUM
* Response, H'5A, (one byte): Response to the sum check of user-boot program * Size (one byte): The number of bytes that represents the checksum This is fixed to 4. * Checksum of user boot program (four bytes): Checksum of user boot MATs The total of the data is obtained in byte units. * SUM (one byte): Sum check for data being transmitted (h) User MAT Sum Check
The boot program will return the byte-by-byte total of the contents of the bytes of the user program.
Command H'4B
* Command, H'4B, (one byte): Sum check for user program
Response H'5B Size Checksum of user program SUM
* Response, H'5B, (one byte): Response to the sum check of the user program * Size (one byte): The number of bytes that represents the checksum This is fixed to 4. * Checksum of user boot program (four bytes): Checksum of user MATs The total of the data is obtained in byte units. * SUM (one byte): Sum check for data being transmitted
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Section 24 Flash Memory
(i)
User Boot MAT Blank Check
The boot program will check whether or not all user boot MATs are blank and return the result.
Command H'4C
* Command, H'4C, (one byte): Blank check for user boot MAT
Response H'06
* Response, H'06, (one byte): Response to the blank check of user boot MAT If all user MATs are blank (H'FF), the boot program will return ACK.
Error Response H'CC H'52
* Error Response, H'CC, (one byte): Response to blank check for user boot MAT * Error Code, H'52, (one byte): Erasure has not been completed. (j) User MAT Blank Check
The boot program will check whether or not all user MATs are blank and return the result.
Command H'4D
* Command, H'4D, (one byte): Blank check for user MATs
Response H'06
* Response, H'06, (one byte): Response to the blank check for user MATs If the contents of all user MATs are blank (H'FF), the boot program will return ACK.
Error Response H'CD H'52
* Error Response, H'CD, (one byte): Error response to the blank check of user MATs. * Error code, H'52, (one byte): Erasure has not been completed.
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Section 24 Flash Memory
(k)
Boot Program State Inquiry
The boot program will return indications of its present state and error condition. This inquiry can be made in the inquiry/selection state or the programming/erasing state.
Command H'4F
* Command, H'4F, (one byte): Inquiry regarding boot program's state
Response H'5F Size Status ERROR SUM
* * * *
Response, H'5F, (one byte): Response to boot program state inquiry Size (one byte): The number of bytes. This is fixed to 2. Status (one byte): State of the boot program ERROR (one byte): Error status ERROR = 0 indicates normal operation. ERROR = 1 indicates error has occurred.
* SUM (one byte): Sum check Table 24.18 Status Code
Code H'11 H'12 H'13 H'1F H'31 H'3F H'4F H'5F Description Device selection wait Clock mode selection wait Bit rate selection wait Programming/erasing state transition wait (bit rate selection is completed) Programming state for erasure Programming/erasing selection wait (erasure is completed) Program data receive wait Erase block specification wait (erasure is completed)
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Section 24 Flash Memory
Table 24.19 Error Code
Code H'00 H'11 H'12 H'21 H'22 H'24 H'25 H'26 H'27 H'29 H'2A H'2B H'51 H'52 H'53 H'54 H'80 H'FF Description No error Sum check error Program size error Device code mismatch error Clock mode mismatch error Bit rate selection error Input frequency error Multiplication ratio error Operating frequency error Block number error Address error Data length error Erasure error Erasure incomplete error Programming error Selection processing error Command error Bit-rate-adjustment confirmation error
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Section 24 Flash Memory
24.14
Usage Notes
1. The initial state of the product at its shipment is in the erased state. For the product whose revision of erasing is undefined, we recommend to execute automatic erasure for checking the initial state (erased state) and compensating. 2. For the PROM programmer suitable for programmer mode in this LSI and its program version, refer to the instruction manual of the socket adapter. 3. If the socket, socket adapter, or product index of the PROM programmer do not match the specifications, too much current flows and the product may be damaged. 4. Use a PROM programmer that supports the device with 1-Mbyte on-chip flash memory and 3.3-V programming voltage. Use only the specified socket adapter. 5. Do not turn off the Vcc power supply nor remove the chip from the PROM programmer during programming/erasure in which a high voltage is applied to the flash memory. Doing so may damage the flash memory permanently. If a reset is input, the reset must be released after the reset input period of at least 100ms. 6. The flash memory is not accessible until FKEY is cleared after programming/erasure starts. If the operating mode is changed and this LSI is restarted by a reset immediately after programming/erasure has finished, secure the reset input period (period of RES = 0) of at least 100s. Transition to the reset state during programming/erasure is inhibited. If a reset is input accidentally, the reset must be released after the reset input period of at least 100s. 7. At powering on or off the Vcc power supply, fix the RES pin to low and set the flash memory to hardware protection state. This power on/off timing must also be satisfied at a power-off and power-on caused by a power failure and other factors. 8. In on-board programming mode or programmer mode, programming of the 128-byte programming-unit block must be performed only once. Perform programming in the state where the programming-unit block is fully erased. 9. When the chip is to be reprogrammed with the programmer after execution of programming or erasure in on-board programming mode, it is recommended that automatic programming is performed after execution of automatic erasure. 10. To program the flash memory, the program data and program must be allocated to addresses which are higher than those of the external interrupt vector table and H'FF must be written to all the system reserved areas in the exception handling vector table. 11. The programming program that includes the initialization routine and the erasing program that includes the initialization routine are each 4 Kbytes or less. Accordingly, when the CPU clock frequency is 35 MHz, the download for each program takes approximately 60 s at the maximum.
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Section 24 Flash Memory
12. A programming/erasing program for the flash memory used in a conventional F-ZTAT H8, H8S microcomputer which does not support download of the on-chip program by setting the SCO bit in FCCS to 1 cannot run in this LSI. Be sure to download the on-chip program to execute programming/erasure of the flash memory in this F-ZTAT H8SX microcomputer. 13. Unlike a conventional F-ZTAT H8 or H8S microcomputers, measures against a program crash are not taken by WDT while programming/erasing and downloading a programming/erasing program. When needed, measures should be taken by user. A periodic interrupt generated by the WDT can be used as the measures, as an example. In this case, the interrupt generation period should take into consideration time to program/erase the flash memory. 14. When downloading the programming/erasing program, do not clear the SCO bit in FCCS to 0 immediately after setting it to 1. Otherwise, download cannot be performed normally. Immediately after executing the instruction to set the SCO bit to 1, dummy read of the FCCS must be executed twice. 15. The contents of general registers ER0 and ER1 are not saved during download of an on-chip program, initialization, programming, or erasure. When needed, save the general registers before a download request or before execution of initialization, programming, or erasure using the procedure program.
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Section 24 Flash Memory
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Section 25 Boundary Scan
Section 25 Boundary Scan
This LSI has boundary scan function, which is a serial I/O interface based on the JTAG (Joint Test Action Group, IEEE Std.1149.1 and IEEE Standard Test Access Port and Boundary-Scan Architecture).
25.1
Features
* Boundary scan valid single chip mode when the EMLE pin= 0 in MCU operating mode 3 * P62, P63, P64, P65, and WDTOVF are pins only for boundary scan when boundary scan is valid * Six test modes: BYPASS mode EXTEST mode SAMPLE/PRELOAD mode CLAMP mode HIGHZ mode IDCODE mode
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Section 25 Boundary Scan
25.2
Block Diagram of Boundary Scan Function
Figure 25.1 shows the block diagram of the boundary scan function.
TDI
Shift register
JTBPR
JTBSR
JTIR
JTDIR
TDO
MUX
TCK TMS TRST TAP controller Decoder
[Legend] JTBPR: JTBSR: JTIR: JTDIR:
Bypass register Boundary scan register Instruction register ID register
Figure 25.1 Block Diagram of Boundary Scan Function
25.3
Input/Output Pins
Table 25.1 shows the I/O pins used in the boundary scan function. Table 25.1 Pin Configuration
Pin Name TCK I/O Input Description Test clock input pin Clock signal for boundary scan. Input the clock the duty cycle of which is 50 percent when boundary scan function is used. TMS TDI TDO TRST Input Input Output Input Test mode select pin Test data input pin Test data output pin Test reset input pin
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Section 25 Boundary Scan
25.4
Register Descriptions
Boundary scan has the following four registers. These registers cannot be accessed from the CPU. * * * * Introduction register (JTIR) Bypass register (JTBPR) Boundary scan register (JTBSR) IDCODE register (JTIDR)
Instructions can be input to the instruction register (JTIR) via the test data input pin (TDI) by serial transfer. The bypass register (JTBPR), which is a 1-bit register, is connected between the TDI and TDO pins in BYPASS mode. The boundary scan register (JTBSR), which is a JTBSR-bit register (see table 25.4), is connected between the TDI and TDO pins when test data are being shifted in. None of the registers is accessible from the CPU. Table 25.2 shows the availability of serial transfer for the registers. Table 25.2 Serial Transfers for Registers
Register Abbreviation JTIR JTBPR JTBSR JTID Serial Input Available Available Available Not available Serial Output Not available Available Available Available
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Section 25 Boundary Scan
25.4.1
Instruction Register (JTIR)
JTIR is a 16-bit register. JTAG instructions can be transferred to JTIR by serial input from the TDI pin. JTIR is initialized when the TRST signal is low level, when the TAP controller is in the Test-Logic-Reset state, and when this LSI is placed in hardware standby mode. JTIR is not initialized by a reset or entry to software standby mode. Instructions must be serially transferred in 4-bit units. When an instruction with more than 4 bits is being transferred, the last four bits of the serial data are stored in JTIR.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 TS3 0 7 0 14 TS2 0 6 0 13 TS1 0 5 0 12 TS0 0 4 0 11 0 3 0 10 0 2 0 9 0 1 0 8 0 0 0
Bit
Bit Name
Initial Value All 0 All 0
R/W R/W R
Descriptions Test Bit Set Specify an instruction as shown in table 25.3. Reserved These bits are always read as 0. The write value should always 0.
15 to 12 TS[3:0] 11 to 0
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Section 25 Boundary Scan
Table 25.3 Boundary Scan Instructions
TS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Instruction EXTEST IDCODE (initial value) CLAMP HIGHZ SAMPLE/PRELOAD Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved BYPASS
25.4.2
Bypass Register (JTBPR)
JTBPR is a 1-bit register and is connected between the TDI and TDO pins when JTIR is set to BYPASS mode. JTBPR cannot be read from or written to by the CPU. 25.4.3 Boundary Scan Register (JTBSR)
JTBSR is a shift register to control the external input and output pins of this LSI and is distributed across the pads. The initial values are undefined. JTBSR cannot be accessed by the CPU. The EXTEST, SAMPLE/PRELOAD, CLAMP, and HIGHZ instructions are issued to apply JTBSR in boundary-scan testing conformant to the JTAG standard. Table 25.5 shows the correspondence between the JTBSR bits and the pins of this LSI.
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Section 25 Boundary Scan
Table 25.4 Relationship between Pins and JTBSR Bits
from TDI Pin No. 3 Pin Name PB3 Input/Output Input Output enable Output 4 5 MD2 PM0 Input Input Output enable Output 6 PM1 Input Output enable Output 7 PM2 Input Output enable Output 8 PF4 Input Output enable Output 9 PF3 Input Output enable Output 11 PF2 Input Output enable Output 12 PF1 Input Output enable Output 13 PF0 Input Output enable Output 14 PE7 Input Output enable Output 15 PE6 Input Output enable Output Bit Name 296 295 294 290 289 288 287 285 284 283 281 280 279 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 246 29 PD3 28 PD4 27 PD5 25 PD6 24 PD7 23 PE0 22 PE1 21 PE2 20 PE3 18 PE4 Pin No. 16 Pin Name PE5 Input/Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Bit Name 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213
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Section 25 Boundary Scan Pin No. 30 Pin Name PD2 Input/Output Input Output enable Output 31 PD1 Input Output enable Output 32 PD0 Input Output enable Output 34 PM3 Input Output enable Output 35 PM4 Input Output enable Output 40 41 43 VBUS MD_CLK P20 Input Input Input Output enable Output 45 P21 Input Output enable Output 46 P22 Input Output enable Output 47 P23 Input Output enable Output 48 P24 Input Output enable Output Bit Name 212 211 210 209 208 207 206 205 204 202 201 200 198 197 196 195 194 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 60 PH6 59 PH5 58 PH4 61 PH7 56 PH3 55 PH2 54 PH1 52 53 NMI PH0 51 P27 50 P26 Pin No. 49 Pin Name P25 Input/Output Input Output enable Output Input Output enable Output Input Output enable Output Input Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Bit Name 169 168 167 157 156 155 154 153 152 151 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121
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Section 25 Boundary Scan Pin No. 64 Pin Name PI1 Input/Output Input Output enable Output 65 PI2 Input Output enable Output 66 PI3 Input Output enable Output 63 PI0 Input Output enable Output 68 PI4 Input Output enable Output 69 PI5 Input Output enable Output 70 PI7 Input Output enable Output 70 PI6 Input Output enable Output 71 P10 Input Output enable Output 72 P11 Input Output enable Output 73 P12 Input Output enable Output Bit Name 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 112 PA2 111 PA1 97 110 MD0 PA0 90 P61 89 P60 87 P17 86 P16 80 P15 79 P14 Pin No. 74 Pin Name P13 Input/Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Output enable Output Input Input Output enable Output Input Output enable Output Input Output enable Output Bit Name 87 86 85 78 77 76 75 74 73 72 71 70 69 68 67 60 59 58 54 53 52 51 33 32 31 30 29 28 27 26 25
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Section 25 Boundary Scan Pin No. 113 Pin Name PA3 Input/Output Input Output enable Output 114 PA4 Input Output enable Output 115 PA5 Input Output enable Output 116 PA6 Input Output enable Output 118 PA7 Input Output enable Output 120 PB0 Input Output enable Output 1 PB1 Input Output enable Output 2 PB2 Input Output enable Output to TDO Bit Name 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1
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Section 25 Boundary Scan
25.4.4
IDCODE Register (JTID)
JTID is a 32-bit register. JTID data is output from the TDO pin when the IDCODE instruction has been executed. Data cannot be written to JTID from the TDI pin.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DID31 DID30 DID29 DID28 DID27 DID26 DID25 DID24 DID23 DID22 DID21 DID20 DID19 DID18 DID17 DID16
R/W 15
R/W 14
R/W 13
R/W 12
R/W 11
R/W 10
R/W 9 DID9
R/W 8 DID8
R/W 7 DID7
R/W 6 DID6
R/W 5 DID5
R/W 4 DID4
R/W 3 DID3
R/W 2 DID2
R/W 1 DID1
R/W 0 DID0
DID15 DID14 DID13 DID12 DID11 DID10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Name
Initial Value R/W H'0803A447
Descriptions JTID is a register the value showing the decide IDCODE is fixed.
31 to 0 DID31 to DID0
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Section 25 Boundary Scan
25.5
Operations
The boundary scan functionality is valid when the EMLE pin is set t o 0 and this LSI is in MCU operation mode 3. 25.5.1 TAP Controller
Figure 25.2 shows the state transition diagram of the TAP controller.
1
Test -logic-reset 0 1 1 Select-DR 0 0 1 Capture-DR 0 Shift-DR 1 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 0 Exit2-IR 1 Update-IR 1 0 Exit1-IR 0 Pause-IR 1 0 0 1 Capture-IR 0 Shift-IR 1 1 0 Select-IR 1
0
Run-test/idle
Figure 25.2 State Transitions of the TAP Controller
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Section 25 Boundary Scan
25.5.2
Commands
BYPASS (Instruction Code: B'1111): The BYPASS instruction is an instruction that drives the bypass register (JTBPR). This instruction shortens the shift path, facilitating the transfer of serial data to other LSIs on a printed-circuit board at higher speeds. While this instruction is being executed, the test circuit has no effect on the system circuits. The bypass register (JTBPR) is connected between the TDI and TDO pins. Bypass operation is initiated from shift-DR operation. The TDO is at 0 in the first clock cycle in the shift-DR state; in the subsequent clock cycles, the TDI signal is output on the TDO pin. EXTEST (Instruction Code: B'0000): The EXTEST instruction is used to test external circuits when this LSI is installed on the printed circuit board. If this instruction is executed, output pins are used to output test data (specified by the SAMPLE/PRELOAD instruction) from the boundary scan register to the print circuit board, and input pins are used to input test result. SAMPLE/PRELOAD (Instruction Code: B'0100): The SAMPLE/PRELOAD instruction is used to input data from the LSI internal circuits to the boundary scan register, output data from scan path, and reload the data to the scan path. While this instruction is executed, input signals are directly input to the LSI and output signals are also directly output to the external circuits. The LSI system circuit is not affected by this function. In SAMPLE operation, the boundary scan register latches the snap shot of data transferred from input pins to internal circuit or data transferred from internal circuit to output pins. The latched data is read from the scan path. The scan register latches the snap data at the rising edge of the TCK in Capture-DR state. The scan register latches snap shot without affecting the LSI normal operation. In PRELOAD operation, initial value is written from the scan path to the parallel output latch of the boundary scan register prior to the EXTEST instruction execution. If the EXTEST is executed without executing this PRELOAD operation, undefined values are output from the beginning to the end (transfer to the output latch) of the EXTEST sequence. (In EXTEST instruction, output parallel latches are always output to the output pins.) IDCODE (Instruction Code: B'0001): When the IDCODE instruction is selected, IDCODE register value is output to the TDO in Shift-DR state of the TAP controller. In this case, IDCODE register value is output from the LSB. During this instruction execution, test circuit does not affect the system circuit. INSTR is initialized by the IDCODE instruction in Test-Logic-Reset state of the TAP controller.
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Section 25 Boundary Scan
CLAMP (Instruction Code: B'0010): When the CLAMP instruction is selected, output pins output the boundary scan register value which was specified by the SAMPLE/PRELOAD instruction in advance. While the CLAMP instruction is selected, the status of boundary scan register is maintained regardless of the TAP controller state. BYPASS is connected between TDI and TDO, the same operation as BYPASS instruction can be achieved. This instruction connects the bypass register (JTBPR) between the TDI and TDO pins, leading to the same operation as when BYPASS mode has been selected. HIGHZ (Instruction Code: B'0011): When the HIGHZ instruction is selected, all output pins enter high-impedance state. While the HIGHZ instruction is selected, the status of boundary scan register is maintained regardless of the state of the TAP controller. BYPASS is connected between TDI and TDO pins, leading to the same operation as when the BYPASS instruction has been selected.
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Section 25 Boundary Scan
25.6
Usage Notes
1. In serial transfer, data are input or output in LSB order (see figure 25.3).
From TDI pin JTIR and JTIDR Bit 31 Bit 30
Shift register
. . .
. . .
Serial data input/output in LSB order
Bit 1 Bit 0 To TDO pin Notes: Serial data output from JTIR to TDO is not possible. Serial data input from TDI to JTIDR is not possible.
Figure 25.3 Serial Data Input/Output 2. If a pin with open-drain function is SAMPLEed while its open-drain function is enabled and while the corresponding OUT register is set to 1, the corresponding Control register is cleared to 0 (the pin status is Hi-Z). If the pin is SAMPLEed while the corresponding OUT register is cleared to 0, the corresponding Control register is 1 (the pin status is 0) 3. Pins of the boundary scan (TCK, TDI, TMS, and TRST) have to be pulled up by pull-up resistors. 4. Power supply pins (VCC, VCL, VSS, AVCC, AVSS, AVref, PLLVCC, PLLVSS, DrVCC, and DrVSS) cannot be boundary-scanned. 5. Clock pins (EXTAL and XTAL) cannot be boundary-scanned. 6. Reset and standby signals (RES and STBY) cannot be boundary-scanned. 7. Boundary scan pins (TCK, TMS, TRST, TDI, and TDO) cannot be boundary-scanned. 8. The boundary scan function is not available when this LSI are in the following states. (1) Reset state (2) Hardware standby mode, software standby mode, and deep software standby mode
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Section 26 Clock Pulse Generator
Section 26 Clock Pulse Generator
This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (I), peripheral module clock (P), external bus clock (B), and USB clock (cku). The clock pulse generator consists of a main clock oscillator, frequency divider, PLL (phaselocked loop) circuit, waveform generation circuit, and selector. Figure 26.1 is a block diagram of the clock pulse generator. The frequency divider, PLL circuit, and selector can change the clock frequency. Software changes the frequency through the setting of the system clock control register (SCKCR). This LSI supports five clocks: a system clock provided to the CPU and bus masters, a peripheral module clock provided to the peripheral modules, an external bus clock provided to the external bus and a USB clock provided to the USB module. Frequencies of the peripheral module clock, the external bus clock, and the system clock can be set independently, although the peripheral module clock and the external bus clock operate with the frequency lower than the system clock frequency. The USB module requires the 48-MHz clock. Set the external clock frequency and the MD_CLK pin so that the USB clock (cku) frequency becomes 48 MHz. Note that the MD_CLK pin setting also changes the frequencies of the peripheral module clock, the external bus clock, and the system clock.
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Section 26 Clock Pulse Generator
SCKCR ICK2 to ICK0 Selector cks System clock (I) (to the CPU, and bus masters)
MD_CLK
SCKCR EXTAL x 4 (2)* x 2 (1) x 1 (1/2) x 1/2 (setting prohibited) PCK2 to PCK0 ckm Peripheral module clock (P) (to peripheral modules)
EXTAL XTAL Oscillator
Divider
Selector
PLL circuit
SCKCR BCK2 to BCK0 Selector ckb External bus clock (B) (to the B pin)
EXTAL x 4 (3)
cku
USB clock (cku) (to USB)
Note:
* Values in parentheses are setting values when MD_CLK = 1.
Figure 26.1 Block Diagram of Clock Pulse Generator Table 26.1 Selection of Clock Pulse Generator
MD_CLK 0 1 EXTAL Input Clock Frequencies 8 MHz to 18 MHz 16 MHz I/P/B EXTAL x4, x2, x1, x1/2 EXTAL x2, x1, x1/2 USB Clock (cku) EXTAL x4 EXTAL x3
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Section 26 Clock Pulse Generator
26.1
Register Description
The clock pulse generator has the following registers. * System clock control register (SCKCR) 26.1.1 System Clock Control Register (SCKCR)
SCKCR controls B output control and frequencies of the system, peripheral module, and external bus clocks.
Bit Bit Name Initial Value R/W Bit Bit Name Initial Value R/W 15 PSTOP1 0 R/W 7 0 R/W 14 0 R/W 6 PCK2 0 R/W 13 0 R/W 5 PCK1 1 R/W 12 0 R/W 4 PCK0 0 R/W 11 0 R/W 3 0 R/W 10 ICK2 0 R/W 2 BCK2 0 R/W 9 ICK1 1 R/W 1 BCK1 1 R/W 8 ICK0 0 R/W 0 BCK0 0 R/W
Bit 15
Bit Name PSTOP1
Initial Value 0
R/W R/W
Description B Clock Output Enable Controls output on PA7. * Normal operation 0: output 1: Fixed high
14 to 11
All 0
R/W
Reserved Although these bits are readable/writable, only 0 should be written to.
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Section 26 Clock Pulse Generator
Bit 10 9 8
Bit Name ICK2 ICK1 ICK0
Initial Value 0 1 0
R/W R/W R/W R/W
Description System Clock (I) Select These bits select the frequency of the system clock provided to the CPU, EXDMAC, DMAC, and DTC. The ratio to the input clock is as follows: ICK (2:0) MD_CLK = 0 000: 001: 010: 011: 1XX: x4 x2 x1 x 1/2 Setting prohibited MD_CLK = 1 x2 x1 x 1/2 Setting prohibited
The frequencies of the peripheral module clock and external bus clock change to the same frequency as the system clock if the frequency of the system clock is lower than that of the two clocks. 7 0 R/W Reserved Although this bit is readable/writable, only 0 should be written to. 6 5 4 PCK2 PCK1 PCK0 0 1 0 R/W R/W R/W Peripheral Module Clock (P) Select These bits select the frequency of the peripheral module clock. The ratio to the input clock is as follows: PCK (2:0) MD_CLK = 0 000: 001: 010: 011: 1XX: x4 x2 x1 x 1/2 Setting prohibited MD_CLK = 1 x2 x1 x 1/2 Setting prohibited
The frequency of the peripheral module clock should be lower than that of the system clock. Though these bits can be set so as to make the frequency of the peripheral module clock higher than that of the system clock, the clocks will have the same frequency in reality.
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Section 26 Clock Pulse Generator
Bit 3
Bit Name
Initial Value 0
R/W R/W
Description Reserved Although this bit is readable/writable, only 0 should be written to.
2 1 0
BCK2 BCK1 BCK0
0 1 0
R/W R/W R/W
External Bus Clock (B) Select These bits select the frequency of the external bus clock. The ratio to the input clock is as follows: BCK (2:0) MD_CLK = 0 000: 001: 010: 011: 1XX: x4 x2 x1 x 1/2 Setting prohibited MD_CLK = 1 x2 x1 x 1/2 Setting prohibited
The frequency of the external bus clock should be lower than that of the system clock. Though these bits can be set so as to make the frequency of the external bus clock higher than that of the system clock, the clocks will have the same frequency in reality. Note: X: Don't care
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Section 26 Clock Pulse Generator
26.2
Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 26.2.1 Connecting Crystal Resonator
A crystal resonator can be connected as the example in figure 26.2. Select the damping resistance Rd according to table 26.2. An AT-cut parallel-resonance type should be used. When providing the clock from the crystal resonator, the frequency should be in the range of 8 to 18 MHz.
CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 pF to 22 pF
Figure 26.2 Connection of Crystal Resonator (Example) Table 26.2 Damping Resistance Value
Frequency (MHz) Rd () 8 200 12 0 16 0 18 0
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Section 26 Clock Pulse Generator
Figure 26.3 shows an equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 26.3.
CL L XTAL Rs EXTAL AT-cut parallel-resonance type
C0
Figure 26.3 Crystal Resonator Equivalent Circuit Table 26.3 Crystal Resonator Characteristics
Frequency (MHz) RS Max. () C0 Max. (pF) 8 80 12 60 16 50 7 18 40
26.2.2
External Clock Input
An external clock signal can be input as the examples in Figure 26.4. When the XTAL pin is left open, make the parasitic capacitance less than 10 pF. When the counter clock is input to the XTAL pin, put the external clock in high level during standby mode.
EXTAL XTAL Open
External clock input
(a) XTAL pin left open
EXTAL XTAL
External clock input
(b) Counter clock input on XTAL pin
Figure 26.4 External Clock Input (Examples)
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Section 26 Clock Pulse Generator
tEXH
tEXL
EXTAL
Vcc x 0.5
tEXr
tEXf
Figure 26.5 External Clock Input Timing
26.3
PLL Circuit
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a factor of 4. The frequency multiplication rate is fixed. The phase difference is controlled so that the timing of the rising edge of the internal clock is the same as that of the EXTAL pin signal.
26.4
Frequency Divider
The frequency divider divides the PLL clock to generate a 1/2, 1/4, or 1/8 clock. After the bits ICK2 to ICK0, PCK 2 to PCK0, and BCK2 to BCK0 are updated, this LSI operates with the updated frequency.
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Section 26 Clock Pulse Generator
26.5
26.5.1
Usage Notes
Notes on Clock Pulse Generator
1. The following points should be noted since the frequency of (I: system clock, P: peripheral module clock, B: external bus clock) supplied to each module changes according to the setting of SCKCR. Select a clock division ratio that is within the operation guaranteed range of clock cycle time tcyc shown in the AC timing of electrical characteristics. Since I min = 8MHz, P min = 8MHz, B min = 8MHz, I max = 50 MHz, P max = 35 MHz, and B max = 50 MHz, the frequencies should satisfy the conditions 8 MHz I 50 MHz, 8 MHz P 35 MHz, and 8 MHz B 50 MHz. 2. All the on-chip peripheral modules (except for the EXDMAC, DMAC, and DTC) operate on the P. Note therefore that the time processing of modules such as a timer and SCI differs before and after changing the clock division ratio. In addition, wait time for clearing software standby mode differs by changing the clock division ratio. For details, see section 27.7.3, Setting Oscillation Settling Time after Exit from Software Standby Mode. 3. The relationship among the system clock, peripheral module clock, and external bus clock is I P and I B. In addition, the system clock setting has the highest priority. Accordingly, P or B may have the frequency set by bits ICK2 to ICK0 regardless of the settings of bits PCK2 to PCK0 or BCK2 to BCK0. 4. Note that the frequency of will be changed in the middle of a bus cycle when setting SCKCR while executing the external bus cycle with the write-data-buffer function and EXDMAC. 5. Figure 26.6 shows the clock modification timing. After a value is written to SCKCR, this LSI waits for the current bus cycle to complete. After the current bus cycle completes, each clock frequency will be modified within one cycle (worst case) of the external input clock .
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Section 26 Clock Pulse Generator
One cycle (worst case) after the bus cycle completion External clock I
Bus master
CPU
CPU
CPU
Operating clock specified in SCKCR
Operating clock changed
Figure 26.6 Clock Modification Timing 26.5.2 Notes on Resonator
Since various characteristics related to the resonator are closely linked to the user's board design, thorough evaluation is necessary on the user's part, using the resonator connection examples shown in this section as a reference. As the parameters for the resonator will depend on the floating capacitance of the resonator and the mounting circuit, the parameters should be determined in consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the maximum rating is not applied to the resonator pin. 26.5.3 Notes on Board Design
When using the crystal resonator, place the crystal resonator and its load capacitors as close to the XTAL and EXTAL pins as possible. Other signal lines should be routed away from the oscillation circuit as shown in Figure 26.7 to prevent induction from interfering with correct oscillation.
Inhibited CL2 XTAL EXTAL CL1 Signal A Signal B This LSI
Figure 26.7 Note on Board Design for Oscillation Circuit
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Section 26 Clock Pulse Generator
Figure 26.8 shows the external circuitry recommended for the PLL circuit. Separate PLLVCC and PLLVSS from the other VCC and VSS lines at the board power supply source, and be sure to insert bypass capacitors CPB and CB close to the pins.
Rp: 100 PLLVCC CPB: 0.1 F* PLLVSS VCC CB: 0.1 F* VSS
Note: * CB and CPB are laminated ceramic capacitors.
Figure 26.8 Recommended External Circuitry for PLL Circuit
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Section 26 Clock Pulse Generator
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Section 27 Power-Down Modes
Section 27 Power-Down Modes
Functions for reduced power consumption by this LSI include a multi-clock function, module stop function, and a function for transition to power-down mode.
27.1
Features
* Multi-clock function The frequency division ratio is settable independently for the system clock, peripheral module clock, and external bus clock. * Module stop function The functions for each peripheral module can be stopped to make a transition to a power-down mode. * Transition function to power-down mode Transition to a power-down mode is possible to stop the CPU, peripheral modules, and oscillator. * Five power-down modes Sleep mode All-module-clock-stop mode Software standby mode Deep software standby mode Hardware standby mode Table 27.1 shows conditions to shift to a power-down mode, states of the CPU and peripheral modules, and clearing method for each mode. After the reset state, since this LSI operates in normal program execution state, the modules, other than the DMAC, DTC, and EXDMAC are stopped.
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Section 27 Power-Down Modes
Table 27.1 States of Operation
All-ModuleClock-Stop Mode Deep Software Standby Software Standby Mode Mode Hardware Standby Mode Pin input
State of Operation Transition condition Cancellation method Oscillator CPU On-chip RAMs 6 to 4 (H'FEE000 to H'FF3FFF) On-chip RAMs 3 to 0 (H'FF4000 to H'FFBFFF)
Sleep Mode
Control register Control register Control register Control + instruction + instruction + instruction register + instruction Interrupt Operating Stopped (retained) Operating (retained) Interrupt*2 Operating Stopped (retained) Stopped (retained) Interrupt*8 Stopped Stopped (retained) Stopped (retained) Interrupt*8 Stopped Stopped (undefined) Stopped (undefined)
Stopped Stopped (undefined) Stopped (undefined)
Operating (retained)
Stopped (retained)
Stopped (retained)
Stopped (retained/ 5 undefined)* Stopped (retained/ undefined)*5 Stopped (undefined) Stopped (undefined) Operating
Stopped (undefined)
Universal Serial Operating Bus interface Watchdog timer Operating 8-bit timer (unit 0/1) Voltage detection circuit*9 Operating Operating
Stopped (retained) Operating Operating*4 Operating
Stopped (retained) Stopped (retained) Stopped (retained) Operating
Stopped (undefined) Stopped (undefined) Stopped (undefined) Stopped
Power-on reset Operating circuit*9 Other peripheral modules I/O ports Operating
Operating Stopped*1
Operating Stopped*1
Operating Stopped*7 (undefined) Stopped*6 (undefined)
Stopped Stopped*3 (undefined) Hi-Z
Operating
Retained
Retained*6
Notes: "Stopped (retained)" in the table means that the internal values are retained and internal operations are suspended.
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Section 27 Power-Down Modes
"Stopped (undefined)" in the table means that the internal values are undefined and the power supply for internal operations is turned off. 1. SCI enters the reset state, and other peripheral modules retain their states. 2. External interrupt and some internal interrupts (8-bit timer, watchdog timer, and 32K timer). 3. All peripheral modules enter the reset state. 4. "Functioning" or "Stopped" is selectable through the setting of bits MSTPA9 and MSTPA8 in MSTPCRA. 5. "Retained" or "undefined" of the contents of RAM is selected by the setting of the bits RAMCUT2 to RAMCUT0 in DPSBYCR. 6. Retention or high-impedance for the address bus and bus-control signals (CS0 to CS7, AS, RD, HWR, and LWR) is selected by the setting of the OPE bit in SBYCR. 7. Some peripheral modules enter a state where the register values are retained. 8. An external interrupt or USB suspend/resume interrupt.
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Section 27 Power-Down Modes
STBY pin = Low STBY pin = High
Reset state Hardware standby mode
RES pin = Low
RES pin = High SSBY = 0 SLEEP instruction*4
Sleep mode
All interrupts
SSBY = 0, ACSE = 1 MSTPCR = H'F[C-F]FFFFFF
All-module-clockstop mode
SLEEP instruction*4 Interrupt*1
Program execution state
SLEEP instruction*4 (SSBY = 1)
Software standby mode (DPSBY = 1 and no external interrupt is generated*5) Deep software standby mode
External interrupt*2
(DPSBY = 0 and no external interrupt is generated)
External interrupt*3
Internal reset state
Program halted state
[Legend]
Transition after exception handling
Notes: 1. NMI, IRQ0 to IRQ11, 8-bit timer interrupt, watchdog timer interrupt, and voltage monitoring interrupt*6 Note that the 8-bit timer interrupt is valid when the MSTPCRA9 or MSTPCRA8 bit is cleared to 0. 2. NMI, IRQ0 to IRQ11, and voltage monitoring interrupt*6. Note that IRQ is valid only when the corresponding bit in SSIER is set to 1. 3. NMI, and IRQ0-A to IRQ3-A, and voltage monitoring interrupt*6. Note that IRQ and voltage monitoring*6 interrupts are valid only when the corresponding bit in DPSIER is set to 1. 4. The SLPIE bit in SBYCR is cleared to 0. 5. If a conflict between a transition to deep software standby mode and generation of software standby mode clearing source occurs, a mode transition may be made from software standby mode to program execution state through execution of interrupt exception handling. In this case, a transition to deep software standby mode is not made. For details, refer to section 27.12, Usage Notes. 6. Supported only by the H8SX/1658M Group. From any state, a transition to hardware standby mode occurs when STBY is driven low. From any state except hardware standby mode, a transition to the reset state occurs when RES is driven low.
Figure 27.1 Mode Transitions
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Section 27 Power-Down Modes
27.2
Register Descriptions
The registers related to the power-down modes are shown below. For details on the system clock control register (SCKCR), refer to section 26.1.1, System Clock Control Register (SCKCR). * * * * * * * * * * * Standby control register (SBYCR) Module stop control register A (MSTPCRA) Module stop control register B (MSTPCRB) Module stop control register C (MSTPCRC) Deep standby control register (DPSBYCR) Deep standby wait control register (DPSWCR) Deep standby interrupt enable register (DPSIER) Deep standby interrupt flag register (DPSIFR) Deep standby interrupt edge register (DPSIEGR) Reset status register (RSTSR) Deep standby backup register n (DPSBKRn) (n: 15 to 0) Standby Control Register (SBYCR)
27.2.1
SBYCR controls software standby mode.
Bit Bit name Initial value:
15 SSBY 0 R/W
7 SLPIE 0 R/W
14 OPE 1 R/W
6
13
12 STS4 0 R/W
4
11 STS3 1 R/W
3
10 STS2 1 R/W
2
9 STS1 1 R/W
1
8 STS0 1 R/W
0
0 R/W
5
R/W:
Bit Bit name Initial value:
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
R/W:
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Section 27 Power-Down Modes
Bit 15
Bit Name SSBY
Initial Value 0
R/W R/W
Description Software Standby Specifies the transition mode after executing the SLEEP instruction 0: Shifts to sleep mode after the SLEEP instruction is executed 1: Shifts to software standby mode after the SLEEP instruction is executed This bit does not change when clearing the software standby mode by using interrupts and shifting to normal operation. For clearing, write 0 to this bit. When the WDT is used in watchdog timer mode, the setting of this bit is disabled. In this case, a transition is always made to sleep mode or all-module-clock-stop mode after the SLEEP instruction is executed. When the SLPIE bit is set to 1, this bit should be cleared to 0. Output Port Enable Specifies whether the output of the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, and LWR) is retained or these lines are set to the high-Z state in software standby mode or deep software standby mode. 0: In software standby mode or deep software standby mode, address bus and bus control signal lines are high-impedance. 1: In software standby mode or deep software standby mode, output states of address bus and bus control signals are retained. Reserved This bit is always read as 0. The write value should always be 0.
14
OPE
1
R/W
13
0
R/W
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Section 27 Power-Down Modes
Bit 12 11 10 9 8
Bit Name STS4 STS3 STS2 STS1 STS0
Initial Value 0 1 1 1 1
R/W R/W R/W R/W R/W R/W
Description Standby Timer Select 4 to 0 These bits select the time the MCU waits for the clock to settle when software standby mode is cleared by an interrupt. With a crystal resonator, refer to table 27.2 and make a selection according to the operating frequency so that the standby time is at least equal to the oscillation settling time. With an external clock, a PLL circuit settling time is necessary. Refer to table 27.2 to set the standby time. While oscillation is being settled, the timer is counted on the P clock frequency. Careful consideration is required in multi-clock mode. 00000: Reserved 00001: Reserved 00010: Reserved 00011: Reserved 00100: Reserved 00101: Standby time = 64 states 00110: Standby time = 512 states 00111: Standby time = 1024 states 01000: Standby time = 2048 states 01001: Standby time = 4096 states 01010: Standby time = 16384 states 01011: Standby time = 32768 states 01100: Standby time = 65536 states 01101: Standby time = 131072 states 01110: Standby time = 262144 states 01111: Standby time = 524288 states 1xxxx: Reserved
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Section 27 Power-Down Modes
Bit 7
Bit Name SLPIE
Initial Value 0
R/W R/W
Description Sleep Instruction Exception Handling Enable Selects whether a sleep interrupt is generated or a transition to power-down mode is made when a SLEEP instruction is executed. 0: A transition to power-down mode is made when a SLEEP instruction is executed. 1: A sleep instruction exception handling is generated when a SLEEP instruction is executed. Even after a sleep instruction exception handling is executed, this bit remains set to 1. For clearing, write 0 to this bit.
6 to 0
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
[Legend] x: Don't care Note: With the F-ZTAT version, the flash memory settling time must be reserved.
27.2.2
Module Stop Control Registers A and B (MSTPCRA and MSTPCRB)
MSTPCRA and MSTPCRB control module stop state. Setting a bit to 1 makes the corresponding module enter module stop state, while clearing the bit to 0 clears module stop state. * MSTPCRA
Bit Bit name Initial value:
15 ACSE 0 R/W
7 MSTPA7 1 R/W
14 MSTPA14 0 R/W
6 MSTPA6 1 R/W
13 MSTPA13 0 R/W
5 MSTPA5 1 R/W
12 MSTPA12 0 R/W
4 MSTPA4 1 R/W
11 MSTPA11 1 R/W
3 MSTPA3 1 R/W
10 MSTPA10 1 R/W
2 MSTPA2 1 R/W
9 MSTPA9 1 R/W
1 MSTPA1 1 R/W
8 MSTPA8 1 R/W
0 MSTPA0 1 R/W
R/W:
Bit Bit name Initial value:
R/W:
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Section 27 Power-Down Modes
* MSTPCRB
Bit Bit name Initial value:
15 MSTPB15 1 R/W
7 MSTPB7 1 R/W
14 MSTPB14 1 R/W
6 MSTPB6 1 R/W
13 MSTPB13 1 R/W
5 MSTPB5 1 R/W
12 MSTPB12 1 R/W
4 MSTPB4 1 R/W
11 MSTPB11 1 R/W
3 MSTPB3 1 R/W
10 MSTPB10 1 R/W
2 MSTPB2 1 R/W
9 MSTPB9 1 R/W
1 MSTPB1 1 R/W
8 MSTPB8 1 R/W
0 MSTPB0 1 R/W
R/W:
Bit Bit name Initial value:
R/W:
* MSTPCRA
Bit 15 Bit Name ACSE Initial Value 0 R/W R/W Module All-Module-Clock-Stop Mode Enable Enables/disables all-module-clock-stop state for reducing current consumption by stopping the bus controller and I/O ports operations when the CPU executes the SLEEP instruction after module stop state has been set for all the on-chip peripheral modules controlled by MSTPCR. 0: All-module-clock-stop mode disabled 1: All-module-clock-stop mode enabled 14 13 12 11 10 9 8 7 6 5 MSTPA14 0 MSTPA13 0 MSTPA12 0 MSTPA11 1 MSTPA10 1 MSTPA9 MSTPA8 MSTPA7 MSTPA6 MSTPA5 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W EXDMA controller (EXDMAC) DMA controller (DMAC) Data transfer controller (DTC) Reserved These bits are always read as 1. The write value should always be 1. 8-bit timer (TMR_3 and TMR_2) 8-bit timer (TMR_1 and TMR_0) Reserved These bits are always read as 1. The write value should always be 1. D/A converter (channels 1 and 0)
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Section 27 Power-Down Modes
Bit 4
Bit Name MSTPA4
Initial Value 1
R/W R/W
Module Reserved This bit is always read as 1. The write value should always be 1.
3 2
MSTPA3 MSTPA2
1 1
R/W R/W
A/D converter (unit 0) Reserved This bit is always read as 1. The write value should always be 1.
1 0
MSTPA1 MSTPA0
1 1
R/W R/W
16-bit timer pulse unit (TPU channels 11 to 6) 16-bit timer pulse unit (TPU channels 5 to 0)
* MSTPCRB
Bit 15 14 13 12 11 Bit Name Initial Value R/W R/W R/W R/W R/W R/W Module Programmable pulse generator (PPG_0: PO7 to PO0) Reserved These bits are always read as 1. The write value should always be 1. Serial communications interface_4 (SCI_4) Reserved This bit is always read as 1. The write value should always be 1. 10 9 8 7 6 5 4 3 2 1 0 MSTPB10 1 MSTPB9 MSTPB8 MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0 1 1 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Serial communications interface_2 (SCI_2) Serial communications interface_1 (SCI_1) Serial communications interface_0 (SCI_0) I2C bus interface 2_1 (IIC2_1) I2C bus interface 2_0 (IIC2_0) User break controller (UBC) Reserved These bits are always read as 1. The write value should always be 1.
MSTPB15 1 MSTPB14 1 MSTPB13 1 MSTPB12 1 MSTPB11 1
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Section 27 Power-Down Modes
27.2.3
Module Stop Control Register C (MSTPCRC)
When bits MSTPC7 to MSTPC0 are set to 1, the corresponding on-chip RAM stops. Do not set the corresponding MSTPC7 to MSTPC0 bits to 1 while accessing the on-chip RAM. Do not access the on-chip RAM while bits MSTPC7 to MSTPC0 are set to 1. The serial communications interfaces, 8-bit timers, Universal Serial Bus interface (USB), CRC calculator, 10-bit A/D converter, and programmable pulse generator (PPG: PO31 to PO16) are placed in the module stop state by using the MSTPC15 and MSTPC14, MSTPC13 and MSTPC12, MSTPC11, MSTPC10, MSTPC9, and MSTPC8 bits, respectively.
Bit Bit name Initial value:
15 MSTPC15 1 R/W
7 MSTPC7 0 R/W
14 MSTPC14 1 R/W
6 MSTPC6 0 R/W
13 MSTPC13 1 R/W
5 MSTPC5 0 R/W
12 MSTPC12 1 R/W
4 MSTPC4 0 R/W
11 MSTPC11 1 R/W
3 MSTPC3 0 R/W
10 MSTPC10 1 R/W
2 MSTPC2 0 R/W
9 MSTPC9 1 R/W
1 MSTPC1 0 R/W
8 MSTPC8 1 R/W
0 MSTPC0 0 R/W
R/W:
Bit Bit name Initial value:
R/W:
Bit 15 14 13 12 11 10 9 8
Bit Name MSTPC15 MSTPC14 MSTPC13 MSTPC12 MSTPC11 MSTPC10 MSTPC9 MSTPC8
Initial Value 1 1 1 1 1 1 1 1
R/W R/W R/W R/W R/W R/W R/W R/W R/W
Module Serial communications interface_5 (SCI_5), (IrDA) Serial communications interface_6 (SCI_6) 8-bit timer (TMR_4, TMR_5) 8-bit timer (TMR_6, TMR_7) Universal Serial Bus interface (USB) Cyclic redundancy check calculator A/D converter (unit 1) Programmable pulse generator (PPG_1: PO31 to PO16)
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Section 27 Power-Down Modes
Bit 7 6
Bit Name MSTPC7 MSTPC6
Initial Value 0 0
R/W R/W R/W
Module With 56 Kbytes of on-chip RAM: On-chip RAM 6 (H'FEE000 to H'FEFFFF) With 40 Kbytes of on-chip RAM: Reserved Always set the MSTPC7 and MSTPC6 bits to the same value.
5 4
MSTPC5 MSTPC4
0 0
R/W R/W
With 56 Kbytes of on-chip RAM: On-chip RAM 5, 4 (H'FF0000 to H'FF3FFF) With 40 Kbytes of on-chip RAM: On-chip RAM 4 (H'FF2000 to H'FF3FFF) Always set the MSTPC5 and MSTPC4 bits to the same value.
3 2 1 0
MSTPC3 MSTPC2 MSTPC1 MSTPC0
0 0 0 0
R/W R/W R/W R/W
On-chip RAM_3, 2 (H'FF4000 to H'FF7FFF) Always set the MSTPC3 and MSTPC2 bits to the same value. On-chip RAM_1, 0 (H'FF8000 to H'FFBFFF) Always set the MSTPC1 and MSTPC0 bits to the same value.
27.2.4
Deep Standby Control Register (DPSBYCR)
DPSBYCR controls deep software standby mode. DPSBYCR is not initialized by the internal reset signal upon exit from deep software standby mode.
Bit Bit name Initial value:
7 DPSBY 0 R/W
6 IOKEEP 0 R/W
5 RAMCUT2 0 R/W
4 RAMCUT1 0 R/W
3
2
1
0 RAMCUT0 1 R/W
0 R/W
0 R/W
0 R/W
R/W:
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Section 27 Power-Down Modes
Bit 7
Bit Name DPSBY
Initial Value 0
R/W R/W
Module Deep Software Standby When the SSBY bit in SBYCR has been set to 1, executing the SLEEP instruction causes a transition to software standby mode. At this time, if there is no source to clear software standby mode and this bit is set to 1, a transition to deep software standby mode is made.
SSBY DPSBY Entry to
0 1
x 0
Enters sleep mode after execution of a SLEEP instruction. Enters software standby mode after execution of a SLEEP instruction. Enters deep software standby mode after execution of a SLEEP instruction.
1
1
When deep software standby mode is canceled due to an interrupt, this bit remains at 1. Write a 0 here to clear it. Setting of this bit has no effect when the WDT is used in watchdog timer mode. In this case, executing the SLEEP instruction always initiates entry to sleep mode or allmodule-clock-stop mode. Be sure to clear this bit to 0 when setting the SLPIE bit to 1.
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Section 27 Power-Down Modes
Bit 6
Bit Name IOKEEP
Initial Value 0
R/W R/W
Module I/O Port Retention In deep software standby mode, the ports retain the states that were held in software standby mode. This bit specifies whether or not the state that has been held in deep software standby mode is retained after exit from deep software standby mode.
IOKEEP Pin State
0
The retained port states are released simultaneously with exit from deep software standby mode. The retained port states are released when a 0 is written to this bit following exit from deep software standby mode.
1
In operation in external extended mode, however, the address bus, bus control signals (CS0, AS, RD, HWR, and LWR), and data bus are set to the initial state upon exit from deep software standby mode. 5 RAMCUT2 0 R/W On-chip RAM Power Off 2 RAMCUT 2, 1, and 0 control the internal power supply to the on-chip RAM and USB in deep software standby mode. For details, see descriptions of the RAMCUT0 bit. 4 RAMCUT1 0 R/W On-chip RAM Power Off 1 RAMCUT 2, 1, and 0 control the internal power supply to the on-chip RAM and USB in deep software standby mode. For details, see descriptions of the RAMCUT0 bit. 3 to 1 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 0 RAMCUT0 1 R/W On-chip RAM Power Off 0 RAMCUT 2, 1, and 0 control the internal power supply to the on-chip RAM and USB in deep software standby mode. RAMCUT 2 to 0 000: Power is supplied to the on-chip RAM and USB. 111: Power is not supplied to the on-chip RAM and USB. Settings other than above are prohibited.
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Section 27 Power-Down Modes
27.2.5
Deep Standby Wait Control Register (DPSWCR)
DPSWCR selects the time for which the MCU waits until the clock settles when deep software standby mode is canceled by an interrupt. DPSWCR is not initialized by the internal reset signal upon exit from deep software standby mode.
Bit Bit name Initial value:
7
6
5 WTSTS5 0 R/W
4 WTSTS4 0 R/W
3 WTSTS3 0 R/W
2 WTSTS2 0 R/W
1 WTSTS1 0 R/W
0 WTSTS0 0 R/W
0 R/W
0 R/W
R/W:
Bit 7, 6
Bit Name
Initial Value All 0
R/W R/W
Module Reserved These bits are always read as 0. The write value should always be 0.
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Section 27 Power-Down Modes
Bit 5 to 0
Bit Name WTSTS [5:0]
Initial Value 0
R/W R/W
Module Deep Software Standby Wait Time Setting These bits select the time for which the MCU waits until the clock settles when deep software standby mode is canceled by an interrupt. When using a crystal resonator, see table 27.3 and select the wait time greater than the oscillation settling time for each operating frequency. When using an external clock, settling time for the PLL circuit should be considered. See table 27.3 to select the wait time. During the oscillation settling period, counting is performed with the clock frequency input to the EXTAL. 000000: Reserved 000001: Reserved 000010: Reserved 000011: Reserved 000100: Reserved 000101: Wait time = 64 states 000110: Wait time = 512 states 000111: Wait time = 1024 states 001000: Wait time = 2048 states 001001: Wait time = 4096 states 001010: Wait time = 16384 states 001011: Wait time = 32768 states 001100: Wait time = 65536 states 001101: Wait time = 131072 states 001110: Wait time = 262144 states 001111: Wait time = 524288 states 01xxxx: Reserved
[Legend] x: Don't care
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Section 27 Power-Down Modes
27.2.6
Deep Standby Interrupt Enable Register (DPSIER)
DPSIER enables or disables interrupts to clear deep software standby mode. DPSIER is not initialized by the internal reset signal upon exit from deep software standby mode.
Bit Bit name Initial value:
7
6 DUSBIE 0 R/W
5
4 DLVDIE* 0 R/W
3 DIRQ3E 0 R/W
2 DIRQ2E 0 R/W
1 DIRQ1E 0 R/W
0 DIRQ0E 0 R/W
0 R/W
0 R/W
R/W:
Note: * Supported only by the H8SX/1658M Group.
Bit 7
Bit Name
Initial Value 0
R/W R/W
Module Reserved This bit is always read as 0. The write value should always be 0.
6
DUSBIE
0
R/W
USB Suspend/Resume Interrupt Enable Enables/disables exit from deep software standby mode by the USB suspend/resume interrupt signal. 0: Disables exit from deep software standby mode by the USB suspend/resume interrupt signal. 1: Enables exit from deep software standby mode by the USB suspend/resume interrupt signal.
5
0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
4
DLVDIE*
0
R/W
LVD Interrupt Enable Enables/disables exit from deep software standby mode by the voltage monitoring interrupt signal. 0: Disables exit from deep software standby mode by the voltage monitoring interrupt signal. 1: Enables exit from deep software standby mode by the voltage monitoring interrupt signal.
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Section 27 Power-Down Modes
Bit 3
Bit Name DIRQ3E
Initial Value 0
R/W R/W
Module IRQ3 Interrupt Enable Enables or disables exit from deep software standby mode by IRQ3-A. 0: Disables exit from deep software standby mode by IRQ3-A. 1: Enables exit from deep software standby mode by IRQ3-A.
2
DIRQ2E
0
R/W
IRQ2 Interrupt Enable Enables or disables exit from deep software standby mode by IRQ2-A. 0: Disables exit from deep software standby mode by IRQ2-A 1: Enables exit from deep software standby mode by IRQ2-A
1
DIRQ1E
0
R/W
IRQ1 Interrupt Enable Enables or disables exit from deep software standby mode by IRQ1-A. 0: Disables exit from deep software standby mode by IRQ1-A. 1: Enables exit from deep software standby mode by IRQ1-A.
0
DIRQ0E
0
R/W
IRQ0 Interrupt Enable Enables or disables exit from deep software standby mode by IRQ0-A. 0: Disables exit from deep software standby mode by IRQ0-A. 1: Enables exit from deep software standby mode by IRQ0-A.
Note:
*
Supported only by the H8SX/1658M Group.
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Section 27 Power-Down Modes
27.2.7
Deep Standby Interrupt Flag Register (DPSIFR)
DPSIFR is used to request an exit from deep software standby mode. When the interrupt specified in DPSIEGR is generated, the applicable bit in DPSIFR is set to 1. The bit is set to 1 even when an interrupt is generated in the modes other than deep software standby. Therefore, a transition to deep software standby should be made after this register bits are cleared to 0. DPSIFR is not initialized by the internal reset signal upon exit from deep software standby mode.
Bit Bit name Initial value:
7 DNMIF 0 R/(W)*1
6 DUSBIF 0 R/(W)*1
5
4 DLVDIF*2 0 R/(W)*1
3 DIRQ3F 0 R/(W)*1
2 DIRQ2F 0 R/(W)*1
1 DIRQ1F 0 R/(W)*1
0 DIRQ0F 0 R/(W)*1
0 R
R/W:
Notes: 1. Only 0 can be written to clear the flag. 2. Supported only by the H8SX/1658M Group.
Bit 7
Bit Name DNMIF
Initial Value 0
R/W R/(W)*
1
Module NMI Flag [Setting condition] NMI input specified in DPSIEGR is generated. [Clearing condition] Writing a 0 to this bit after reading it as 1.
6
DUSBIF
0
R/(W)*
1
USB Suspend/Resume Interrupt Flag [Setting condition] When the USB suspend/resume interrupt occurs. [Clearing condition] Writing a 0 to this bit after reading it as 1.
5
0
R
Reserved These bits are always read as 0. The write value should always be 0.
4
DLVDIF*2
0
R/(W)*1
LVD Interrupt Flag [Setting condition] Voltage monitoring interrupt is generated. [Clearing condition] Writing a 0 to this bit after reading it as 1.
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Section 27 Power-Down Modes
Bit 3
Bit Name DIRQ3F
Initial Value 0
R/W R/(W)*
1
Module IRQ3 Interrupt Flag [Setting condition] IRQ3-A input specified in DPSIEGR is generated. [Clearing condition] Writing a 0 to this bit after reading it as 1.
2
DIRQ2F
0
R/(W)*1
IRQ2 Interrupt Flag [Setting condition] IRQ2-A input specified in DPSIEGR is generated. [Clearing condition] Writing a 0 to this bit after reading it as 1.
1
DIRQ1F
0
R/(W)*
1
IRQ1 Interrupt Flag [Setting condition] IRQ1-A input specified in DPSIEGR is generated. [Clearing condition] Writing a 0 to this bit after reading it as 1.
0
DIRQ0F
0
R/(W)*
1
IRQ0 Interrupt Flag [Setting condition] IRQ0-A input specified in DPSIEGR is generated. [Clearing condition] Writing a 0 to this bit after reading it as 1.
Notes: 1. Only 0 can be written to clear the flag. 2. Supported only by the H8SX/1658M Group.
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Section 27 Power-Down Modes
27.2.8
Deep Standby Interrupt Edge Register (DPSIEGR)
DPSIEGR selects the rising or falling edge to clear deep software standby mode. DPSIEGR is not initialized by the internal reset signal upon exit from deep software standby mode.
Bit Bit name Initial value:
7 DNMIEG 0 R/W
6
5
4
3 DIRQ3EG 0 R/W
2 DIRQ2EG 0 R/W
1 DIRQ1EG 0 R/W
0 DIRQ0EG 0 R/W
0 R/W
0 R/W
0 R/W
R/W:
Bit 7
Bit Name DNMIEG
Initial Value 0
R/W R/W
Module NMI Edge Select Selects the active edge for NMI pin input. 0: The interrupt request is generated by a falling edge. 1: The interrupt request is generated by a rising edge.
6 to 4
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
3
DIRQ3EG
0
R/W
IRQ3 Interrupt Edge Select Selects the active edge for IRQ3-A pin input. 0: The interrupt request is generated by a falling edge. 1: The interrupt request is generated by a rising edge.
2
DIRQ2EG
0
R/W
IRQ2-A Interrupt Edge Select Selects the active edge for IRQ2 pin input. 0: The interrupt request is generated by a falling edge. 1: The interrupt request is generated by a rising edge.
1
DIRQ1EG
0
R/W
IRQ1-A Interrupt Edge Select Selects the active edge for IRQ1 pin input. 0: The interrupt request is generated by a falling edge. 1: The interrupt request is generated by a rising edge.
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Section 27 Power-Down Modes
Bit 0
Bit Name DIRQ0EG
Initial Value 0
R/W R/W
Module IRQ0 Interrupt Edge Select Selects the active edge for IRQ0-A pin input. 0: The interrupt request is generated by a falling edge. 1: The interrupt request is generated by a rising edge.
27.2.9
Reset Status Register (RSTSR)
The DPSRSTF bit in RSTSR indicates that deep software standby mode has been canceled by an interrupt. RSTSR is not initialized by the internal reset signal upon exit from deep software standby mode.
Bit Bit name Initial value:
7 DPSRSTF 0 R/(W)*1
6
5
4
3
2 LVDF*2 0*3 R/W*4
1
0
PORF*2
0 R/W
0 R/W
0 R/W
0 R/W
0*3 R/W
0*3 R/W*5
R/W:
Notes: 1. 2. 3. 4. 5.
Only 0 can be written to clear the flag. Supported only by the H8SX/1658M Group. Initial value is undefined in the H8SX/1658M Group. Only 0 can be written to clear the flag in the H8SX/1658M Group. Readable only in the H8SX/1658 M Group.
Bit 7
Bit Name
Initial Value
R/W R/(W)*
1
Module Deep Software Standby Reset Flag Indicates that deep software standby mode has been canceled by an interrupt source specified in DPSIER or DPSIEGR and an internal reset is generated. [Setting condition] Deep software standby mode is canceled by an interrupt source. [Clearing condition] Writing a 0 to this bit after reading it as 1.
DPSRSTF 0
6 to 3
All 0
R/W
Reserved These bits are always read as 0. The write value should always be 0.
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Section 27 Power-Down Modes
* H8SX1658R Group
2 to 0 All 0 R/W Reserved These bits are always read as 0. The write value should always be 0.
* H8SX1658M Group
2 LVDF Undefined R/(W)* LVD Flag This bit indicates that the voltage-detection circuit has detected a low voltage (Vcc at or below Vdet). For details, see section 5, Voltage Detection Circuit (LVD). 1 Undefined R/W Reserved These bits are always read as 0. The write value should always be 0. 0 PORF Undefined R Power-on Reset Flag This bit indicates that a power-on reset has been generated. For details, see section 4, Reset. Note: * Only 0 can be written to clear the flag.
27.2.10 Deep Standby Backup Register (DPSBKRn) DPSBKRn (n = 15 to 0) is a 16-bit readable/writable register to store data during deep software standby mode. Although data in on-chip RAM is not retained in deep software standby mode, data in this register is retained. DPSBKRn (n = 15 to 0) is not initialized by the internal reset signal upon exit from deep software standby mode.
Bit Bit name Initial value:
7 BKUPn7 0 R/W
6 BKUPn6 0 R/W
5 BKUPn5 0 R/W
4 BKUPn4 0 R/W
3 BKUPn3 0 R/W
2 BKUPn2 0 R/W
1 BKUPn1 0 R/W
0 BKUPn0 0 R/W
R/W:
n: 15 to 0
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Section 27 Power-Down Modes
27.3
Multi-Clock Function
When bits ICK2 to ICK0, PCK2 to PCK0, and BCK2 to BCK0 in SCKCR are set, the clock frequency is changed at the end of the bus cycle. The CPU and bus masters operate on the operating clock specified by bits ICK2 to ICK0. The peripheral modules operate on the operating clock specified by bits PCK2 to PCK0. The external bus operates on the operating clock specified by bits BCK2 to BCK0. Even if the frequencies specified by bits PCK2 to PCK0 and BCK2 to BCK0 are higher than the frequency specified by bits ICK2 to ICK0, the specified values are not reflected in the peripheral module and external bus clocks. The peripheral module and external bus clocks are restricted to the operating clock specified by bits ICK2 to ICK0.
27.4
Module Stop State
Module stop functionality can be set for individual on-chip peripheral modules. When the corresponding MSTP bit in MSTPCRA, MSTPCRB, or MSTPCRC is set to 1, module operation stops at the end of the bus cycle and a transition is made to a module stop state. The CPU continues operating independently. When the corresponding MSTP bit is cleared to 0, a module stop state is cleared and the module starts operating at the end of the bus cycle. In a module stop state, the internal states of modules other than the SCI are retained. After the reset state is cleared, all modules other than the EXDMAC, DMAC, and DTC and onchip RAM are placed in a module stop state. The registers of the module for which the module stop state is selected cannot be read from or written to.
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Section 27 Power-Down Modes
27.5
27.5.1
Sleep Mode
Entry to Sleep Mode
When the SLEEP instruction is executed when the SSBY bit in SBYCR is 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other peripheral functions do not stop. 27.5.2 Exit from Sleep Mode
Sleep mode is exited by any interrupt, signals on the RES or STBY pin, and a reset caused by a watchdog timer overflow, a voltage monitoring reset*, or a power-on reset*. * Exit from sleep mode by interrupt When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the CPU. * Exit from sleep mode by RES pin Setting the RES pin level low selects the reset state. After the stipulated reset input duration, driving the RES pin high makes the CPU start the reset exception processing. * Exit from sleep mode by STBY pin When the STBY pin level is driven low, a transition is made to hardware standby mode. * Exit from sleep mode by reset caused by watchdog timer overflow Sleep mode is exited by an internal reset caused by a watchdog timer overflow. * Exit from voltage monitoring reset* Sleep mode is exited by a voltage monitoring reset of the voltage detection circuit. * Exit from power-on reset* Sleep mode is exited by a power-on reset. Note: * Supported only by the H8SX/1658M Group.
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Section 27 Power-Down Modes
27.6
All-Module-Clock-Stop Mode
When the ACSE bit is set to 1 and all modules controlled by MSTPCRA and MSTPCRB are stopped (MSTPCRA, MSTPCRB = H'FFFFFFFF), or all modules except for the 8-bit timer (units 0 and 1) are stopped (MSTPCRA, MSTPCRB = H'F[C to F]FFFFFF), executing a SLEEP instruction with the SSBY bit in SBYCR cleared to 0 will cause all modules (except for the 8-bit timer*1, watchdog timer, power-on reset circuit*2, and voltage detection circuit*2) the bus controller, and the I/O ports to stop operating, and to make a transition to all-module-clock-stop mode at the end of the bus cycle. When power consumption should be reduced ever more in all-module-clock-stop mode, stop modules controlled by MSTPCRC (MSTPCRC[15:8] = H'FFFF). All-module-clock-stop mode is cleared by an external interrupt (NMI or IRQ0 to IRQ11 pins), RES pin input, or an internal interrupt (8-bit timer*1, watchdog timer, and voltage detection circuit*2), and the CPU returns to the normal program execution state via the exception handling state. All-module-clock-stop mode is not cleared if interrupts are disabled, if interrupts other than NMI are masked on the CPU side, or if the relevant interrupt is designated as a DTC activation source. When the STBY pin is driven low, a transition is made to hardware standby mode. Notes: 1. Operation or stopping of the 8-bit timer can be selected by bits MSTPA9 and MSTPA8 in MSTPCRA. 2. Supported only by the H8SX/1658M Group.
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Section 27 Power-Down Modes
27.7
27.7.1
Software Standby Mode
Entry to Software Standby Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1 and the DPSBY bit in DPSBYCR is cleared to 0, software standby mode is entered. In this mode, the CPU, on-chip peripheral functions, and oscillator all stop. However, the contents of the CPU's internal registers, on-chip RAM data, and the states of on-chip peripheral functions other than the SCI, and the states of the I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, allowing power consumption to be significantly reduced. If the WDT is used in watchdog timer mode, it is impossible to make a transition to software standby mode. The WDT should be stopped before the SLEEP instruction execution. 27.7.2 Exit from Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI or IRQ0 to IRQ11*1) or an internal interrupt (voltage monitoring interrupt *2 or USB suspend/resume), a voltage monitoring reset*2, a power-on reset*2 or by means of the RES pin or STBY pin. 1. Exit from software standby mode by interrupt When an NMI, IRQ0 to IRQ11*1, or USB suspend/resume interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS4 to STS0 in SBYCR, stable clocks are supplied to the entire LSI, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ11*1 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ11*1 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. 2. Exit from voltage monitoring reset*2 When a voltage monitoring reset is generated by the fall of power-voltage, software standby mode is cleared and a clock oscillation starts. At the same time, a clock signal is supplied throughout the LSI. After that, if power voltage rises, the voltage detection reset is released. Thereafter, CPU starts the reset exception handling. 3. Exit from power-on reset*3 When a power-on reset is generated by the fall of power voltage, software standby mode is released. After that, if power voltage rises, the clock oscillation starts and the power-on reset is
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Section 27 Power-Down Modes
released while the clock oscillation stabilization time is well kept. Thereafter CPU starts the reset exception handling. 4. Exit from software standby mode by RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low until clock oscillation settles. When the RES pin goes high, the CPU begins reset exception handling. 5. Exit from software standby mode by STBY pin When the STBY pin is driven low, a transition is made to hardware standby mode. Notes: 1. By setting the SSIn bit in SSIER to 1, IRQ0 to IRQ11 can be used as a software standby mode clearing source. 2. Supported only by the H8SX/1658M Group. 27.7.3 Setting Oscillation Settling Time after Exit from Software Standby Mode
Bits STS4 to STS0 in SBYCR should be set as described below. 1. Using a crystal resonator Set bits STS4 to STS0 so that the standby time is at least equal to the oscillation settling time. Table 27.2 shows the standby times for operating frequencies and settings of bits STS4 to STS0. 2. Using an external clock A PLL circuit settling time is necessary. Refer to table 27.2 to set the standby time.
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Section 27 Power-Down Modes
Table 27.2 Oscillation Settling Time Setting
Standby 35 STS4 STS3 STS2 STS1 STS0 Time
0 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 Reserved Reserved Reserved Reserved Reserved 64 512 1024 2048 4096 16384 32768 65536 131072 262144 524288 Reserved 1.8 14.6 29.3 58.5 0.12 0.47 0.94 1.87 3.74 7.49 14.98
P* (MHz) 25
2.6 20.5 41.0 81.9 0.16 0.66 1.31 2.62 5.24 10.49 20.97
20
3.2 25.6 51.2 102.4 0.20 0.82 1.64 3.28 6.55 13.11 26.21
13
4.9 39.4 78.8 157.5 0.32 1.26 2.52 5.04 10.08 20.16 40.33
10
6.4 51.2 102.4 204.8 0.41 1.64 3.28 6.55 13.11 26.21 52.43
8
8.0 64.0 128.0 256.0 0.51 2.05 4.10 8.19 16.38 32.77 65.54
Unit
s
ms
[Legend] : Recommended setting when external clock is in use : Recommended setting when crystal oscillator is in use Note: * P is the output from the peripheral module frequency divider. The oscillation settling time, which includes a period where the oscillation by an oscillator is not stable, depends on the resonator characteristics. The above figures are for reference.
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Section 27 Power-Down Modes
27.7.4
Software Standby Mode Application Example
Figure 27.2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin.
Oscillator
I
NMI
NMIEG
SSBY
NMI exception handling NMIEG = 1 SSBY = 1 SLEEP instruction
Software standby mode (power-down mode) Oscillation settling time tOSC2
NMI exception handling
Figure 27.2 Software Standby Mode Application Example
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Section 27 Power-Down Modes
27.8
27.8.1
Deep Software Standby Mode
Entry to Deep Software Standby Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR has been set to 1, a transition to software standby mode is made. In this state, if the CPSBY bit in DPSBYCR is set to 1, a transition to deep software standby mode is made. If a software standby mode clearing source (an NMI, IRQ0 to IRQ11, voltage-monitoring interrupt requests*, or USB suspend/resume) occurs when a transition to software standby mode is made, software standby mode will be cleared regardless of the DPSBY bit setting, and the interrupt exception handling starts after the oscillation settling time for software standby mode specified by the bits STS4 to STS0 in SBYCR has elapsed. When both of the SSBY bit in SBYCR and the CPSBY bit in DPSBYCR are set to 1 and no software standby mode clearing source occurs, a transition to deep software standby mode will be made immediately after software standby mode is entered. In deep software standby mode, the CPU, on-chip peripheral functions (except for the USB and 32K timer), on-chip RAMs 6 to 4, and oscillator functionality are all halted. In addition, the internal power supply to these modules stops, resulting in a significant reduction in power consumption. At this time, the contents of all the registers of the CPU, on-chip peripheral functions (except for the USB), and on-chip RAMs 6 to 4 become undefined. Contents of the on-chip RAMs 3 to 0 and USB registers can be retained when all the bits RAMCUT2 to RAMCUT0 in DPSBYCR have been cleared to 0. If these bits are set to all 1, the internal power supply to the on-chip RAMs 3 to 0 and USB stops and the power consumption is further reduced. At this time, the contents of the on-chip RAMs 3 to 0 and USB registers become undefined. The voltage detection circuit*, and power-on reset circuit* can operate in deep software standby mode. The I/O ports can be retained in the same state as in software standby mode. Note: * Supported only by the H8SX/1658M Group.
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Section 27 Power-Down Modes
27.8.2
Exit from Deep Software Standby Mode
Exit from deep software standby mode is initiated by signals on the external interrupt pins (NMI and IRQ0-A to IRQ3-A), internal interrupt signals (voltage-monitoring interrupt and USB suspend/resume), voltage-monitoring reset*, power-on reset*, RES pin, or STBY pin. 1. Exit from deep software standby mode by external interrupt pins or internal interrupt signals Deep software standby mode is canceled when any of the DNMIF, DIRQnF (n = 3 to 0), DLVDIF bit* and DUSBIF bits in DPSIFR is set to 1. The DNMIF or DIRQnF (n = 3 to 0) bit is set to 1 when a specified edge is generated on the NMI pin or IRQ0-A to IRQ3-A pins, that have been enabled by the DIRQnE (n = 3 to 0) bit in DPSIER. The rising or falling edge of the signals can be specified with DPSIEGR. The DLVDIF bit is set to 1 when a voltagemonitoring interrupt occurs. The DUSBIF bit is set to 1 when a USB suspend/resume interrupt occurs. When deep software standby mode clearing source is generated, internal power supply starts simultaneously with the start of clock oscillation, and internal reset signal is generated for the entire LSI. Once the time specified by the WTSTS5 to WTSTS0 bits in DPSWCR has elapsed, a stable clock signal is being supplied throughout the LSI and the internal reset is cleared. Deep software standby mode is canceled on clearing of the internal reset, and then the reset exception handling starts. When deep software standby mode is canceled by an external interrupt pin or internal interrupt signal, the DPSRSTF bit in RSTSR is set to 1. 2. Exit from deep software standby mode by a voltage-monitoring reset* When a voltage monitoring reset is generated by the power-supply voltage falling, the LSI is released from deep software standby mode and clock oscillation starts. At the same time, a clock signal is supplied throughout the LSI. When the power-supply voltage has risen sufficiently, the LSI is released from the voltage-detection reset state. The CPU then starts reset-exception handling. 3. Exit from power-on reset* When a power-on reset is generated by the power-supply voltage falling, the LSI is released from deep software standby mode. If the power-supply voltage then rises sufficiently, clock oscillation starts and the LSI is released from the power-on reset state after the clock oscillation stabilization time has been secured. As soon as the clock oscillation starts, the clock signal is provided to the LSI. After that, the CPU starts reset-exception handling. 4. Exit from deep software standby mode by the signal on the RES pin
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Section 27 Power-Down Modes
Clock oscillation and internal power supply start as soon as the signal on the RES pin is driven low. At the same time, clock signals are supplied to the LSI. In this case, the RES pin has to be held low until the clock oscillation has become stable. Once the signal on the RES pin is driven high, the CPU starts reset exception handling. 5. Exit from deep software standby mode by the signal on the STBY pin When the STBY pin is driven low, a transition is made to hardware standby mode. Note: * Supported only by the H8SX/1658M Group. 27.8.3 Pin State on Exit from Deep Software Standby Mode
In deep software standby mode, the ports retain the states that were held during software standby mode. The internal of the LSI is initialized by an internal reset caused by deep software standby mode, and the reset exception handling starts as soon as deep software standby mode is canceled. The following shows the port states at this time. (1) Pins for address bus, bus control and data bus
Pins for the address bus, bus control signals (CS0, AS, HWR, and LWR), and data bus operate depending on the CPU. (2) Pins other than address bus, bus control and data bus pins
Whether the ports are initialized or retain the states that were held during software standby mode can be selected by the IOKEEP bit. * When IOKEEP = 0 Ports are initialized by an internal reset caused by deep software standby mode. * When IOKEEP = 1 The port states that were held in deep software standby mode are retained regardless of the LSI internal state though the internal of the LSI is initialized by an internal reset caused by deep software standby mode. At this time, the port states that were held in software standby mode are retained even if settings of I/O ports or peripheral modules are set. Subsequently, the retained port states are released when the IOKEEP bit is cleared to 0 and operation is performed according to the internal settings. The IOKEEP bit is not initialized by an internal reset caused by canceling deep standby mode.
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Section 27 Power-Down Modes
27.8.4
B Operation after Exit from Deep Software Standby Mode
When the IOKEEP bit is 0, B output is undefined for a maximum of one cycle immediately after exit from deep software standby mode. At this time, the output state cannot be guaranteed. Even when the IOKEEP bit is set to 1, B output is undefined for a maximum of one cycle immediately after the IOKEEP bit is cleared to 0 after deep software standby mode was canceled, and the output state cannot be guaranteed. (See figure 27.3) However, clock can be normally output by canceling deep software standby mode with the IOKEEP bit set to 1 and then controlling the B output with the IOKEEP and PSTOP1 bits. Use the following procedure. 1. Change the value of the PSTOP1 bit from 0 to 1 to fix the B output at the high level (given that the B output was already fixed high). 2. Clear the IOKEEP bit to 0 to end retention of the B state. 3. Clear the PSTOP1 bit to 0 to enable B output. For the port state when the IOKEEP bit is set to 1, see section 27.8.3, Pin State on Exit from Deep Software Standby Mode.
Deep software standby mode Oscillator
NMI
Internal reset
I
(1) B output cannot be guaranteed.
When IOKEEP = 0
B
When IOKEEP = 1
Clock is undefined
IOKEEP cleared
PSTOP1 IOKEEP PSTOP1 set cleared cleared
(2) The procedure to guarantee B output is used.
B
(IOKEEP=1)
When IOKEEP = 1, the clock can be normally output by using the PSTOP1 bit.
Figure 27.3 B Operation after Exit from Deep Software Standby Mode
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Section 27 Power-Down Modes
27.8.5
Setting Oscillation Settling Time after Exit from Deep Software Standby Mode
The WTSTS5 to WTSTS0 bits in DPSWCR should be set as follows: 1. Using a crystal resonator Specify the WTSTS5 to WTSTS0 bits so that the standby time is at least equal to the oscillation settling time. Table 27.3 shows EXTAL input clock frequencies and the standby time according to WTSTS5 to WTSTS0 settings. 2. Using an external clock The PLL circuit settling time should be considered. See table 27.3 to set the standby time.
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Section 27 Power-Down Modes
Table 27.3 Oscillation Settling Time Settings
EXTAL Input Clock Frequency* (MHz) WT STS5 0 WT STS4 0 WT STS3 0 WT STS2 0 WT STS1 0 WT STS0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 0 Standby Time Reserved Reserved Reserved Reserved Reserved 64 512 1024 2048 4096 16384 32768 65536 131072 262144 524288 Reserved 18 3.6 28.4 56.9 113.8 0.23 0.91 1.82 3.64 7.28 14.56 29.13 16 4.0 32.0 64.0 128.0 0.26 1.02 2.05 4.10 8.19 16.38 32.77 14 4.6 36.6 73.1 146.3 0.29 1.17 2.34 4.68 9.36 18.72 37.45 12 5.3 42.7 85.3 170.7 0.34 1.37 2.73 5.46 10.92 21.85 43.69 10 6.4 51.2 102.4 204.8 0.41 1.64 3.28 6.55 13.11 26.21 52.43 8 8.0 64.0 128.0 256.0 0.51 2.05 4.10 8.19 16.38 32.77 65.54 ms Unit s
[Legend] : Recommended setting when external clock is in use : Recommended setting when crystal oscillator is in use Note: * The oscillation settling time, which includes a period where the oscillation by an oscillator is not stable, depends on the resonator characteristics. The above figures are for reference.
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Section 27 Power-Down Modes
27.8.6 (1)
Deep Software Standby Mode Application Example
Transition to and Exit from Deep Software Standby Mode
Figure 27.4 shows an example where the transition to deep software standby mode is initiated by a falling edge on the NMI pin and exit from deep software standby mode is initiated by a rising edge on the NMI pin. In this example, falling-edge sensing of NMI interrupts has been specified by clearing the NMIEG bit in INTCR to 0 (not shown). After an NMI interrupt has been sensed, rising-edge sensing is specified by setting the DNMIEG bit to 1, the SSBY and DPSBY bits are set to 1, and the transition to deep software standby mode is triggered by execution of a SLEEP instruction. After that, deep software standby mode is canceled at the rising edge on the NMI pin.
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Section 27 Power-Down Modes
Oscillator
I NMI
Set
Set DNMI interrupt
Becomes invalid by an internal reset
NMI interrupt
DNMIEG bit
Set
DPSBY bit
Set
Cleared
IOKEEP bit
I/O port
Set
Cleared
Operated
Retained
Operated
DPSRSTF flag
Cleared
Internal reset
Deep software NMI exception standby mode handling (power-down mode) DNMIEG = 1 SSBY = 1 DPSBY = 1 SLEEP instruction
Oscillation settling time
Reset exception handling
Figure 27.4 Deep Software Standby Mode Application Example (IOKEEP = 1)
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Section 27 Power-Down Modes
(2)
Deep Software Standby Mode in External Extended Mode (IOKEEP = 1)
Figure 27.5 shows an example of operations in deep standby mode when the IOKEEP and OPE bits are set to 1 in external extended mode. In this example, deep software standby mode is entered with the IOKEEP and OPE bits set to 1, and then exited at the rising edge of the NMI pin. In external expansion mode, while the IOKEEP bit is set to 1, retention of the states of pins for the address bus, bus-control signals (CS0, AS, RD, HWR, and LWR), data bus is released after the oscillation settling time has elapsed. For other pins, including the B output pin, retention is released when the IOKEEP bit is cleared to 0, and then they are set according to the I/O port or peripheral module settings.
Oscillator
I
NMI
Internal reset
Started from h'00000
Address
Operated
Retained
Operated
Bus control
Retained
Data
Operated
Retained
Operated
PSTOP1 PSTOP1 set cleared
B
Retained
IOKEEP cleared
I/O other than above
Operated
Retained
Operated
Oscillation settling time
Program execution state
Deep software standby mode SLEEP (power-down mode) instruction
Reset exception handling
Program execution state
Figure 27.5 Example of Deep Software Standby Mode Operation in External Extended Mode (IOKEEP = OPE = 1)
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Section 27 Power-Down Modes
(3)
Deep Software Standby Mode in External Extended Mode (IOKEEP = 0)
Figure 27.6 shows an example of operations in deep software standby mode with the IOKEEP bit is set to 1 and the OPE bit is cleared to 0 in external extended mode. When the IOKEEP bit is cleared to 0, retention of the states of pins including the address bus, bus-control signals (CS0, AS, RD, HWR, and LWR), data bus, and other pins including B output is released after the oscillation settling time has elapsed.
Oscillator
I
NMI
Internal reset
Started from h'00000
Address
Operated
Retained
Operated
Bus control
Retained
Data
Operated
Retained
Operated
B
Retained
I/O other than above
Operated
Retained
Oscillation settling time
Operated
Program execution state
Deep software standby mode (power-down mode) SLEEP instruction
Reset exception handling
Program execution state
Figure 27.6 Example of Deep Software Standby Mode Operation in External Extended Mode (IOKEEP = OPE = 0)
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Section 27 Power-Down Modes
27.8.7
Flowchart of Deep Software Standby Mode Operation
Figure 27.7 shows an example of flowchart of deep software standby mode operation. In this example, reading the DPSRSTF bit determines whether a reset was generated by the RES pin or exit from deep software standby mode, after the reset exception handling was performed. When a reset was caused by the RES pin, deep software standby mode is entered after required register settings. When a reset was caused by exit from deep software standby mode, the IOKEEP bit is cleared after the I/O ports setting. When the IOKEEP bit is cleared, the setting to avoid instability in B output is also set.
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Section 27 Power-Down Modes
Clear a reset by RES
Reset exception handling
Program start
RSTSR. DPSRSTF = 0 Yes
Set DPSWCR.WTSTS5-0
No
Set oscillation setting time
Read DPSIFR
Identify deep software standby mode clearing source (1)
Set SBYCR.SSBY to 1 DPSBYCR.DPSBY to 1 DPSBYCR.RAMCUT2-0
Select deep software standby mode
Set PnDDR,PnDR Set pin state after clearing IOKEEP to 0 Set SCKCR.PSTOP1 to 1
Set PnDDR,PnDR Set pin state in deep software standby mode and after exit from deep software standby mode
Set DPSBYCR.IOKEEP to 0
Releases pin states that were retained during deep software standby mode
Set SBYCR.OPE
Set SCKCR.PSTOP1 to 0
Start B output
Set DPSBYCR.IOKEEP to 1
Set DPSIEGR Set deep software standby mode clearing interrupt
Execute a program corresponding to the clearing source that was identified in (1)
Set DPSIER
Clear DPSIFR
Execute SLEEP instruction
Deep software standby mode An interrupt is generated by exit from deep software standby mode.
Figure 27.7 Flowchart of Deep Software Standby Mode Operation
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Section 27 Power-Down Modes
27.9
27.9.1
Hardware Standby Mode
Transition to Hardware Standby Mode
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power consumption. Data in the on-chip RAM is not retained because the internal power supply to the on-chip RAM stops. I/O ports are set to the high-impedance state. Do not change the states of mode pins (MD2 to MD0) while this LSI is in hardware standby mode. 27.9.2 Clearing Hardware Standby Mode
Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is entered and clock oscillation is started. Ensure that the RES pin is held low until clock oscillation settles (for details on the oscillation settling time, refer to table 27.2). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 27.9.3 Hardware Standby Mode Timing
Figure 27.8 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation settling time, then changing the RES pin from low to high.
Oscillator
RES
STBY
Oscillation settling time
Reset exception handling
Figure 27.8 Hardware Standby Mode Timing
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Section 27 Power-Down Modes
27.9.4
Timing Sequence at Power-On
Figure 27.9 shows the timing sequence at power-on. At power-on, the RES pin must be driven low with the STBY pin driven high for a given time in order to clear the reset state. To enter hardware standby mode immediately after power-on, drive the STBY pin low after exiting the reset state. For details on clearing hardware standby mode, see section 27.9.3, Hardware Standby Mode Timing. In a power-on reset*, power on while driving the STBY or RES pin to a high-level. Note: * Supported only by the H8SX/1658M Group.
1 Power supply
RES
2 Reset state
STBY
3 Hardware standby mode
Figure 27.9 Timing Sequence at Power-On
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Section 27 Power-Down Modes
27.10
Sleep Instruction Exception Handling
A sleep instruction exception handling is generated by executing a SLEEP instruction. The sleep instruction exception handling is always accepted in the program execution state. When the SLPIE bit is set to 0, sleep instruction exception handling does not follow execution of the SLEEP instruction. In this case, the CPU is placed in the power-down state. After exit from the power-down state has been initiated by an exception, the CPU starts handling of the exception. When the SLPIE bit is set to 1, sleep instruction exception handling follows execution of the SLEEP instruction. The CPU immediately starts sleep instruction exception handling, which blocks the transition to the power-down state is prevented by. When a SLEEP instruction is executed while the SLPIE bit is cleared to 0, a transition is made to the power-down state. Exit from the power-down state is initiated by an exit-initiating interrupt source (see figure 27.10). When an interrupt that causes exit from the power-down state is generated immediately before the execution of a SLEEP instruction, exception handling for the interrupt starts. On return from the exception service routine, the SLEEP instruction is executed to enter the power-down state. In this case, exit from the power-down state will not take place until the next time an exit-initiating interrupt is generated (see figure 27.11). As stated above, setting the SLPIE bit to 1 causes sleep instruction exception handling to follow the execution of the SLEEP instruction. If this setting is made in the exception service routine for an interrupt that initiates exit from the power-down state, handling of the sleep instruction exception due to the execution of a SLEEP instruction will proceed even if the interrupt was generated immediately beforehand (see figure 27.12). Consequently, the CPU will execute the instruction that follows the SLEEP instruction, after handling of the sleep instruction exception and exception service routine, and will not enter the power-down state. Thus, when the SLPIE bit is set to 1 to enable the sleep exception handling, clear the SSBY bit in SBYCR to 0.
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Section 27 Power-Down Modes
SLPIE = 0 Instruction before SLEEP instruction
SLEEP instruction executed (SLPIE = 0)
Power-down state Canceling factor interrupt No Yes
Transition by interrupt exception handling
Interrupt handling routine RTE instruction executed
Instruction after SLEEP instruction
Figure 27.10 When an Interrupt that Initiates Exit from the Power-Down State is Generated after SLEEP Instruction Execution
SLPIE = 0 Instruction before SLEEP instruction
Canceling factor interrupt
No
Yes
Transition by interrupt exception handling
Interrupt handling routine RTE instruction executed
SLEEP instruction executed (SLPIE = 0)
Return from the powerdown state after the next canceling factor interrupt is generated
Power-down state
Canceling factor interrupt No
Yes
Transition by interrupt exception handling
Interrupt handling routine RTE instruction executed
Instruction after SLEEP instruction
Figure 27.11 When an Interrupt that Initiates Exit from the Power-Down State is Generated before SLEEP Instruction Execution (Sleep-Instruction Exception Handling does not Proceed)
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Section 27 Power-Down Modes
SLPIE = 0 Instruction before SLEEP instruction
Canceling factor interrupt No
Yes
Transition by interrupt exception handling
Interrupt handling routine RTE instruction executed
SLPIE = 1 SSBY = 0
SLEEP instruction executed (SLPIE = 1)
Sleep instruction exceotion handling
Transition by interrupt exception handling
Vector Number 18 Exception service routine RTE instruction executed
Instruction after SLEEP instruction
Figure 27.12 When an Interrupt that Initiates Exit from the Power-Down State is Generated before SLEEP Instruction Execution (Sleep Instruction Exception Handling Proceeds)
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Section 27 Power-Down Modes
27.11
Clock Output Control
Output of the B clock can be controlled by the PSTOP1 bit in SCKCR, and DDR for the corresponding PA7 pin. Clearing the PSTOP1 bit to 0 enables the B clock output on the PA7 pin. When bit PSTOP1 is set to 1, the B clock output stops at the end of the bus cycle, and the B clock output goes high. When DDR for the PA7 pin is cleared to 0, the B clock output is disabled and the pin becomes an input port. Tables 27.4 shows the states of the B pin in each processing state. Table 27.4 Pin (PA7) State in Each Processing State
Register Setting Value DDR 0 1 1 PSTOP1 x 0 1 Normal Operating Mode Hi-Z B output High Sleep Mode Hi-Z B output High All-ModuleClock-Stop Mode Hi-Z B output High Software Standby Mode OPE = 0 Hi-Z High High OPE = 1 Hi-Z High High Deep Software Standby Mode IOKEEP = 0 IOKEEP = 1 Hi-Z High High Hi-Z High High Hardware Standby Mode Hi-Z Hi-Z Hi-Z
[Legend] x = Don't care
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Section 27 Power-Down Modes
27.12
Usage Notes
27.12.1 I/O Port Status In software standby mode or deep software standby mode, the I/O port states are retained. Therefore, there is no reduction in current drawn due to output currents when high-level signals are being output. 27.12.2 Current Consumption during Oscillation Settling Standby Period Current consumption increases during the oscillation settling standby period. 27.12.3 Module Stop State of EXDMAC, DMAC, or DTC Depending on the operating state of the EXDMAC, DMAC, and DTC, bits MSTPA14, MSTPA13, and MSTPA12 may not be set to 1, respectively. The module stop state setting for the EXDMAC, DMAC, or DTC should be carried out only when the EXDMAC, DMAC, or DTC is not activated. For details, refer to section 10, DMA Controller (DMAC), section 11, EXDMA Controller (EXDMAC), and section 12, Data Transfer Controller (DTC). 27.12.4 On-Chip Peripheral Module Interrupts Relevant interrupt operations cannot be performed in a module stop state. Consequently, if the module stop state is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering a module stop state. 27.12.5 Writing to MSTPCRA, MSTPCRB, and MSTPCRC MSTPCRA, MSTPCRB, and MSTPCRC should only be written to by the CPU.
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Section 27 Power-Down Modes
27.12.6 Control of Input Buffers by DIRQnE (n = 3 to 0) When the input buffers for the P10/IRQ0-A to P13/IRQ3-A pins are enabled by setting the DIRQnE bits (n = 3 to 0) in DSPIER to 1, the PnICR settings corresponding to these pins are invalid. Therefore, note that external inputs to these pins, of which states are reflected on the DIRQnF bits, are also input to the interrupt controller, peripheral modules and I/O ports, after the DIRQnE bits (n = 3 to 0) are set to 1. 27.12.7 Conflict between a transition to deep software standby mode and interrupts If a conflict between a transition to deep software standby mode and generation of software standby mode clearing source occurs, a transition to deep software standby mode is not made but the software standby mode clearing sequence is executed. In this case, an interrupt exception handling for the input interrupt starts after the oscillation settling time for software standby mode (set by the STS4 to STS0 bits in SBYCR) has elapsed. Note that if a conflict between a deep software standby mode transition and NMI interrupt occurs, the NMI interrupt exception handling routine is required. If a conflict between transitions to deep software standby mode, the IRQ0 to IRQ11 interrupts, and voltage-monitoring interrupt* occurs, a transition to deep software standby mode can be made without executing the interrupt handling by clearing the SSIn bits in SSIER to 0 beforehand. Note: * Supported only by the H8SX/1658M Group. 27.12.8 B Output State B output is undefined for a maximum of one cycle immediately after deep software standby mode is canceled with the IOKEEP bit cleared to 0 or immediately after the IOKEEP bit is cleared after cancellation of deep software standby mode with the IOKEEP bit set to 1. However, B can be normally output by setting the IOKEEP and PSTOP1 bits. For details, see section 27.8.4, B Operation after Exit from Deep Software Standby Mode.
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Section 28 List of Registers
Section 28 List of Registers
The register list gives information on the on-chip I/O register addresses, how the register bits are configured, and the register states in each operating mode. The information is given as shown below. Register addresses (address order) Registers are listed from the lower allocation addresses. Registers are classified according to functional modules. The number of Access Cycles indicates the number of states based on the specified reference clock. For details, refer to section 9.5.4, External Bus Interface. * Among the internal I/O register area, addresses not listed in the list of registers are undefined or reserved addresses. Undefined and reserved addresses cannot be accessed. Do not access these addresses; otherwise, the operation when accessing these bits and subsequent operations cannot be guaranteed. Register bits Bit configurations of the registers are listed in the same order as the register addresses. Reserved bits are indicated by in the bit name column. Space in the bit name field indicates that the entire register is allocated to either the counter or data. * For the registers of 16 or 32 bits, the MSB is listed first. * Byte configuration description order is subject to big endian. 3. Register states in each operating mode * Register states are listed in the same order as the register addresses. * For the initialized state of each bit, refer to the register description in the corresponding section. * The register states shown here are for the basic operating modes. If there is a specific reset for an on-chip peripheral module, refer to the section on that on-chip peripheral module. 2. * * * 1. * * *
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Section 28 List of Registers
28.1
Register Addresses (Address Order)
Number Abbreviation of Bits Address TCR_4 TCR_5 TCSR_4 TCSR_5 TCORA_4 TCORA_5 TCORB_4 TCORB_5 TCNT_4 TCNT_5 TCCR_4 TCCR_5 CRCCR CRCDIR CRCDOR TCR_6 TCR_7 TCSR_6 TCSR_7 TCORA_6 TCORA_7 TCORB_6 TCORB_7 TCNT_6 TCNT_7 TCCR_6 TCCR_7 ADDRA_1 ADDRB_1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 16 16 H'FEA40 H'FEA41 H'FEA42 H'FEA43 H'FEA44 H'FEA45 H'FEA46 H'FEA47 H'FEA48 H'FEA49 H'FEA4A H'FEA4B Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 Access Cycles (Read/Write) 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P
Register Name Timer control register_4 Timer control register_5 Timer control/status register_4 Timer control/status register_5 Time constant registerA_4 Time constant registerA_5 Time constant registerB_4 Time constant registerB_5 Timer counter_4 Timer counter_5 Timer counter control register_4 Timer counter control register_5 CRC control register CRC data input register CRC data output register Timer control register_6 Timer control register_7 Timer control/status register_6 Timer control/status register_7 Time constant registerA_6 Time constant registerA_7 Time constant registerB_6 Time constant registerB_7 Timer counter_6 Timer counter_7 Timer counter control register_6 Timer counter control register_7 A/D data register A_1 A/D data register B_1
Module TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5
H'FEA4C CRC H'FEA4D CRC H'FEA4E H'FEA50 H'FEA51 H'FEA52 H'FEA53 H'FEA54 H'FEA55 H'FEA56 H'FEA57 H'FEA58 H'FEA59 H'FEA5A H'FEA5B H'FEA80 H'FEA82 CRC TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 A/D_1 A/D_1
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Section 28 List of Registers
Register Name A/D data register C_1 A/D data register D_1 A/D data register E_1 A/D data register F_1 A/D data register G_1 A/D data register H_1 A/D control/status register_1 A/D control register_1 Interrupt flag register 0 Interrupt flag register 1 Interrupt flag register 2 Interrupt enable register 0 Interrupt enable register 1 Interrupt enable register 2 Interrupt select register 0 Interrupt select register 1 Interrupt select register 2 EP0i data register EP0o data register EP0s data register EP1 data register EP2 data register EP3 data register EP0o receive data size register EP1 receive data size register Data status register FIFO clear register End point store register Trigger register DMA transfer setting register Configuration value register
Number Abbreviation of Bits Address ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_1 ADCR_1 IFR0 IFR1 IFR2 IER0 IER1 IER2 ISR0 ISR1 ISR2 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2 EPDR3 EPSZ0o EPSZ1 DASTS FCLR EPSTL TRG DMA CVR 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FEA84 H'FEA86 H'FEA90 H'FEA92 H'FEA94 H'FEA96 H'FEAA0 H'FEAA1 H'FEE00 H'FEE01 H'FEE02 H'FEE04 H'FEE05 H'FEE06 H'FEE08 H'FEE09 H'FEE0A
Module A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 A/D_1 USB USB USB USB USB USB USB USB USB
Data Width 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Access Cycles (Read/Write) 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P
H'FEE0C USB H'FEE0D USB H'FEE0E H'FEE10 H'FEE14 H'FEE18 H'FEE24 H'FEE25 H'FEE27 H'FEE28 H'FEE2A USB USB USB USB USB USB USB USB USB
H'FEE2C USB H'FEE2D USB H'FEE2E USB
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Section 28 List of Registers
Register Name Control register End point information register Transceiver test register 0 Transceiver test register 1 Port M data direction register Port M data register Port M register Port M input buffer control register Serial mode register_5 Bit rate register_5 Serial control register_5 Transmit data register_5 Serial status register_5 Receive data register_5 Smart card mode register_5 Serial extended mode register_5 IrDA control register Serial mode register_6 Bit rate register_6 Serial control register_6 Transmit data register_6 Serial status register_6 Receive data register_6 Smart card mode register_6 Serial extended mode register_6 PPG output control register_1 PPG output mode register_1 Next data enable register H_1 Next data enable register L_1 Output data register H_1 Output data register L_1
Number Abbreviation of Bits Address CTLR EPIR TRNTREG0 TRNTREG1 PMDDR PMDR PORTM PMICR SMR_5 BRR_5 SCR_5 TDR_5 SSR_5 RDR_5 SCMR_5 SEMR_5 IrCR SMR_6 BRR_6 SCR_6 TDR_6 SSR_6 RDR_6 SCMR_6 SEMR_6 PCR_1 PMR_1 NDERH_1 NDERL_1 PODRH_1 PODRL_1 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FEE2F H'FEE32 H'FEE44 H'FEE45 H'FEE50 H'FEE51 H'FEE52 H'FEE53 H'FF600 H'FF601 H'FF602 H'FF603 H'FF604 H'FF605 H'FF606 H'FF608 H'FF60C H'FF610 H'FF611 H'FF612 H'FF613 H'FF614 H'FF615 H'FF616 H'FF618 H'FF636 H'FF637 H'FF638 H'FF639 H'FF63A H'FF63B
Module USB USB USB USB I/O port I/O port I/O port I/O port SCI_5 SCI_5 SCI_5 SCI_5 SCI_5 SCI_5 SCI_5 SCI_5 SCI_5 SCI_6 SCI_6 SCI_6 SCI_6 SCI_6 SCI_6 SCI_6 SCI_6 PPG_1 PPG_1 PPG_1 PPG_1 PPG_1 PPG_1
Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Access Cycles (Read/Write) 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P 3P/3P
Rev. 2.00 Sep. 25, 2008 Page 1182 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name Next data register H_1* Next data register L_1*
1
Number Abbreviation of Bits Address NDRH_1 NDRL_1 NDRH_1 NDRL_1 BARAH BARAL BAMRAH BAMRAL BARBH BARBL BAMRBH BAMRBL BARCH BARCL BAMRCH BAMRCL BARDH BARDL BAMRDH BAMRDL BRCRA BRCRB BRCRC BRCRD TSTRB TSYRB TCR_6 TMDR_6 TIORH_6 TIORL_6 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 H'FF63C H'FF63D H'FF63E H'FF63F H'FFA00 H'FFA02 H'FFA04 H'FFA06 H'FFA08 H'FFA0A H'FFA0C H'FFA0E H'FFA10 H'FFA12 H'FFA14 H'FFA16 H'FFA18 H'FFA1A H'FFA1C H'FFA1E H'FFA28 H'FFA2C H'FFA30 H'FFA34 H'FFB00 H'FFB01 H'FFB10 H'FFB11 H'FFB12 H'FFB13
Module PPG_1 PPG_1 PPG_1 PPG_1 UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC UBC TPU (unit 1) TPU (unit 1) TPU_6 TPU_6 TPU_6 TPU_6
Data Width 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access Cycles (Read/Write) 3P/3P 3P/3P 3P/3P 3P/3P 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P
1
Next data register H_1* Next data register L_1*
1
1
Break address register AH Break address register AL Break address mask register AH Break address mask register AL Break address register BH Break address register BL Break address mask register BH Break address mask register BL Break address register CH Break address register CL Break address mask register CH Break address mask register CL Break address register DH Break address register DL Break address mask register DH Break address mask register DL Break control register A Break control register B Break control register C Break control register D Timer start register Timer synchronous register Timer control register_6 Timer mode register_6 Timer I/O control register H_6 Timer I/O control register L_6
Rev. 2.00 Sep. 25, 2008 Page 1183 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name Timer interrupt enable register_6 Timer status register_6 Timer counter_6 Timer general register A_6 Timer general register B_6 Timer general register C_6 Timer general register D_6 Timer control register_7 Timer mode register_7 Timer I/O control register_7 Timer interrupt enable register_7 Timer status register_7 Timer counter_7 Timer general register A_7 Timer general register B_7 Timer control register_8 Timer mode register_8 Timer I/O control register_8 Timer interrupt enable register_8 Timer status register_8 Timer counter_8 Timer general register A_8 Timer general register B_8 Timer control register_9 Timer mode register_9 Timer I/O control register H_9 Timer I/O control register L_9 Timer interrupt enable register_9 Timer status register_9 Timer counter_9 Timer general register A_9
Number Abbreviation of Bits Address TIER_6 TSR_6 TCNT_6 TGRA_6 TGRB_6 TGRC_6 TGRD_6 TCR_7 TMDR_7 TIOR_7 TIER_7 TSR_7 TCNT_7 TGRA_7 TGRB_7 TCR_8 TMDR_8 TIOR_8 TIER_8 TSR_8 TCNT_8 TGRA_8 TGRB_8 TCR_9 TMDR_9 TIORH_9 TIORL_9 TIER_9 TSR_9 TCNT_9 TGRA_9 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 8 16 16 H'FFB14 H'FFB15 H'FFB16 H'FFB18 H'FFB1A H'FFB1C H'FFB1E H'FFB20 H'FFB21 H'FFB22 H'FFB24 H'FFB25 H'FFB26 H'FFB28 H'FFB2A H'FFB30 H'FFB31 H'FFB32 H'FFB34 H'FFB35 H'FFB36 H'FFB38 H'FFB3A H'FFB40 H'FFB41 H'FFB42 H'FFB43 H'FFB44 H'FFB45 H'FFB46 H'FFB48
Module TPU_6 TPU_6 TPU_6 TPU_6 TPU_6 TPU_6 TPU_6 TPU_7 TPU_7 TPU_7 TPU_7 TPU_7 TPU_7 TPU_7 TPU_7 TPU_8 TPU_8 TPU_8 TPU_8 TPU_8 TPU_8 TPU_8 TPU_8 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9 TPU_9
Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P
Rev. 2.00 Sep. 25, 2008 Page 1184 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name Timer general register B_9 Timer general register C_9 Timer general register D_9 Timer control register_10 Timer mode register_10 Timer I/O control register_10 Timer interrupt enable register_10 Timer status register_10 Timer counter_10 Timer general register A_10 Timer general register B_10 Timer control register_11 Timer mode register_11 Timer I/O control register_11 Timer interrupt enable register_11 Timer status register_11 Timer counter_11 Timer general register A_11 Timer general register B_11 Port 1 data direction register Port 2 data direction register Port 6 data direction register Port A data direction register Port B data direction register Port D data direction register Port E data direction register Port F data direction register Port 1 input buffer control register Port 2 input buffer control register Port 5 input buffer control register Port 6 input buffer control register
Number Abbreviation of Bits Address TGRB_9 TGRC_9 TGRD_9 TCR_10 TMDR_10 TIOR_10 TIER_10 TSR_10 TCNT_10 TGRA_10 TGRB_10 TCR_11 TMDR_11 TIOR_11 TIER_11 TSR_11 TCNT_11 TGRA_11 TGRB_11 P1DDR P2DDR P6DDR PADDR PBDDR PDDDR PEDDR PFDDR P1ICR P2ICR P5ICR P6ICR 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 H'FFB4A H'FFB4C H'FFB4E H'FFB50 H'FFB51 H'FFB52 H'FFB54 H'FFB55 H'FFB56 H'FFB58 H'FFB5A H'FFB60 H'FFB61 H'FFB62 H'FFB64 H'FFB65 H'FFB66 H'FFB68 H'FFB6A H'FFB80 H'FFB81 H'FFB85 H'FFB89 H'FFB8A H'FFB8C H'FFB8D H'FFB8E H'FFB90 H'FFB91 H'FFB94 H'FFB95
Module TPU_9 TPU_9 TPU_9 TPU_10 TPU_10 TPU_10 TPU_10 TPU_10 TPU_10 TPU_10 TPU_10 TPU_11 TPU_11 TPU_11 TPU_11 TPU_11 TPU_11 TPU_11 TPU_11 I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port
Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8
Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P
Rev. 2.00 Sep. 25, 2008 Page 1185 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name Port A input buffer control register Port B input buffer control register Port D input buffer control register Port E input buffer control register Port F input buffer control register Port H register Port I register Port J register Port K register Port H data register Port I data register Port J data register Port K data register Port H data direction register Port I data direction register Port J data direction register Port K data direction register Port H input buffer control register Port I input buffer control register Port J input buffer control register Port K input buffer control register Port D pull-up MOS control register Port E pull-up MOS control register Port F pull-up MOS control register Port H pull-up MOS control register Port I pull-up MOS control register Port J pull-up MOS control register Port K pull-up MOS control register Port 2 open-drain control register Port F open-drain control register Port function control register 0
Number Abbreviation of Bits Address PAICR PBICR PDICR PEICR PFICR PORTH PORTI PORTJ PORTK PHDR PIDR PJDR PKDR PHDDR PIDDR PJDDR PKDDR PHICR PIICR PJICR PKICR PDPCR PEPCR PFPCR PHPCR PIPCR PJPCR PKPCR P2ODR PFODR PFCR0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFB99 H'FFB9A H'FFB9C H'FFB9D H'FFB9E H'FFBA0 H'FFBA1 H'FFBA2 H'FFBA3 H'FFBA4 H'FFBA5 H'FFBA6 H'FFBA7 H'FFBA8 H'FFBA9
Module I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port
Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/3P
H'FFBAA I/O port H'FFBAB I/O port H'FFBAC I/O port H'FFBAD I/O port H'FFBAE I/O port H'FFBAF H'FFBB4 H'FFBB5 H'FFBB6 H'FFBB8 H'FFBB9 I/O port I/O port I/O port I/O port I/O port I/O port
H'FFBBA I/O port H'FFBBB I/O port H'FFBBC I/O port H'FFBBD I/O port H'FFBC0 I/O port
Rev. 2.00 Sep. 25, 2008 Page 1186 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name Port function control register 1 Port function control register 2 Port function control register 4 Port function control register 6 Port function control register 7 Port function control register 8 Port function control register 9 Port function control register A Port function control register B Port function control register C Port function control register D
Number Abbreviation of Bits Address PFCR1 PFCR2 PFCR4 PFCR6 PFCR7 PFCR8 PFCR9 PFCRA PFCRB PFCRC PFCRD 8 8 8 8 8 8 8 8 8 8 8 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 32 32 H'FFBC1 H'FFBC2 H'FFBC4 H'FFBC6 H'FFBC7 H'FFBC8 H'FFBC9
Module I/O port I/O port I/O port I/O port I/O port I/O port I/O port
Data Width 8 8 8 8 8 8 8 8 8 8 8 8
Access Cycles (Read/Write) 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2P/3P 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/2I 2I/2I
H'FFBCA I/O port H'FFBCB I/O port H'FFBCC I/O port H'FFBCD I/O port H'FFBCE INTC H'FFBF0 H'FFBF1 H'FFBF2 H'FFBF3 H'FFBF4 H'FFBF5 H'FFBF6 H'FFBF7 H'FFBF8 H'FFBF9 H'FFBFA H'FFBFB
Software standby release IRQ enable SSIER register Deep standby backup register 0 Deep standby backup register 1 Deep standby backup register 2 Deep standby backup register 3 Deep standby backup register 4 Deep standby backup register 5 Deep standby backup register 6 Deep standby backup register 7 Deep standby backup register 8 Deep standby backup register 9 Deep standby backup register 10 Deep standby backup register 11 Deep standby backup register 12 Deep standby backup register 13 Deep standby backup register 14 Deep standby backup register 15 DMA source address register_0 DMA destination address register_0 DPSBKR0 DPSBKR1 DPSBKR2 DPSBKR3 DPSBKR4 DPSBKR5 DPSBKR6 DPSBKR7 DPSBKR8 DPSBKR9 DPSBKR10 DPSBKR11 DPSBKR12 DPSBKR13 DPSBKR14 DPSBKR15 DSAR_0 DDAR_0
SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8
H'FFBFC SYSTEM 8 H'FFBFD SYSTEM 8 H'FFBFE H'FFBFF H'FFC00 H'FFC04 SYSTEM 8 SYSTEM 8 DMAC_0 16 DMAC_0 16
Rev. 2.00 Sep. 25, 2008 Page 1187 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name DMA offset register_0 DMA transfer count register_0 DMA block size register_0 DMA mode control register_0 DMA address control register_0 DMA source address register_1 DMA destination address register_1 DMA offset register_1 DMA transfer count register_1 DMA block size register_1 DMA mode control register_1 DMA address control register_1 DMA source address register_2 DMA destination address register_2 DMA offset register_2 DMA transfer count register_2 DMA block size register_2 DMA mode control register_2 DMA address control register_2 DMA source address register_3 DMA destination address register_3 DMA offset register_3 DMA transfer count register_3 DMA block size register_3 DMA mode control register_3 DMA address control register_3 EXDMA source address register_0 EXDMA destination address register_0 EXDMA offset register_0
Number Abbreviation of Bits Address DOFR_0 DTCR_0 DBSR_0 DMDR_0 DACR_0 DSAR_1 DDAR_1 DOFR_1 DTCR_1 DBSR_1 DMDR_1 DACR_1 DSAR_2 DDAR_2 DOFR_2 DTCR_2 DBSR_2 DMDR_2 DACR_2 DSAR_3 DDAR_3 DOFR_3 DTCR_3 DBSR_3 DMDR_3 DACR_3 EDSAR_0 EDDAR_0 EDOFR_0 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 H'FFC08
Module
Data Width
Access Cycles (Read/Write) 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I
DMAC_0 16
H'FFC0C DMAC_0 16 H'FFC10 H'FFC14 H'FFC18 H'FFC20 H'FFC24 H'FFC28 DMAC_0 16 DMAC_0 16 DMAC_0 16 DMAC_1 16 DMAC_1 16 DMAC_1 16
H'FFC2C DMAC_1 16 H'FFC30 H'FFC34 H'FFC38 H'FFC40 H'FFC44 H'FFC48 DMAC_1 16 DMAC_1 16 DMAC_1 16 DMAC_2 16 DMAC_2 16 DMAC_2 16
H'FFC4C DMAC_2 16 H'FFC50 H'FFC54 H'FFC58 H'FFC60 H'FFC64 H'FFC68 DMAC_2 16 DMAC_2 16 DMAC_2 16 DMAC_3 16 DMAC_3 16 DMAC_3 16
H'FFC6C DMAC_3 16 H'FFC70 H'FFC74 H'FFC78 H'FFC80 H'FFC84 H'FFC88 DMAC_3 16 DMAC_3 16 DMAC_3 16 EXDMAC 16 _0 EXDMAC 16 _0 EXDMAC 16 _0
Rev. 2.00 Sep. 25, 2008 Page 1188 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name EXDMA transfer count register_0 EXDMA block size register_0 EXDMA mode control regisrer_0 EXDMA address control register_0 EXDMA source address register_1 EXDMA destination address register_1 EXDMA offset register_1 EXDMA transfer count register_1 EXDMA block size register_1 EXDMA mode control register_1 EXDMA address control register_1 EXDMA source address register_2 EXDMA destination address register_2 EXDMA offset register_2 EXDMA transfer count register_2 EXDMA block size register_2 EXDMA mode control register_2 EXDMA address control register_2
Number Abbreviation of Bits Address EDTCR_0 EDBSR_0 EDMDR_0 EDACR_0 EDSAR_1 EDDAR_1 EDOFR_1 EDTCR_1 EDBSR_1 EDMDR_1 EDACR_1 EDSAR_2 EDDAR_2 EDOFR_2 EDTCR_2 EDBSR_2 EDMDR_2 EDACR_2 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32
Module
Data Width
Access Cycles (Read/Write) 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I
H'FFC8C EXDMAC 16 _0 H'FFC90 H'FFC94 H'FFC98 H'FFCA0 H'FFCA4 H'FFCA8 EXDMAC 16 _0 EXDMAC 16 _0 EXDMAC 16 _0 EXDMAC 16 _1 EXDMAC 16 _1 EXDMAC 16 _1
H'FFCAC EXDMAC 16 _1 H'FFCB0 H'FFCB4 H'FFCB8 EXDMAC 16 _1 EXDMAC 16 _1 EXDMAC 16 _1
H'FFCC0 EXDMAC 16 _2 H'FFCC4 EXDMAC 16 _2 H'FFCC8 EXDMAC 16 _2 H'FFCCC EXDMAC 16 _2 H'FFCD0 EXDMAC 16 _2 H'FFCD4 EXDMAC 16 _2 H'FFCD8 EXDMAC 16 _2
Rev. 2.00 Sep. 25, 2008 Page 1189 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name EXDMA source address register_3 EXDMA destination address register_3 EXDMA offset register_3 EXDMA transfer count register_3 EXDMA block size register_3 EXDMA mode control register_3 EXDMA address control register_3 Cluster buffer register 0 Cluster buffer register 1 Cluster buffer register 2 Cluster buffer register 3 Cluster buffer register 4 Cluster buffer register 5 Cluster buffer register 6 Cluster buffer register 7
Number Abbreviation of Bits Address EDSAR_3 EDDAR_3 EDOFR_3 EDTCR_3 EDBSR_3 EDMDR_3 EDACR_3 CLSBR0 CLSBR1 CLSBR2 CLSBR3 CLSBR4 CLSBR5 CLSBR6 CLSBR7 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 8 8 8 8 16 16 16 16 16 16 16 H'FFCE0 H'FFCE4 H'FFCE8
Module
Data Width
Access Cycles (Read/Write) 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I
EXDMAC 16 _3 EXDMAC 16 _3 EXDMAC 16 _3
H'FFCEC EXDMAC 16 _3 H'FFCF0 H'FFCF4 H'FFCF8 H'FFD00 H'FFD04 H'FFD08 EXDMAC 16 _3 EXDMAC 16 _3 EXDMAC 16 _3 EXDMAC 16 EXDMAC 16 EXDMAC 16
H'FFD0C EXDMAC 16 H'FFD10 H'FFD14 H'FFD18 EXDMAC 16 EXDMAC 16 EXDMAC 16
H'FFD1C EXDMAC 16 H'FFD20 H'FFD21 H'FFD22 H'FFD23 H'FFD40 H'FFD42 H'FFD44 H'FFD48 H'FFD4A DMAC_0 16 DMAC_1 16 DMAC_2 16 DMAC_3 16 INTC INTC INTC INTC INTC 16 16 16 16 16 16 16
DMA module request select register_0 DMRSR_0 DMA module request select register_1 DMRSR_1 DMA module request select register_2 DMRSR_2 DMA module request select register_3 DMRSR_3 Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H IPRA IPRB IPRC IPRE IPRF IPRG IPRH
H'FFD4C INTC H'FFD4E INTC
Rev. 2.00 Sep. 25, 2008 Page 1190 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name Interrupt priority register I Interrupt priority register J Interrupt priority register K Interrupt priority register L Interrupt priority register M Interrupt priority register N Interrupt priority register O Interrupt priority register Q Interrupt priority register R IRQ sense control register H IRQ sense control register L DTC vector base register Bus width control register Access state control register Wait control register A Wait control register B Read strobe timing control register CS assertion period control register Idle control register Bus control register 1 Bus control register 2 Endian control register SRAM mode control register Burst ROM interface control register Address/data multiplexed I/O control register RAM emulation register Mode control register System control register System clock control register Standby control register
Number Abbreviation of Bits Address IPRI IPRJ IPRK IPRL IPRM IPRN IPRO IPRQ IPRR ISCRH ISCRL DTCVBR ABWCR ASTCR WTCRA WTCRB RDNCR CSACR IDLCR BCR1 BCR2 ENDIANCR SRAMCR BROMCR MPXCR RAMER MDCR SYSCR SCKCR SBYCR 16 16 16 16 16 16 16 16 16 16 16 32 16 16 16 16 16 16 16 16 8 8 16 16 16 8 16 16 16 16 H'FFD50 H'FFD52 H'FFD54 H'FFD56 H'FFD58 H'FFD5A
Module INTC INTC INTC INTC INTC INTC
Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access Cycles (Read/Write) 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I
H'FFD5C INTC H'FFD60 H'FFD62 H'FFD68 H'FFD6A H'FFD80 H'FFD84 H'FFD86 H'FFD88 H'FFD8A INTC INTC INTC INTC BSC BSC BSC BSC BSC
H'FFD8C BSC H'FFD8E H'FFD90 H'FFD92 H'FFD94 H'FFD95 H'FFD98 H'FFD9A BSC BSC BSC BSC BSC BSC BSC
H'FFD9C BSC H'FFD9E BSC
H'FFDC0 SYSTEM 16 H'FFDC2 SYSTEM 16 H'FFDC4 SYSTEM 16 H'FFDC6 SYSTEM 16
Rev. 2.00 Sep. 25, 2008 Page 1191 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name Module stop control register A Module stop control register B Module stop control register C Flash code control/status register Flash program code select register Flash erase code select register Flash key code register Flash MAT select register Flash transfer destination address register Deep standby control register Deep standby wait control register
Number Abbreviation of Bits Address MSTPCRA MSTPCRB MSTPCRC FCCS FPCS FECS FKEY FMATS FTDAR DPSBYCR DPSWCR 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Module
Data Width
Access Cycles (Read/Write) 2I/3I 2I/3I 2I/3I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P
H'FFDC8 SYSTEM 16 H'FFDCA SYSTEM 16 H'FFDCC SYSTEM 16 H'FFDE8 H'FFDE9 FLASH FLASH 16 16 16 16 16 16
H'FFDEA FLASH H'FFDEC FLASH H'FFDED FLASH H'FFDEE FLASH H'FFE70 H'FFE71 H'FFE72 H'FFE73 H'FFE74 H'FFE75 H'FFE78 H'FFE84 H'FFE90 H'FFE91 H'FFE92 H'FFE93 H'FFE94 H'FFE95 H'FFE96 H'FFEB0 H'FFEB1 H'FFEB2 H'FFEB3 H'FFEB4 H'FFEB5
SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SYSTEM 8 SCI_2 SCI_4 SCI_4 SCI_4 SCI_4 SCI_4 SCI_4 SCI_4 IIC2_0 IIC2_0 IIC2_0 IIC2_0 IIC2_0 IIC2_0 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Deep standby interrupt enable register DPSIER Deep standby interrupt flag register Deep standby interrupt edge register Reset status register Low voltage detection control 2 register* Serial extended mode register_2 Serial mode register_4 Bit rate register_4 Serial control register_4 Transmit data register_4 Serial status register_4 Receive data register_4 Smart card mode register_4 I C bus control register A_0 I C bus control register B_0 I C bus mode register_0 I C bus interrupt enable register_0 I C bus status register_0 Slave address register_0
2 2 2 2 2
DPSIFR DPSIEGR RSTSR LVDCR SEMR_2 SMR_4 BRR_4 SCR_4 TDR_4 SSR_4 RDR_4 SCMR_4 ICCRA_0 ICCRB_0 ICMR_0 ICIER_0 ICSR_0 SAR_0
Rev. 2.00 Sep. 25, 2008 Page 1192 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name I C bus transmit data register_0 I C bus receive data register_0 I C bus control register A_1 I C bus control register B_1 I C bus mode register_1 I C bus interrupt enable register_1 I C bus status register_1 Slave address register_1 I C bus transmit data register_1 I C bus receive data register_1 Timer control register_2 Timer control register_3 Timer control/status register_2 Timer control/status register_3 Time constant register A_2 Time constant register A_3 Time constant register B_2 Time constant register B_3 Timer counter_2 Timer counter_3 Timer counter control register_2 Timer counter control register_3 Timer control register_4 Timer mode register_4 Timer I/O control register_4 Timer interrupt enable register_4 Timer status register_4 Timer counter_4 Timer general register A_4 Timer general register B_4 Timer control register_5
2 2 2 2 2 2 2 2 2
Number Abbreviation of Bits Address ICDRT_0 ICDRR_0 ICCRA_1 ICCRB_1 ICMR_1 ICIER_1 ICSR_1 SAR_1 ICDRT_1 ICDRR_1 TCR_2 TCR_3 TCSR_2 TCSR_3 TCORA_2 TCORA_3 TCORB_2 TCORB_3 TCNT_2 TCNT_3 TCCR_2 TCCR_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4 TGRA_4 TGRB_4 TCR_5 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 8 H'FFEB6 H'FFEB7 H'FFEB8 H'FFEB9
Module IIC2_0 IIC2_0 IIC2_1 IIC2_1
Data Width 8 8 8 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P
H'FFEBA IIC2_1 H'FFEBB IIC2_1 H'FFEBC IIC2_1 H'FFEBD IIC2_1 H'FFEBE IIC2_1 H'FFEBF H'FFEC0 H'FFEC1 H'FFEC2 H'FFEC3 H'FFEC4 H'FFEC5 H'FFEC6 H'FFEC7 H'FFEC8 H'FFEC9 IIC2_1 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3
H'FFECA TMR_2 H'FFECB TMR_3 H'FFEE0 H'FFEE1 H'FFEE2 H'FFEE4 H'FFEE5 H'FFEE6 H'FFEE8 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4 TPU_4
H'FFEEA TPU_4 H'FFEF0 TPU_5
Rev. 2.00 Sep. 25, 2008 Page 1193 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name Timer mode register_5 Timer I/O control register_5 Timer interrupt enable register_5 Timer status register_5 Timer counter_5 Timer general register A_5 Timer general register B_5 DTC enable register A DTC enable register B DTC enable register C DTC enable register D DTC enable register E DTC enable register F DTC control register Interrupt control register CPU priority control register IRQ enable register IRQ status register Port 1 register Port 2 register Port 5 register Port 6 register Port A register Port B register Port D register Port E register Port F register Port 1 data register Port 2 data register Port 6 data register Port A data register
Number Abbreviation of Bits Address TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 TGRA_5 TGRB_5 DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCCR INTCR CPUPCR IER ISR PORT1 PORT2 PORT5 PORT6 PORTA PORTB PORTD PORTE PORTF P1DR P2DR P6DR PADR 8 8 8 8 16 16 16 16 16 16 16 16 16 8 8 8 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFEF1 H'FFEF2 H'FFEF4 H'FFEF5 H'FFEF6 H'FFEF8 H'FFEFA H'FFF20 H'FFF22 H'FFF24 H'FFF26 H'FFF28 H'FFF2A H'FFF30 H'FFF32 H'FFF33 H'FFF34 H'FFF36 H'FFF40 H'FFF41 H'FFF44 H'FFF45 H'FFF49 H'FFF4A H'FFF4C H'FFF4D H'FFF4E H'FFF50 H'FFF51 H'FFF55 H'FFF59
Module TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 TPU_5 INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC INTC I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port I/O port
Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8
Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2I/3I 2P/2P/2P/2P/2P/2P/2P/2P/2P/2P/2P 2P/2P 2P/2P 2P/2P
Rev. 2.00 Sep. 25, 2008 Page 1194 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name Port B data register Port D data register Port E data register Port F data register Serial mode register_2 Bit rate register_2 Serial control register_2 Transmit data register_2 Serial status register_2 Receive data register_2 Smart card mode register_2 D/A data register 0 D/A data register 1 D/A control register 01 PPG output control register PPG output mode register Next data enable register H Next data enable register L Output data register H Output data register L Next data register H* Next data register L* Next data register H* Next data register L* Serial mode register_0 Bit rate register_0 Serial control register_0 Transmit data register_0 Serial status register_0 Receive data register_0 Smart card mode register_0
Number Abbreviation of Bits Address PBDR PDDR PEDR PFDR SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DADR0 DADR1 DACR01 PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL NDRH NDRL SMR_0 BRR_0 SCR_0 TDR_0 SSR_0 RDR_0 SCMR_0 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFF5A H'FFF5C H'FFF5D H'FFF5E H'FFF60 H'FFF61 H'FFF62 H'FFF63 H'FFF64 H'FFF65 H'FFF66 H'FFF68 H'FFF69 H'FFF6A H'FFF76 H'FFF77 H'FFF78 H'FFF79 H'FFF7A H'FFF7B H'FFF7C H'FFF7D H'FFF7E H'FFF7F H'FFF80 H'FFF81 H'FFF82 H'FFF83 H'FFF84 H'FFF85 H'FFF86
Module I/O port I/O port I/O port I/O port SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 SCI_2 D/A D/A D/A PPG_0 PPG_0 PPG_0 PPG_0 PPG_0 PPG_0 PPG_0 PPG_0 PPG_0 PPG_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0 SCI_0
Data Width 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8
Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P
Rev. 2.00 Sep. 25, 2008 Page 1195 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name Serial mode register_1 Bit rate register_1 Serial control register_1 Transmit data register_1 Serial status register_1 Receive data register_1 Smart card mode register_1 A/D data register A_0 A/D data register B_0 A/D data register C_0 A/D data register D_0 A/D data register E_0 A/D data register F_0 A/D data register G_0 A/D data register H_0 A/D control/status register_0 A/D control register_0 Timer control/status register Timer counter Reset control/status register Timer control register_0 Timer control register_1 Timer control/status register_0 Timer control/status register_1 Time constant register A_0 Time constant register A_1 Time constant register B_0 Time constant register B_1 Timer counter_0 Timer counter_1 Timer counter control register_0
Number Abbreviation of Bits Address SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ADDRA_0 ADDRB_0 ADDRC_0 ADDRD_0 ADDRE_0 ADDRF_0 ADDRG_0 ADDRH_0 ADCSR_0 ADCR_0 TCSR TCNT RSTCSR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 TCCR_0 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 H'FFF88 H'FFF89 H'FFF8A H'FFF8B H'FFF8C H'FFF8D H'FFF8E H'FFF90 H'FFF92 H'FFF94 H'FFF96 H'FFF98 H'FFF9A H'FFF9C H'FFF9E H'FFFA0 H'FFFA1 H'FFFA4 H'FFFA5 H'FFFA7 H'FFFB0 H'FFFB1 H'FFFB2 H'FFFB3 H'FFFB4 H'FFFB5 H'FFFB6 H'FFFB7 H'FFFB8 H'FFFB9 H'FFFBA
Module SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 SCI_1 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 A/D_0 WDT WDT WDT TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0
Data Width 8 8 8 8 8 8 8 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/3P 2P/3P 2P/3P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P
Rev. 2.00 Sep. 25, 2008 Page 1196 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name Timer counter control register_1 Timer start register Timer synchronous register Timer control register_0 Timer mode register_0 Timer I/O control register H_0 Timer I/O control register L_0 Timer interrupt enable register_0 Timer status register_0 Timer counter_0 Timer general register A_0 Timer general register B_0 Timer general register C_0 Timer general register D_0 Timer control register_1 Timer mode register_1 Timer I/O control register_1 Timer interrupt enable register_1 Timer status register_1 Timer counter_1 Timer general register A_1 Timer general register B_1 Timer control register_2 Timer mode register_2 Timer I/O control register_2 Timer interrupt enable register_2 Timer status register_2 Timer counter_2 Timer general register A_2 Timer general register B_2 Timer control register_3
Number Abbreviation of Bits Address TCCR_1 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1 TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCR_3 8 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 16 16 16 8 8 8 8 8 16 16 16 8 H'FFFBB
Module TMR_1
Data Width 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P
H'FFFBC TPU H'FFFBD TPU H'FFFC0 H'FFFC1 H'FFFC2 H'FFFC3 H'FFFC4 H'FFFC5 H'FFFC6 H'FFFC8 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0 TPU_0
H'FFFCA TPU_0 H'FFFCC TPU_0 H'FFFCE TPU_0 H'FFFD0 H'FFFD1 H'FFFD2 H'FFFD4 H'FFFD5 H'FFFD6 H'FFFD8 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1 TPU_1
H'FFFDA TPU_1 H'FFFE0 H'FFFE1 H'FFFE2 H'FFFE4 H'FFFE5 H'FFFE6 H'FFFE8 H'FFFEA H'FFFF0 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_2 TPU_3
Rev. 2.00 Sep. 25, 2008 Page 1197 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Name Timer mode register_3 Timer I/O control register H_3 Timer I/O control register L_3 Timer interrupt enable register_3 Timer status register_3 Timer counter_3 Timer general register A_3 Timer general register B_3 Timer general register C_3 Timer general register D_3
Number Abbreviation of Bits Address TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3 8 8 8 8 8 16 16 16 16 16 H'FFFF1 H'FFFF2 H'FFFF3 H'FFFF4 H'FFFF5 H'FFFF6 H'FFFF8 H'FFFFA H'FFFFC H'FFFFE
Module TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3 TPU_3
Data Width 16 16 16 16 16 16 16 16 16 16
Access Cycles (Read/Write) 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P 2P/2P
Notes: 1. When the same output trigger is specified for pulse output groups 2 and 3 by the PCR setting, the NDRH address is H'FFF7C. When different output triggers are specified, the NDRH addresses for pulse output groups 2 and 3 are H'FFF7E and H'FFF7C, respectively. Similarly, when the same output trigger is specified for pulse output groups 0 and 1 by the PCR setting, the NDRL address is H'FFF7D. When different output triggers are specified, the NDRL addresses for pulse output groups 0 and 1 are H'FFF7F and H'FFF7D, respectively. When the same output trigger is specified for pulse output groups 6 and 7 by the PCR setting, the NDRH address is H'FF63C. When different output triggers are specified, the NDRH addresses for pulse output groups 6 and 7 are H'FF63E and H'FF63C, respectively. When the same output trigger is specified for pulse output groups 4 and 5 by the PCR setting, the NDRL address is H'FF63D. When different output triggers are specified, the NDRL addresses for pulse output groups 4 and 5 are H'FF63F and H'FF63D, respectively. 2. Supported only by the H8SX/1658M Group.
Rev. 2.00 Sep. 25, 2008 Page 1198 of 1340 REJ09B0413-0200
Section 28 List of Registers
28.2
Register Bits
Register addresses and bit names of the on-chip peripheral modules are described below. Each line covers eight bits, and 16-bit and 32-bit registers are shown as 2 or 4 lines, respectively.
Register Abbreviation TCR_4 TCR_5 TCSR_4 TCSR_5 TCORA_4 TCORA_5 TCORB_4 TCORB_5 TCNT_4 TCNT_5 TCCR_4 TCCR_5 CRCCR CRCDIR CRCDOR TCR_6 TCR_7 TCSR_6 TCSR_7 TCORA_6 TCORA_7 TCORB_6 TCORB_7 TCNT_6 TCNT_7 CMIEB CMIEB CMFB CMFB CMIEA CMIEA CMFA CMFA OVIE OVIE OVF OVF CCLR1 CCLR1 ADTE CCLR0 CCLR0 OS3 OS3 CKS2 CKS2 OS2 OS2 CKS1 CKS1 OS1 OS1 CKS0 CKS0 OS0 OS0 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 DORCLR TMRIS TMRIS LMS ICKS1 ICKS1 G1 ICKS0 ICKS0 G0 Bit Bit Bit Bit Bit Bit Bit Bit 24/16/8/0 CKS0 CKS0 OS0 OS0 Module TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 CRC
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 CMIEB CMIEB CMFB CMFB CMIEA CMIEA CMFA CMFA OVIE OVIE OVF OVF CCLR1 CCLR1 ADTE CCLR0 CCLR0 OS3 OS3 CKS2 CKS2 OS2 OS2 CKS1 CKS1 OS1 OS1
Rev. 2.00 Sep. 25, 2008 Page 1199 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation TCCR_6 TCCR_7 ADDRA_1
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 ICKS0 ICKS0 Module TMR_6 TMR_7 A/D_1
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 TMRIS TMRIS ICKS1 ICKS1
ADDRB_1
ADDRC_1
ADDRD_1
ADDRE_1
ADDRF_1
ADDRG_1
ADDRH_1
ADCSR_1 ADCR_1 IFR0 IFR1 IFR2 IER0 IER1 IER2 ISR0
ADF TRGS1 BRST BRST SSRSME BRST
ADIE TRGS0
ADST SCANE
EXCKS SCANS
CH3 CKS1
CH2 CKS0
CH1
CH0
ADSTCLR EXTRGS EP0i TR EP3 TS SETC EP0i TR EP3 TS SETCE EP0i TR EP0i TS VBUSF SETI EP0i TS VBUSF SETIE EP0i TS USB
EP1 FULL EP2 TR SURSS
EP2 EMPTY SETUP TS EP0o TS
SURSF
VBUS MN EP3 TR CFDN
EP1 FULL EP2 TR
EP2 EMPTY SETUP TS EP0o TS
SURSE EP2 EMPTY
CFDN
EP3 TR
EP1 FULL EP2 TR
SETUP TS EP0o TS
ISR1

EP3 TR
EP3 TS
VBUSF
Rev. 2.00 Sep. 25, 2008 Page 1200 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation ISR2 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2 EPDR3 EPSZ0o EPSZ1 DASTS FCLR EPSTL TRG DMA
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 SETIE D0 D0 D0 D0 D0 D0 EP0i DE Module USB
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 D7 D7 D7 D7 D7 D7 D6 D6 D6 D6 D6 D6 EP3 CLR D5 D5 D5 D5 D5 D5 EP3 DE EP1 CLR SURSE D4 D4 D4 D4 D4 D4 EP2 DE EP2 CLR CFDN D3 D3 D3 D3 D3 D3 EP3STL D2 D2 D2 D2 D2 D2 EP2STL
EP0s RDFN
SETCE D1 D1 D1 D1 D1 D1
EP0o CLR EP0i CLR EP1STL EP0STL
EP3 PKTE EP1 RDFN
EP2 PKTE RSME D3
EP0o RDFN EP0i PKTE
PULLUP_ E
EP2DMAE EP1DMAE
CVR CTLR EPIR TRNTREG0 TRNTREG1 PMDDR PMDR PORTM PMICR SMR_5*
1
CNFV1 D7 PTSTE C/A (GM)
CNFV0 D6 CHR (BLK)
INTV1 D5 PE (PE)
INTV0 RWUPS D4 PM4DDR PM4DR PM4 PM4ICR O/E (O/E)
ALTV2 RWMD D2
ALTV1 ASCE D1 txse0 dpls PM1DDR PM1DR PM1 PM1ICR CKS1
ALTV0 D0 txdata dmns PM0DDR PM0DR PM0 PM0ICR CKS0 SCI_5 I/O port
SUSPEND txenl PM3DDR PM3DR PM3 PM3ICR STOP (BCP1) xver_data PM2DDR PM2DR PM2 PM2ICR MP (BCP0)
BRR_5 SCR_5*1 TDR_5 TIE RIE TE RE MPIE TEIE CKE1 CKE0
Rev. 2.00 Sep. 25, 2008 Page 1201 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation SSR_5*1
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 MPBT Module SCI_5
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 TDRE RDRF ORER FER (ERS) PER TEND MPB
RDR_5 SCMR_5 SEMR_5 IrCR SMR_6*
1
IrE C/A (GM)
IrCKS2 CHR (BLK)
IrCKS1 PE (PE)
ABCS IrCKS0 O/E (O/E)
SDIR ACS3 IrTxINV STOP (BCP1)
SINV ACS2 IrRxINV MP (BCP0)
ACS1 CKS1
SMIF ACS0 CKS0 SCI_6
BRR_6 SCR_6*1 TDR_6 SSR_6*1 TDRE RDRF ORER FER (ERS) RDR_6 SCMR_6 SEMR_6 PCR_1 PMR_1 NDERH_1 NDERL_1 PODRH_1 PODRL_1 NDRH_1*
2
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
PER
TEND
MPB
MPBT
G3CMS1 G3INV NDER31 NDER23 POD31 POD23 NDR31 NDR23 BARA31 BARA23
G3CMS0 G2INV NDER30 NDER22 POD30 POD22 NDR30 NDR22 BARA30 BARA22
G2CMS1 G1INV NDER29 NDER21 POD29 POD21 NDR29 NDR21 BARA29 BARA21
ABCS G2CMS0 G0INV NDER28 NDER20 POD28 POD20 NDR28 NDR20 BARA28 BARA20
SDIR ACS3 G1CMS1 G3NOV NDER27 NDER19 POD27 POD19 NDR27 NDR19 NDR27 NDR19 BARA27 BARA19
SINV ACS2 G1CMS0 G2NOV NDER26 NDER18 POD26 POD18 NDR26 NDR18 NDR26 NDR18 BARA26 BARA18
ACS1 G0CMS1 G1NOV NDER25 NDER17 POD25 POD17 NDR25 NDR17 NDR25 NDR17 BARA25 BARA17
SMIF ACS0 G0CMS0 G0NOV NDER24 NDER16 POD24 POD16 NDR24 NDR16 NDR24 NDR16 BARA24 BARA16 UBC PPG_1
NDRL_1*2 NDRH_1*2 NDRL_1* BARAH
2
Rev. 2.00 Sep. 25, 2008 Page 1202 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation BARAL
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 BARA8 BARA0
BAMRA24 BAMRA16
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 BARA15 BARA7 BARA14 BARA6
BAMRA30 BAMRA22
Module UBC
BARA13 BARA5
BAMRA29 BAMRA21
BARA12 BARA4
BAMRA28 BAMRA20
BARA11 BARA3
BAMRA27 BAMRA19
BARA10 BARA2
BAMRA26 BAMRA18
BARA9 BARA1
BAMRA25 BAMRA17
BAMRAH
BAMRA31 BAMRA23
BAMRAL
BAMRA15 BAMRA14 BAMRA13 BAMRA12 BAMRA11 BAMRA10 BAMRA9 BAMRA7 BAMRA6 BARB30 BARB22 BARB14 BARB6 BAMRA5 BARB29 BARB21 BARB13 BARB5 BAMRA4 BARB28 BARB20 BARB12 BARB4 BAMRA3 BARB27 BARB19 BARB11 BARB3 BAMRA2 BARB26 BARB18 BARB10 BARB2 BAMRA1 BARB25 BARB17 BARB9 BARB1
BAMRA8 BAMRA0 BARB24 BARB16 BARB8 BARB0
BARBH
BARB31 BARB23
BARBL
BARB15 BARB7
BAMRBH
BAMRB31 BAMRB30 BAMRB29 BAMRB28 BAMRB27 BAMRB26 BAMRB25 BAMRB24 BAMRB23 BAMRB22 BAMRB21 BAMRB20 BAMRB19 BAMRB18 BAMRB17 BAMRB16
BAMRBL
BAMRB15 BAMRB14 BAMRB13 BAMRB12 BAMRB11 BAMRB10 BAMRB9 BAMRB7 BAMRB6 BARC30 BARC22 BARC14 BARC6 BAMRB5 BARC29 BARC21 BARC13 BARC5 BAMRB4 BARC28 BARC20 BARC12 BARC4 BAMRB3 BARC27 BARC19 BARC11 BARC3 BAMRB2 BARC26 BARC18 BARC10 BARC2 BAMRB1 BARC25 BARC17 BARC9 BARC1
BAMRB8 BAMRB0 BARC24 BARC16 BARC8 BARC0
BARCH
BARC31 BARC23
BARCL
BARC15 BARC7
BAMRCH
BAMRC31 BAMRC30 BAMRC29 BAMRC28 BAMRC27 BAMRC26 BAMRC25 BAMRC24 BAMRC23 BAMRC22 BAMRC21 BAMRC20 BAMRC19 BAMRC18 BAMRC17 BAMRC16
BAMRCL
BAMRC15 BAMRC14 BAMRC13 BAMRC12 BAMRC11 BAMRC10 BAMRC9 BAMRC7 BAMRC6 BARD30 BARD22 BARD14 BARD6 BAMRC5 BARD29 BARD21 BARD13 BARD5 CMFCPA IDA1 CMFCPB IDB1 CMFCPC IDC1 BAMRC4 BARD28 BARD20 BARD12 BARD4 IDA0 IDB0 IDC0 BAMRC3 BARD27 BARD19 BARD11 BARD3 CPA2 RWA1 CPB2 RWB1 CPC2 RWC1 BAMRC2 BARD26 BARD18 BARD10 BARD2 CPA1 RWA0 CPB1 RWB0 CPC1 RWC0 BAMRC1 BARD25 BARD17 BARD9 BARD1 CPA0 CPB0 CPC0
BAMRC8 BAMRC0 BARD24 BARD16 BARD8 BARD0
BARDH
BARD31 BARD23
BARDL
BARD15 BARD7
BRCRA

BRCRB

BRCRC

Rev. 2.00 Sep. 25, 2008 Page 1203 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation BRCRD
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU (unit 1) TPU_6 Module UBC
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 CCLR1 IOB2 IOD2 DMFCPD IDD1 CST5 SYNC5 CCLR0 BFB IOB1 IOD1 * IDD0 CST4 SYNC4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV CPD2 RWD1 CST3 SYNC3 CKEG0 MD3 IOA3 IOC3 TGIED TGFD CPD1 RWD0 CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC CPD0 CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB
TSTRB TSYRB TCR_6 TMDR_6 TIORH_6 TIORL_6 TIER_6 TSR_6 TCNT_6
CCLR2 IOB3 IOD3
TGRA_6
TGRB_6
TGRC_6
TGRD_6
TCR_7 TMDR_7 TIOR_7 TIER_7 TSR_7 TCNT_7
IOB3 TCFD
CCLR1 IOB2
CCLR0 IOB1 TCIEU TCFU
CKEG1 IOB0 TCIEV TCFV
CKEG0 MD3 IOA3
TPSC2 MD2 IOA2
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
TPU_7
TGRA_7
Rev. 2.00 Sep. 25, 2008 Page 1204 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation TGRB_7
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 Module TPU_7
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
TCR_8 TMDR_8 TIOR_8 TIER_8 TSR_8 TCNT_8
IOB3 TCFD
CCLR1 IOB2
CCLR0 IOB1 TCIEU TCFU
CKEG1 IOB0 TCIEV TCFV
CKEG0 MD3 IOA3
TPSC2 MD2 IOA2
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
TPU_8
TGRA_8
TGRB_8
TCR_9 TMDR_9 TIORH_9 TIORL_9 TIER_9 TSR_9 TCNT_9
CCLR2 IOB3 IOD3
CCLR1 IOB2 IOD2
CCLR0 BFB IOB1 IOD1
CKEG1 BFA IOB0 IOD0 TCIEV TCFV
CKEG0 MD3 IOA3 IOC3 TGIED TGFD
TPSC2 MD2 IOA2 IOC2 TGIEC TGFC
TPSC1 MD1 IOA1 IOC1 TGIEB TGFB
TPSC0 MD0 IOA0 IOC0 TGIEA TGFA
TPU_9
TGRA_9
TGRB_9
TGRC_9
TGRD_9
Rev. 2.00 Sep. 25, 2008 Page 1205 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation TCR_10 TMDR_10 TIOR_10 TIER_10 TSR_10 TCNT_10
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 TPSC0 MD0 IOA0 TGIEA TGFA Module TPU_10
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 IOB3 TCFD CCLR1 IOB2 CCLR0 IOB1 TCIEU TCFU CKEG1 IOB0 TCIEV TCFV CKEG0 MD3 IOA3 TPSC2 MD2 IOA2 TPSC1 MD1 IOA1 TGIEB TGFB
TGRA_10
TGRB_10
TCR_11 TMDR_11 TIOR_11 TIER_11 TSR_11 TCNT_11
IOB3 TCFD
CCLR1 IOB2
CCLR0 IOB1 TCIEU TCFU
CKEG1 IOB0 TCIEV TCFV
CKEG0 MD3 IOA3
TPSC2 MD2 IOA2
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
TPU_11
TGRA_11
TGRB_11
P1DDR P2DDR P6DDR PADDR PBDDR PDDDR PEDDR PFDDR
P17DDR P27DDR PA7DDR PD7DDR PE7DDR
P16DDR P26DDR PA6DDR PD6DDR PE6DDR
P15DDR P25DDR P65DDR PA5DDR PD5DDR PE5DDR
P14DDR P24DDR P64DDR PA4DDR PD4DDR PE4DDR PF4DDR
P13DDR P23DDR P63DDR PA3DDR PB3DDR PD3DDR PE3DDR PF3DDR
P12DDR P22DDR P62DDR PA2DDR PB2DDR PD2DDR PE2DDR PF2DDR
P11DDR P21DDR P61DDR PA1DDR PB1DDR PD1DDR PE1DDR PF1DDR
P10DDR P20DDR P60DDR PA0DDR PB0DDR PD0DDR PE0DDR PF0DDR
I/O port
Rev. 2.00 Sep. 25, 2008 Page 1206 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation P1ICR P2ICR P5ICR P6ICR PAICR PBICR PDICR PEICR PFICR PORTH PORTI PORTJ PORTK PHDR PIDR PJDR PKDR PHDDR PIDDR PJDDR PKDDR PHICR PIICR PJICR PKICR PDPCR PEPCR PFPCR PHPCR
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 P10ICR P20ICR P50ICR P60ICR PA0ICR PB0ICR PD0ICR PE0ICR PF0ICR PH0 PI0 PJ0 PK0 PH0DR PI0DR PJ0DR PK0DR PH0DDR PI0DDR PJ0DDR PK0DDR PH0ICR PI0ICR PJ0ICR PK0ICR PD0PCR PE0PCR PF0PCR PH0PCR Module I/O port
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 P17ICR P27ICR P57ICR PA7ICR PD7ICR PE7ICR PH7 PI7 PJ7 PK7 PH7DR PI7DR PJ7DR PK7DR PH7DDR PI7DDR PJ7DDR PK7DDR PH7ICR PI7ICR PJ7ICR PK7ICR PD7PCR PE7PCR PH7PCR P16ICR P26ICR P56ICR PA6ICR PD6ICR PE6ICR PH6 PI6 PJ6 PK6 PH6DR PI6DR PJ6DR PK6DR PH6DDR PI6DDR PJ6DDR PK6DDR PH6ICR PI6ICR PJ6ICR PK6ICR PD6PCR PE6PCR PH6PCR P15ICR P25ICR P55ICR P65ICR PA5ICR PD5ICR PE5ICR PH5 PI5 PJ5 PK5 PH5DR PI5DR PJ5DR PK5DR PH5DDR PI5DDR PJ5DDR PK5DDR PH5ICR PI5ICR PJ5ICR PK5ICR PD5PCR PE5PCR PH5PCR P14ICR P24ICR P54ICR P64ICR PA4ICR PD4ICR PE4ICR PF4ICR PH4 PI4 PJ4 PK4 PH4DR PI4DR PJ4DR PK4DR PH4DDR PI4DDR PJ4DDR PK4DDR PH4ICR PI4ICR PJ4ICR PK4ICR PD4PCR PE4PCR PF4PCR PH4PCR P13ICR P23ICR P53ICR P63ICR PA3ICR PB3ICR PD3ICR PE3ICR PF3ICR PH3 PI3 PJ3 PK3 PH3DR PI3DR PJ3DR PK3DR PH3DDR PI3DDR PJ3DDR PK3DDR PH3ICR PI3ICR PJ3ICR PK3ICR PD3PCR PE3PCR PF3PCR PH3PCR P12ICR P22ICR P52ICR P62ICR PA2ICR PB2ICR PD2ICR PE2ICR PF2ICR PH2 PI2 PJ2 PK2 PH2DR PI2DR PJ2DR PK2DR PH2DDR PI2DDR PJ2DDR PK2DDR PH2ICR PI2ICR PJ2ICR PK2ICR PD2PCR PE2PCR PF2PCR PH2PCR P11ICR P21ICR P51ICR P61ICR PA1ICR PB1ICR PD1ICR PE1ICR PF1ICR PH1 PI1 PJ1 PK1 PH1DR PI1DR PJ1DR PK1DR PH1DDR PI1DDR PJ1DDR PK1DDR PH1ICR PI1ICR PJ1ICR PK1ICR PD1PCR PE1PCR PF1PCR PH1PCR
Rev. 2.00 Sep. 25, 2008 Page 1207 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation PIPCR PJPCR PKPCR P2ODR PFODR PFCR0 PFCR1 PFCR2 PFCR4 PFCR6 PFCR7 PFCR8 PFCR9 PFCRA PFCRB PFCRC PFCRD SSIER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 PI0PCR PJ0PCR PK0PCR P20ODR PF0ODR CS0E A16E DMAS0B Module I/O port
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 PI7PCR PJ7PCR PK7PCR P27ODR CS7E CS7SA DMAS3A TPUMS5 PI6PCR PJ6PCR PK6PCR P26ODR CS6E CS7SB CS2S LHWROE DMAS3B TPUMS4 PI5PCR PJ5PCR PK5PCR P25ODR CS5E CS6SA BSS DMAS2A PI4PCR PJ4PCR PK4PCR P24ODR PF4ODR CS4E CS6SB BSE A20E DMAS2B PI3PCR PJ3PCR PK3PCR P23ODR PF3ODR CS3E CS5SA A19E TCLKS DMAS1A PI2PCR PJ2PCR PK2PCR P22ODR PF2ODR CS2E CS5SB RDWRE A18E DMAS1B PI1PCR PJ1PCR PK1PCR P21ODR PF1ODR CS1E ASOE A17E DMAS0A
EDMAS1A EDMAS1B EDMAS0A EDMAS0B TPUMS7 ITS10 ITS2 SSI10 SSI2 DKUP02 DKUP12 DKUP22 DKUP32 DKUP42 DKUP52 DKUP62 DKUP72 DKUP82 DKUP92 DKUP102
TPUMS3A TPUMS3B
TPUMS11 TPUMS10 TPUMS9A TPUMS9B TPUMS8 ITS7 PCJKE SSI7 ITS14 ITS6 SSI6 DKUP06 DKUP16 DKUP26 DKUP36 DKUP46 DKUP56 DKUP66 DKUP76 DKUP86 DKUP96 DKUP106 ITS5 SSI5 DKUP05 DKUP15 DKUP25 DKUP35 DKUP45 DKUP55 DKUP65 DKUP75 DKUP85 DKUP95 DKUP105 ITS4 SSI4 DKUP04 DKUP14 DKUP24 DKUP34 DKUP44 DKUP54 DKUP64 DKUP74 DKUP84 DKUP94 DKUP104 ITS11 ITS3 SSI11 SSI3 DKUP03 DKUP13 DKUP23 DKUP33 DKUP43 DKUP53 DKUP63 DKUP73 DKUP83 DKUP93 DKUP103
TPUMS6A TPUMS6B ITS9 ITS1 SSI9 SSI1 DKUP01 DKUP11 DKUP21 DKUP31 DKUP41 DKUP51 DKUP61 DKUP71 DKUP81 DKUP91 DKUP101 ITS8 ITS0 SSI8 SSI0 DKUP00 DKUP10 DKUP20 DKUP30 DKUP40 DKUP50 DKUP60 DKUP70 DKUP80 DKUP90 DKUP100 SYSTEM INTC
DPSBKR0 DPSBKR1 DPSBKR2 DPSBKR3 DPSBKR4 DPSBKR5 DPSBKR6 DPSBKR7 DPSBKR8 DPSBKR9 DPSBKR10
DKUP07 DKUP17 DKUP27 DKUP37 DKUP47 DKUP57 DKUP67 DKUP77 DKUP87 DKUP97 DKUP107
Rev. 2.00 Sep. 25, 2008 Page 1208 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation DPSBKR11 DPSBKR12 DPSBKR13 DPSBKR14 DPSBKR15 DSAR_0
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 DKUP110 DKUP120 DKUP130 DKUP140 DKUP150 DMAC_0 Module SYSTEM
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 DKUP117 DKUP127 DKUP137 DKUP147 DKUP157 DKUP116 DKUP126 DKUP136 DKUP146 DKUP156 DKUP115 DKUP125 DKUP135 DKUP145 DKUP155 DKUP114 DKUP124 DKUP134 DKUP144 DKUP154 DKUP113 DKUP123 DKUP133 DKUP143 DKUP153 DKUP112 DKUP122 DKUP132 DKUP142 DKUP152 DKUP111 DKUP121 DKUP131 DKUP141 DKUP151
DDAR_0
DOFR_0
DTCR_0
DBSR_0
BKSZH31 BKSZH23 BKSZ15 BKSZ7
BKSZH30 BKSZH22 BKSZ14 BKSZ6 DACKE DTSZ0 DTF0
BKSZH29 BKSZH21 BKSZ13 BKSZ5 TENDE MDS1 DTA
BKSZH28 BKSZH20 BKSZ12 BKSZ4 MDS0
BKSZH27 BKSZH19 BKSZ11 BKSZ3 DREQS ERRF TSEIE
BKSZH26 BKSZH18 BKSZ10 BKSZ2 NRD DMAP2
BKSZH25 BKSZH17 BKSZ9 BKSZ1 ESIF ESIE DMAP1
BKSZH24 BKSZH16 BKSZ8 BKSZ0 DTIF DTIE DMAP0
DMDR_0
DTE ACT DTSZ1 DTF1
Rev. 2.00 Sep. 25, 2008 Page 1209 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation DACR_0
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 ARS0 DAT0 SARA0 DARA0 DMAC_1 Module DMAC_0
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 AMS SARIE DARIE DIRS SAT1 SAT0 SARA4 DARA4 SARA3 DARA3 RPTIE SARA2 DARA2 ARS1 DAT1 SARA1 DARA1
DSAR_1
DDAR_1
DOFR_1
DTCR_1
DBSR_1
BKSZH31 BKSZH23 BKSZ15 BKSZ7
BKSZH30 BKSZH22 BKSZ14 BKSZ6 DACKE DTSZ0 DTF0
BKSZH29 BKSZH21 BKSZ13 BKSZ5 TENDE MDS1 DTA
BKSZH28 BKSZH20 BKSZ12 BKSZ4 MDS0
BKSZH27 BKSZH19 BKSZ11 BKSZ3 DREQS TSEIE
BKSZH26 BKSZH18 BKSZ10 BKSZ2 NRD DMAP2
BKSZH25 BKSZH17 BKSZ9 BKSZ1 ESIF ESIE DMAP1
BKSZH24 BKSZH16 BKSZ8 BKSZ0 DTIF DTIE DMAP0
DMDR_1
DTE ACT DTSZ1 DTF1
Rev. 2.00 Sep. 25, 2008 Page 1210 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation DACR_1
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 ARS0 DAT0 SARA0 DARA0 DMAC_2 Module DMAC_1
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 AMS SARIE DARIE DIRS SAT1 SAT0 SARA4 DARA4 SARA3 DARA3 RPTIE SARA2 DARA2 ARS1 DAT1 SARA1 DARA1
DSAR_2
DDAR_2
DOFR_2
DTCR_2
DBSR_2
BKSZH31 BKSZH23 BKSZ15 BKSZ7
BKSZH30 BKSZH22 BKSZ14 BKSZ6 DACKE DTSZ0 DTF0
BKSZH29 BKSZH21 BKSZ13 BKSZ5 TENDE MDS1 DTA
BKSZH28 BKSZH20 BKSZ12 BKSZ4 MDS0
BKSZH27 BKSZH19 BKSZ11 BKSZ3 DREQS TSEIE
BKSZH26 BKSZH18 BKSZ10 BKSZ2 NRD DMAP2
BKSZH25 BKSZH17 BKSZ9 BKSZ1 ESIF ESIE DMAP1
BKSZH24 BKSZH16 BKSZ8 BKSZ0 DTIF DTIE DMAP0
DMDR_2
DTE ACT DTSZ1 DTF1
Rev. 2.00 Sep. 25, 2008 Page 1211 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation DACR_2
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 ARS0 DAT0 SARA0 DARA0 DMAC_3 Module DMAC_2
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 AMS SARIE DARIE DIRS SAT1 SAT0 SARA4 DARA4 SARA3 DARA3 RPTIE SARA2 DARA2 ARS1 DAT1 SARA1 DARA1
DSAR_3
DDAR_3
DOFR_3
DTCR_3
DBSR_3
BKSZH31 BKSZH23 BKSZ15 BKSZ7
BKSZH30 BKSZH22 BKSZ14 BKSZ6 DACKE DTSZ0 DTF0
BKSZH29 BKSZH21 BKSZ13 BKSZ5 TENDE MDS1 DTA
BKSZH28 BKSZH20 BKSZ12 BKSZ4 MDS0
BKSZH27 BKSZH19 BKSZ11 BKSZ3 DREQS TSEIE
BKSZH26 BKSZH18 BKSZ10 BKSZ2 NRD DMAP2
BKSZH25 BKSZH17 BKSZ9 BKSZ1 ESIF ESIE DMAP1
BKSZH24 BKSZH16 BKSZ8 BKSZ0 DTIF DTIE DMAP0
DMDR_3
DTE ACT DTSZ1 DTF1
Rev. 2.00 Sep. 25, 2008 Page 1212 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation DACR_3
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 ARS0 DAT0 SARA0 DARA0 EXDMAC_ 0 Module DMAC_3
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 AMS SARIE DARIE DIRS SAT1 SAT0 SARA4 DARA4 SARA3 DARA3 RPTIE SARA2 DARA2 ARS1 DAT1 SARA1 DARA1
EDSAR_0
EDDAR_0
EDOFR_0
EDTCR_0
EDBSR_0
BKSZH31 BKSZH23 BKSZ15 BKSZ7
BKSZH30 BKSZH22 BKSZ14 BKSZ6 EDACKE DTSZ0 DTF0
BKSZH29 BKSZH21 BKSZ13 BKSZ5 ETENDE MDS1
BKSZH28 BKSZH20 BKSZ12 BKSZ4 EDRAKE MDS0
BKSZH27 BKSZH19 BKSZ11 BKSZ3 EDREQS ERRF TSEIE
BKSZH26 BKSZH18 BKSZ10 BKSZ2 NRD EDMAP2
BKSZH25 BKSZH17 BKSZ9 BKSZ1 ESIF ESIE DEMAP1
BKSZH24 BKSZH16 BKSZ8 BKSZ0 DTIF DTIE EDMAP0
EDMDR_0
DTE ACT DTSZ1 DTF1
Rev. 2.00 Sep. 25, 2008 Page 1213 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation EDACR_0
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 ARS0 DAT0 SARA0 DARA0 EXDMAC_ 1 Module EXDMAC_ 0
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 AMS SARIE DARIE DIRS SAT1 SAT0 SARA4 DARA4 SARA3 DARA3 RPTIE SARA2 DARA2 ARS1 DAT1 SARA1 DARA1
EDSAR_1
EDDAR_1
EDOFR_1
EDTCR_1
EDBSR_1
BKSZH31 BKSZH23 BKSZ15 BKSZ7
BKSZH30 BKSZH22 BKSZ14 BKSZ6 EDACKE DTSZ0 DTF0
BKSZH29 BKSZH21 BKSZ13 BKSZ5 ETENDE MDS1
BKSZH28 BKSZH20 BKSZ12 BKSZ4 EDRAKE MDS0
BKSZH27 BKSZH19 BKSZ11 BKSZ3 EDREQS TSEIE
BKSZH26 BKSZH18 BKSZ10 BKSZ2 NRD EDMAP2
BKSZH25 BKSZH17 BKSZ9 BKSZ1 ESIF ESIE DEMAP1
BKSZH24 BKSZH16 BKSZ8 BKSZ0 DTIF DTIE EDMAP0
EDMDR_1
DTE ACT DTSZ1 DTF1
Rev. 2.00 Sep. 25, 2008 Page 1214 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation EDACR_1
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 ARS0 DAT0 SARA0 DARA0 EXDMAC_ 2 Module EXDMAC_ 1
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 AMS SARIE DARIE DIRS SAT1 SAT0 SARA4 DARA4 SARA3 DARA3 RPTIE SARA2 DARA2 ARS1 DAT1 SARA1 DARA1
EDSAR_2
EDDAR_2
EDOFR_2
EDTCR_2
EDBSR_2
BKSZH31 BKSZH23 BKSZ15 BKSZ7
BKSZH30 BKSZH22 BKSZ14 BKSZ6 EDACKE DTSZ0 DTF0
BKSZH29 BKSZH21 BKSZ13 BKSZ5 ETENDE MDS1
BKSZH28 BKSZH20 BKSZ12 BKSZ4 EDRAKE MDS0
BKSZH27 BKSZH19 BKSZ11 BKSZ3 EDREQS TSEIE
BKSZH26 BKSZH18 BKSZ10 BKSZ2 NRD EDMAP2
BKSZH25 BKSZH17 BKSZ9 BKSZ1 ESIF ESIE DEMAP1
BKSZH24 BKSZH16 BKSZ8 BKSZ0 DTIF DTIE EDMAP0
EDMDR_2
DTE ACT DTSZ1 DTF1
Rev. 2.00 Sep. 25, 2008 Page 1215 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation EDACR_2
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 ARS0 DAT0 SARA0 DARA0 EXDMAC_ 3 Module EXDMAC_ 2
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 AMS SARIE DARIE DIRS SAT1 SAT0 SARA4 DARA4 SARA3 DARA3 RPTIE SARA2 DARA2 ARS1 DAT1 SARA1 DARA1
EDSAR_3
EDDAR_3
EDOFR_3
EDTCR_3
EDBSR_3
BKSZH31 BKSZH23 BKSZ15 BKSZ7
BKSZH30 BKSZH22 BKSZ14 BKSZ6 EDACKE DTSZ0 DTF0
BKSZH29 BKSZH21 BKSZ13 BKSZ5 ETENDE MDS1
BKSZH28 BKSZH20 BKSZ12 BKSZ4 EDRAKE MDS0
BKSZH27 BKSZH19 BKSZ11 BKSZ3 EDREQS TSEIE
BKSZH26 BKSZH18 BKSZ10 BKSZ2 NRD EDMAP2
BKSZH25 BKSZH17 BKSZ9 BKSZ1 ESIF ESIE DEMAP1
BKSZH24 BKSZH16 BKSZ8 BKSZ0 DTIF DTIE EDMAP0
EDMDR_3
DTE ACT DTSZ1 DTF1
Rev. 2.00 Sep. 25, 2008 Page 1216 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation EDACR_3
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 ARS0 DAT0 SARA0 DARA0 EXDMAC Module EXDMAC_ 3
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 AMS SARIE DARIE DIRS SAT1 SAT0 SARA4 DARA4 SARA3 DARA3 RPTIE SARA2 DARA2 ARS1 DAT1 SARA1 DARA1
CLSBR0
CLSBR1
CLSBR2
CLSBR3
CLSBR4
CLSBR5
Rev. 2.00 Sep. 25, 2008 Page 1217 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation CLSBR6
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 Module EXDMAC
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
CLSBR7
DMRSR_0 DMRSR_1 DMRSR_2 DMRSR_3 IPRA IPRB IPRC IPRE IPRF IPRG IPRH IPRI IPRJ IPRA14 IPRA6 IPRB14 IPRB6 IPRC14 IPRC6 IPRF6 IPRG14 IPRG6 IPRH14 IPRH6 IPRI14 IPRI6 IPRIJ4 IPRJ6 IPRA13 IPRA5 IPRB13 IPRB5 IPRC13 IPRC5 IPRF5 IPRG13 IPRG5 IPRH13 IPRH5 IPRI13 IPRI5 IPRJ13 IPRJ5 IPRA12 IPRA4 IPRB12 IPRB4 IPRC12 IPRC4 IPRF4 IPRG12 IPRG4 IPRH12 IPRH4 IPRI12 IPRI4 IPRJ12 IPRJ4 IPRA10 IPRA2 IPRB10 IPRB2 IPRC10 IPRC2 IPRE10 IPRF10 IPRF2 IPRG10 IPRG2 IPRH10 IPRH2 IPRI10 IPRI2 IPRJ10 IPRJ2 IPRA9 IPRA1 IPRB9 IPRB1 IPRC9 IPRC1 IPRE9 IPRF9 IPRF1 IPRG9 IPRG1 IPRH9 IPRH1 IPRI9 IPRI1 IPRJ9 IPRJ1 IPRA8 IPRA0 IPRB8 IPRB0 IPRC8 IPRC0 IPRE8 IPRF8 IPRF0 IPRG8 IPRG0 IPRH8 IPRH0 IPRI8 IPRI0 IPRJ8 IPRJ0
DMAC_0 DMAC_1 DMAC_2 DMAC_3 INTC
Rev. 2.00 Sep. 25, 2008 Page 1218 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation IPRK
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 IPRK8 IPRK0 IPRL0 IPRM8 IPRM0 IPRN8 IPRN0 IPRO8 IPRQ0 IPRR8 IPRR0 IRQ8SF IRQ4SF IRQ0SF BSC Module INTC
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 IPRK14 IPRK6 IPRL14 IPRL6 IPRM14 IPRM6 IPRN14 IPRN6 IPRO14 IPRO6 IPRQ6 IPRR14 IPRR6 IRQ11SF IRQ7SF IRQ3SF IPRK13 IPRK5 IPRL13 IPRL5 IPRM13 IPRM5 IPRN13 IPRN5 IPRO13 IPRO5 IPRQ5 IPRR13 IPRR5 IRQ14SR IRQ10SR IRQ6SR IRQ2SR IPRK12 IPRK4 IPRL12 IPRL4 IPRM12 IPRM4 IPRN12 IPRN4 IPRO12 IPRO4 IPRQ4 IPRR12 IPRR4 IRQ14SF IRQ10SF IRQ6SF IRQ2SF IRQ9SR IRQ5SR IRQ1SR IPRK10 IPRK2 IPRL2 IPRM10 IPRM2 IPRN10 IPRN2 IPRO10 IPRQ2 IPRR10 IPRR2 IRQ9SF IRQ5SF IRQ1SF IPRK9 IPRK1 IPRL1 IPRM9 IPRM1 IPRN9 IPRN1 IPRO9 IPRQ1 IPRR9 IPRR1 IRQ8SR IRQ4SR IRQ0SR
IPRL

IPRM

IPRN

IPRO

IPRQ

IPRR

ISCRH
IRQ11SR
ISCRL
IRQ7SR IRQ3SR
DTCVBR
ABWCR
ABWH7 ABWL7
ABWH6 ABWL6 AST6 W72 W52 W32 W12
ABWH5 ABWL5 AST5 W71 W51 W31 W11
ABWH4 ABWL4 AST4 W70 W50 W30 W10
ABWH3 ABWL3 AST3
ABWH2 ABWL2 AST2 W62 W42 W22 W02
ABWH1 ABWL1 AST1 W61 W41 W21 W01
ABWH0 ABWL0 AST0 W60 W40 W20 W00
ASTCR
AST7
WTCRA

WTCRB

Rev. 2.00 Sep. 25, 2008 Page 1219 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation RDNCR
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 RDN0 CSXH0 CSXT0 IDLCA0 IDLSEL0 WAITE PWDBE BCSEL0 BSWD00 BSWD10 ADDEX RAM0 MDS0 RAME ICK0 BCK0 STS0 MSTPA8 MSTPA0 MSTPB8 MSTPB0 SYSTEM Module BSC
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 RDN7 RDN6 CSXH6 CSXT6 IDLS2 IDLSEL6 BREQOE LE6 BCSEL6 BSTS02 BSTS12 MPXE6 PCK2 OPE RDN5 CSXH5 CSXT5 IDLS1 IDLSEL5 EBCCS LE5 BCSEL5 BSTS01 BSTS11 MPXE5 MACS PCK1 RDN4 CSXH4 CSXT4 IDLS0 IDLSEL4 IBCCS LE4 BCSEL4 BSTS00 BSTS10 MPXE4 PCK0 STS4 RDN3 CSXH3 CSXT3 IDLCB1 IDLSEL3 LE3 BCSEL3 MPXE3 RAMS MDS3 RDN2 CSXH2 CSXT2 IDLCB0 IDLSEL2 LE2 BCSEL2 RAM2 MDS2 RDN1 CSXH1 CSXT1 IDLCA1 IDLSEL1 WDBE BCSEL1 BSWD01 BSWD11 RAM1 MDS1 EXPE DTCMD ICK1 BCK1 STS1
CSACR
CSXH7 CSXT7
IDLCR
IDLS3 IDLSEL7
BCR1
BRLE DKC
BCR2 ENDIANCR SRAMCR
LE7 BCSEL7
BROMCR
BSRM0 BSRM1
MPXCR
MPXE7
RAMER MDCR

SYSCR

FETCHMD STS3 ICK2 BCK2 STS2
SCKCR
PSTOP1
SBYCR
SSBY SLPIE
MSTPCRA
ACSE MSTPA7
MSTPA14 MSTPA13 MSTPA12 MSTPA11 MSTPA10 MSTPA9 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1
MSTPCRB
MSTPB15 MSTPB14 MSTPB13 MSTPB12 MSTPB11 MSTPB10 MSTPB9 MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1
Rev. 2.00 Sep. 25, 2008 Page 1220 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation MSTPCRC
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 MSTPC8 MSTPC0 SCO PPVS EPVB K0 MS0 TDA0 RAMCUT0 SYSTEM WTSTS0 DIRQ0E DIRQ0F DIRQ0EG FLASH Module SYSTEM
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 MSTPC15 MSTPC14 MSTPC13 MSTPC12 MSTPC11 MSTPC10 MSTPC9 MSTPC7 MSTPC6 K6 MS6 TDA6 IOKEEP DUSBIE DUSBIF DUSBIEG MSTPC5 K5 MS5 TDA5 MSTPC4 FLER K4 MS4 TDA4 MSTPC3 K3 MS3 TDA3 MSTPC2 K2 MS2 TDA2 WTSTS2 DIRQ2E DIRQ2F DIRQ2EG MSTPC1 K1 MS1 TDA1 WTSTS1 DIRQ1E DIRQ1F DIRQ1EG
FCCS FPCS FECS FKEY FMATS FTDAR DPSBYCR DPSWCR DPSIER DPSIFR DPSIEGR RSTSR LVDCR*
3
K7 MS7 TDER DPSBY DNMIF DNMIEG
RAMCUT2 RAMCUT1 WTSTS5 WTSTS4 LVDMON PE (PE) O/E (O/E) ABCS STOP (BCP1) WTSTS3 DIRQ3E DIRQ3F DIRQ3EG
DPSRSTF LVDE C/A (GM) LVDRI CHR (BLK)
SEMR_2 SMR_4*1
ACS2 MP (BCP0)
ACS1 CKS1
ACS0 CKS0
SCI_2 SCI_4
BRR_4 SCR_4*1 TDR_4 SSR_4*1 TDRE RDRF ORER FER (ERS) RDR_4 SCMR_4 ICCRA_0 ICCRB_0 ICMR_0 ICIER_0 ICSR_0 SAR_0 ICE BBSY TIE TDRE SVA6 RCVD SCP WAIT TEIE TEND SVA5 MST SDAO RIE RDRF SVA4 TRS NAKIE NACKF SVA3 SDIR CKS3 SCLO BCWP STIE STOP SVA2 SINV CKS2 BC2 ACKE AL SVA1 CKS1 IICRST BC1 ACKBR AAS SVA0 SMIF CKS0 BC0 ACKBT ADZ IIC2_0 PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0
Rev. 2.00 Sep. 25, 2008 Page 1221 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation ICDRT_0 ICDRR_0 ICCRA_1 ICCRB_1 ICMR_1 ICIER_1 ICSR_1 SAR_1 ICDRT_1 ICDRR_1 TCR_2 TCR_3 TCSR_2 TCSR_3 TCORA_2 TCORA_3 TCORB_2 TCORB_3 TCNT_2 TCNT_3 TCCR_2 TCCR_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4 TCNT_4
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 Module IIC2_0
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
ICE BBSY TIE TDRE SVA6
RCVD SCP WAIT TEIE TEND SVA5
MST SDAO RIE RDRF SVA4
TRS NAKIE NACKF SVA3
CKS3 SCLO BCWP STIE STOP SVA2
CKS2 BC2 ACKE AL SVA1
CKS1 IICRST BC1 ACKBR AAS SVA0
CKS0 BC0 ACKBT ADZ
IIC2_1
CMIEB CMIEB CMFB CMFB
CMIEA CMIEA CMFA CMFA
OVIE OVIE OVF OVF
CCLR1 CCLR1 ADTE
CCLR0 CCLR0 OS3 OS3
CKS2 CKS2 OS2 OS2
CKS1 CKS1 OS1 OS1
CKS0 CKS0 OS0 OS0
TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3
IOB3 TTGE TCFD
CCLR1 IOB2
CCLR0 IOB1 TCIEU TCFU
CKEG1 IOB0 TCIEV TCFV
TMRIS TMRIS CKEG0 MD3 IOA3
TPSC2 MD2 IOA2
ICKS1 ICKS1 TPSC1 MD1 IOA1 TGIEB TGFB
ICKS0 ICKS0 TPSC0 MD0 IOA0 TGIEA TGFA
TMR_2 TMR_3 TPU_4
Rev. 2.00 Sep. 25, 2008 Page 1222 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation TGRA_4
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 Module TPU_4
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
TGRB_4
TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5
IOB3 TTGE TCFD
CCLR1 IOB2
CCLR0 IOB1 TCIEU TCFU
CKEG1 IOB0 TCIEV TCFV
CKEG0 MD3 IOA3
TPSC2 MD2 IOA2
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
TPU_5
TGRA_5
TGRB_5
DTCERA
DTCEA15 DTCEA7
DTCEA14 DTCEA6 DTCEB6 DTCEC14 DTCEC6 DTCED14 DTCED6 DTCEE6 DTCEF14 DTCP2
DTCEA13 DTCEA5 DTCEB13 DTCEB5 DTCEC13 DTCEC5 DTCED13 DTCED5 DTCEE13 DTCEE5 INTM1 DTCP1
DTCEA12 DTCEA4 DTCEB12 DTCEB4
DTCEA11 DTCEB11 DTCEB3
DTCEA10 DTCEB10 DTCEB2 DTCEC10 DTCEC2 DTCED10 DTCED2 DTCEE10 DTCEE2 DTCEF10 CPUP2
DTCEA9 DTCEB9 DTCEB1 DTCEC9 DTCEC1 DTCED9 DTCED1 DTCEE9 DTCEE1 DTCEF9 CPUP1
DTCEA8 DTCEB8 DTCEB0 DTCEC8 DTCEC0 DTCED8 DTCED0 DTCEE8 DTCEE0 ERR CPUP0
INTC
DTCERB
DTCEB15 DTCEB7
DTCERC
DTCEC15 DTCEC7
DTCEC12 DTCEC11 DTCEC4 DTCEC3
DTCERD
DTCED15 DTCED7
DTCED12 DTCED11 DTCED4 DTCEE12 DTCEE4 RRS INTM0 DTCP0 DTCED3 DTCEE11 DTCEE3 DTCEF11 RCHNE NMIEG IPSETE
DTCERE
DTCEE7
INTC
DTCERF
DTCEF15
DTCCR INTCR CPUPCR
CPUPCE
Rev. 2.00 Sep. 25, 2008 Page 1223 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation IER
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 IRQ8E IRQ0E IRQ8F IRQ0F P10 P20 P50 P60 PA0 PB0 PD0 PE0 PF0 P10DR P20DR P60DR PA0DR PB0DR PD0DR PE0DR PF0DR CKS0 SCI_2 I/O port Module INTC
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 IRQ7E IRQ14E IRQ6E IRQ14F IRQ6F P16 P26 P56 PA6 PD6 PE6 P16DR P26DR PA6DR PD6DR PE6DR CHR (BLK) IRQ5E IRQ5F P15 P25 P55 P65 PA5 PD5 PE5 P15DR P25DR P65DR PA5DR PD5DR PE5DR PE (PE) IRQ4E IRQ4F P14 P24 P54 P64 PA4 PD4 PE4 PF4 P14DR P24DR P64DR PA4DR PD4DR PE4DR PF4DR O/E (O/E) IRQ11E IRQ3E IRQ11F IRQ3F P13 P23 P53 P63 PA3 PB3 PD3 PE3 PF3 P13DR P23DR P63DR PA3DR PB3DR PD3DR PE3DR PF3DR STOP (BCP1) IRQ10E IRQ2E IRQ10F IRQ2F P12 P22 P52 P62 PA2 PB2 PD2 PE2 PF2 P12DR P22DR P62DR PA2DR PB2DR PD2DR PE2DR PF2DR MP (BCP0) IRQ9E IRQ1E IRQ9F IRQ1F P11 P21 P51 P61 PA1 PB1 PD1 PE1 PF1 P11DR P21DR P61DR PA1DR PB1DR PD1DR PE1DR PF1DR CKS1
ISR
IRQ7F
PORT1 PORT2 PORT5 PORT6 PORTA PORTB PORTD PORTE PORTF P1DR P2DR P6DR PADR PBDR PDDR PEDR PFDR SMR_2*
1
P17 P27 P57 PA7 PD7 PE7 P17DR P27DR PA7DR PD7DR PE7DR C/A (GM)
BRR_2 SCR_2*1 TDR_2 SSR_2*1 TDRE RDRF ORER FER (ERS) RDR_2 SCMR_2 SDIR SINV SMIF PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0
Rev. 2.00 Sep. 25, 2008 Page 1224 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation DADR0 DADR1 DACR01 PCR PMR NDERH NDERL PODRH PODRL NDRH* NDRL*
2
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 Module D/A
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
DAOE1 G3CMS1 G3INV NDER15 NDER7 POD15 POD7 NDR15 NDR7
DAOE0 G3CMS0 G2INV NDER14 NDER6 POD14 POD6 NDR14 NDR6 CHR (BLK)
DAE G2CMS1 G1INV NDER13 NDER5 POD13 POD5 NDR13 NDR5 PE (PE)
G2CMS0 G0INV NDER12 NDER4 POD12 POD4 NDR12 NDR4 O/E (O/E)
G1CMS1 G3NOV NDER11 NDER3 POD11 POD3 NDR11 NDR3 NDR11 NDR3 STOP (BCP1)
G1CMS0 G2NOV NDER10 NDER2 POD10 POD2 NDR10 NDR2 NDR10 NDR2 MP (BCP0)
G0CMS1 G1NOV NDER9 NDER1 POD9 POD1 NDR9 NDR1 NDR9 NDR1 CKS1
G0CMS0 G0NOV NDER8 NDER0 POD8 POD0 NDR8 NDR0 NDR8 NDR0 CKS0 SCI_0 PPG_0
2
NDRH* NDRL*
2
2
SMR_0*
1
C/A (GM)
BRR_0 SCR_0*1 TDR_0 SSR_0*1 TDRE RDRF ORER FER (ERS) RDR_0 SCMR_0 SMR_1*
1
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
PER
TEND
MPB
MPBT
C/A (GM)
CHR (BLK)
PE (PE)
O/E (O/E)
SDIR STOP (BCP1)
SINV MP (BCP0)
CKS1
SMIF CKS0 SCI_1
BRR_1 SCR_1*1 TDR_1 SSR_1*1 TDRE RDRF ORER FER (ERS) RDR_1 SCMR_1 SDIR SINV SMIF PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0
Rev. 2.00 Sep. 25, 2008 Page 1225 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation ADDRA_0
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 Module A/D_0
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
ADDRB_0
ADDRC_0
ADDRD_0
ADDRE_0
ADDRF_0
ADDRG_0
ADDRH_0
ADCSR_0 ADCR_0 TCSR TCNT RSTCSR TCR_0 TCR_1 TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0
ADF TRGS1 OVF
ADIE TRGS0 WT/IT
ADST SCANE TME
SCANS
CH3 CKS1
CH2 CKS0 CKS2
CH1 CKS1
CH0 EXTRGS CKS0 WDT
WOVF CMIEB CMIEB CMFB CMFB
RSTE CMIEA CMIEA CMFA CMFA
OVIE OVIE OVF OVF
CCLR1 CCLR1 ADTE
CCLR0 CCLR0 OS3 OS3
CKS2 CKS2 OS2 OS2
CKS1 CKS1 OS1 OS1
CKS0 CKS0 OS0 OS0 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0
Rev. 2.00 Sep. 25, 2008 Page 1226 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation TCNT_1 TCCR_0 TCCR_1 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 Module TMR_1
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
CCLR2 IOB3 IOD3 TTGE
CCLR1 IOB2 IOD2
CST5 SYNC5 CCLR0 BFB IOB1 IOD1
CST4 SYNC4 CKEG1 BFA IOB0 IOD0 TCIEV TCFV
TMRIS TMRIS CST3 SYNC3 CKEG0 MD3 IOA3 IOC3 TGIED TGFD
CST2 SYNC2 TPSC2 MD2 IOA2 IOC2 TGIEC TGFC
ICKS1 ICKS1 CST1 SYNC1 TPSC1 MD1 IOA1 IOC1 TGIEB TGFB
ICKS0 ICKS0 CST0 SYNC0 TPSC0 MD0 IOA0 IOC0 TGIEA TGFA
TMR_0 TMR_1 TPU
TPU_0
TGRA_0
TGRB_0
TGRC_0
TGRD_0
TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1
IOB3 TTGE TCFD
CCLR1 IOB2
CCLR0 IOB1 TCIEU TCFU
CKEG1 IOB0 TCIEV TCFV
CKEG0 MD3 IOA3
TPSC2 MD2 IOA2
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
TPU_1
TGRA_1
Rev. 2.00 Sep. 25, 2008 Page 1227 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation TGRB_1
Bit
Bit
Bit
Bit
Bit
Bit
Bit
Bit 24/16/8/0 Module TPU_1
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1
TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2
IOB3 TTGE TCFD
CCLR1 IOB2
CCLR0 IOB1 TCIEU TCFU
CKEG1 IOB0 TCIEV TCFV
CKEG0 MD3 IOA3
TPSC2 MD2 IOA2
TPSC1 MD1 IOA1 TGIEB TGFB
TPSC0 MD0 IOA0 TGIEA TGFA
TPU_2
TGRA_2
TGRB_2
TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3
CCLR2 IOB3 IOD3 TTGE
CCLR1 IOB2 IOD2
CCLR0 BFB IOB1 IOD1
CKEG1 BFA IOB0 IOD0 TCIEV TCFV
CKEG0 MD3 IOA3 IOC3 TGIED TGFD
TPSC2 MD2 IOA2 IOC2 TGIEC TGFC
TPSC1 MD1 IOA1 IOC1 TGIEB TGFB
TPSC0 MD0 IOA0 IOC0 TGIEA TGFA
TPU_3
TGRA_3
TGRB_3
TGRC_3
TGRD_3
Rev. 2.00 Sep. 25, 2008 Page 1228 of 1340 REJ09B0413-0200
Section 28 List of Registers
Notes: 1. Parts of the bit functions differ in normal mode and the smart card interface. 2. When the same output trigger is specified for pulse output groups 2 and 3 by the PCR setting, the NDRH address is H'FFF7C. When different output triggers are specified, the NDRH addresses for pulse output groups 2 and 3 are H'FFF7E and H'FFF7C, respectively. Similarly, when the same output trigger is specified for pulse output groups 0 and 1 by the PCR setting, the NDRL address is H'FFF7D. When different output triggers are specified, the NDRL addresses for pulse output groups 0 and 1 are H'FFF7F and H'FFF7D, respectively. When the same output trigger is specified for pulse output groups 6 and 7 by the PCR setting, the NDRH address is H'FF63C. When different output triggers are specified, the NDRH addresses for pulse output groups 6 and 7 are H'FF63E and H'FF63C, respectively. When the same output trigger is specified for pulse output groups 4 and 5 by the PCR setting, the NDRL address is H'FF63D. When different output triggers are specified, the NDRL addresses for pulse output groups 4 and 5 are H'FF63F and H'FF63D, respectively. 3. Supported only by the H8SX/1658M Group.
Rev. 2.00 Sep. 25, 2008 Page 1229 of 1340 REJ09B0413-0200
Section 28 List of Registers
28.3
Register States in Each Operating Mode
Module Stop State Sleep AllSoftware ModuleClock-Stop Standby Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Register Abbreviation TCR_4 TCR_5 TCSR_4 TCSR_5 TCORA_4 TCORA_5 TCORB_4 TCORB_5 TCNT_4 TCNT_5 TCCR_4 TCCR_5 CRCCR CRCDIR CRCDOR TCR_6 TCR_7 TCSR_6 TCSR_7 TCORA_6 TCORA_7 TCORB_6 TCORB_7 TCNT_6 TCNT_7 TCCR_6 TCCR_7
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 TMR_4 TMR_5 CRC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7 TMR_6 TMR_7
1
1
1
1
1
1
1
1
1
1
1
Rev. 2.00 Sep. 25, 2008 Page 1230 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_1 ADCR_1 IFR0 IFR1 IFR2 IER0 IER1 IER2 ISR0 ISR1 ISR2 EPDR0i EPDR0o EPDR0s EPDR1 EPDR2 EPDR3 EPSZ0o EPSZ1 DASTS FCLR
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module A/D_1
1
1
1
1
1
1
1
1
1
2
USB
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
Rev. 2.00 Sep. 25, 2008 Page 1231 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation EPSTL TRG DMA CVR CTLR EPIR TRNTREG0 TRNTREG1 PMDDR PMDR PORTM PMICR SMR_5 BRR_5 SCR_5 TDR_5 SSR_5 RDR_5 SCMR_5 SEMR_5 IrCR SMR_6 BRR_6 SCR_6 TDR_6 SSR_6 RDR_6 SCMR_6 SEMR_6
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep Initialized Initialized Initialized Initialized Initialized Initialized
AllSoftware ModuleClock-Stop Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1 2
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module USB
2
2
2
2
2
2
2
1
I/O port
1
1
SCI_5
1
1
1
1
1
1
1
1
1
SCI_6
1
1
1
1
1
1
1
Rev. 2.00 Sep. 25, 2008 Page 1232 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation PCR_1 PMR_1 NDERH_1 NDERL_1 PODRH_1 PODRL_1 NDRH_1 NDRL_1 BARAH BARAL BAMRAH BAMRAL BARBH BARBL BAMRBH BAMRBL BARCH BARCL BAMRCH BAMRCL BARDH BARDL BAMRDH BAMRDL BRCRA BRCRB BRCRC BRCRD TSTRB TSYRB
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module PPG
1
1
PPG
1
1
1
1
1
1
UBC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
TPU (unit 1)
Rev. 2.00 Sep. 25, 2008 Page 1233 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation TCR_6 TMDR_6 TIORH_6 TIORL_6 TIER_6 TSR_6 TCNT_6 TGRA_6 TGRB_6 TGRC_6 TGRD_6 TCR_7 TMDR_7 TIOR_7 TIER_7 TSR_7 TCNT_7 TGRA_7 TGRB_7 TCR_8 TMDR_8 TIOR_8 TIER_8 TSR_8 TCNT_8 TGRA_8 TGRB_8 TCR_9 TMDR_9
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module TPU_6
1
1
1
1
1
1
1
1
1
1
1
TPU_7
1
1
1
1
1
1
1
1
TPU_8
1
1
1
TPU_9
1
1
1
1
1
1
Rev. 2.00 Sep. 25, 2008 Page 1234 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation TIORH_9 TIORL_9 TIER_9 TSR_9 TCNT_9 TGRA_9 TGRB_9 TGRC_9 TGRD_9 TCR_10 TMDR_10 TIOR_10 TIER_10 TSR_10 TCNT_10 TGRA_10 TGRB_10 TCR_11 TMDR_11 TIOR_11 TIER_11 TSR_11 TCNT_11 TGRA_11 TGRB_11 P1DDR P2DDR P6DDR PADDR
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module TPU_9
1
1
1
1
1
1
1
1
1
TPU_10
1
1
1
1
1
1
1
1
TPU_11
1
1
1
1
1
1
1
1
I/O port
1
1
1
Rev. 2.00 Sep. 25, 2008 Page 1235 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation PBDDR PDDDR PEDDR PFDDR P1ICR P2ICR P5ICR P6ICR PAICR PBICR PDICR PEICR PFICR PORTH PORTI PORTJ PORTK PHDR PIDR PJDR PKDR PHDDR PIDDR PJDDR PKDDR PHICR PIICR PJICR PKICR
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1 1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module I/O port
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. 2.00 Sep. 25, 2008 Page 1236 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation PDPCR PEPCR PFPCR PHPCR PIPCR PJPCR PKPCR P2ODR PFODR PFCR0 PFCR1 PFCR2 PFCR4 PFCR6 PFCR7 PFCR8 PFCR9 PFCRA PFCRB PFCRC PFCRD SSIER DPSBKR0 DPSBKR1 DPSBKR2 DPSBKR3 DPSBKR4 DPSBKR5 DPSBKR6
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module I/O port
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
INTC SYSTEM
Rev. 2.00 Sep. 25, 2008 Page 1237 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation DPSBKR7 DPSBKR8 DPSBKR9 DPSBKR10 DPSBKR11 DPSBKR12 DPSBKR13 DPSBKR14 DPSBKR15 DSAR_0 DDAR_0 DOFR_0 DTCR_0 DBSR_0 DMDR_0 DACR_0 DSAR_1 DDAR_1 DOFR_1 DTCR_1 DBSR_1 DMDR_1 DACR_1 DSAR_2 DDAR_2 DOFR_2 DTCR_2 DBSR_2 DMDR_2
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module SYSTEM
DMAC_0
1
1
1
1
1
1
1
DMAC_1
1
1
1
1
1
1
1
DMAC_2
1
1
1
1
1
Rev. 2.00 Sep. 25, 2008 Page 1238 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation DACR_2 DSAR_3 DDAR_3 DOFR_3 DTCR_3 DBSR_3 DMDR_3 DACR_3 EDSAR_0 EDDAR_0 EDOFR_0 EDTCR_0 EDBSR_0 EDMDR_0 EDACR_0 EDSAR_1 EDDAR_1 EDOFR_1 EDTCR_1 EDBSR_1 EDMDR_1 EDACR_1 EDSAR_2 EDDAR_2 EDOFR_2 EDTCR_2 EDBSR_2 EDMDR_2 EDACR_2
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module DMAC_2 DMAC_3
1
1
1
1
1
1
1
1
EXDMAC_0
1
1
1
1
1
1
1
EXDMAC_1
1
1
1
1
1
1
1
EXDMAC_2
1
1
1
1
1
1
Rev. 2.00 Sep. 25, 2008 Page 1239 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation EDSAR_3 EDDAR_3 EDOFR_3 EDTCR_3 EDBSR_3 EDMDR_3 EDACR_3 CLSBR0 CLSBR1 CLSBR2 CLSBR3 CLSBR4 CLSBR5 CLSBR6 CLSBR7 DMRSR_1 DMRSR_1 DMRSR_2 DMRSR_3 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1 1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module EXDMAC_3
1
1
1
1
1
1
EXDMAC
DMAC_1 DMAC_1 DMAC_2 DMAC_3 INTC
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. 2.00 Sep. 25, 2008 Page 1240 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation IPRK IPRL IPRM IPRN IPRO IPRQ IPRR ISCRH ISCRL DTCVBR ABWCR ASTCR WTCRA WTCRB RDNCR CSACR IDLCR BCR1 BCR2 ENDIANCR SRAMCR BROMCR MPXCR RAMER MDCR SYSCR SCKCR SBYCR MSTPCRA
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module INTC
1
1
1
1
1
1
1
1
1
BSC
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SYSTEM
1
1
1
1
Rev. 2.00 Sep. 25, 2008 Page 1241 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation MSTPCRB MSTPCRC FCCS FPCS FEC FKEY FMATS FTDAR DPSBYCR DPSWCR DPSIER DPSIFR DPSIEGR RSTSR LVDCR*
3
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
4
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby Initialized Initialized Initialized Initialized Initialized Initialized
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1 1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module SYSTEM
1
1
FLASH
1
1
1
1
1
SYSTEM
Initialized* Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SEMR_2 SMR_4 BRR_4 SCR_4 TDR_4 SSR_4 RDR_4 SCMR_4 ICCRA_1 ICCRB_1 ICMR_1 ICIER_1 ICSR_1 SAR_1
SCI_2 SCI_4
1
1
1
1
1
1
1
1
IIC2_1
1
1
1
1
1
Rev. 2.00 Sep. 25, 2008 Page 1242 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation ICDRT_1 ICDRR_1 ICCRA_1 ICCRB_1 ICMR_1 ICIER_1 ICSR_1 SAR_1 ICDRT_1 ICDRR_1 TCR_2 TCR_3 TCSR_2 TCSR_3 TCORA_2 TCORA_3 TCORB_2 TCORB_3 TCNT_2 TCNT_3 TCCR_2 TCCR_3 TCR_4 TMDR_4 TIOR_4 TIER_4 TSR_4
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module IIC2_1
1
1
1
1
1
1
1
1
1
1
TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TMR_2 TMR_3 TPU_4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rev. 2.00 Sep. 25, 2008 Page 1243 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation TCNT_4 TGRA_4 TGRB_4 TCR_5 TMDR_5 TIOR_5 TIER_5 TSR_5 TCNT_5 TGRA_5 TGRB_5 DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF DTCCR INTCR CPUPCR IER ISR PORT1 PORT2 PORT5 PORT6 PORTA PORTB PORTD
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module TPU_4
1
1
1
TPU_5
1
1
1
1
1
1
1
1
INTC
1
1
1
1
1
1
1
1
1
1
I/O port
Rev. 2.00 Sep. 25, 2008 Page 1244 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation PORTE PORTF P1DR P2DR P6DR PADR PBDR PDDR PEDR PFDR SMR_2 BRR_2 SCR_2 TDR_2 SSR_2 RDR_2 SCMR_2 DADR0 DADR1 DACR01 PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep Initialized Initialized Initialized
AllSoftware ModuleClock-Stop Standby Initialized Initialized Initialized Initialized Initialized Initialized
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module I/O port
1
1
1
1
1
1
1
1
SCI_2
1
1
1
1
1
1
1
D/A
1
1
1
PPG
1
1
1
1
1
1
1
Rev. 2.00 Sep. 25, 2008 Page 1245 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 SMR_1 BRR_1 SCR_1 TDR_1 SSR_1 RDR_1 SCMR_1 ADDRA_1 ADDRB_1 ADDRC_1 ADDRD_1 ADDRE_1 ADDRF_1 ADDRG_1 ADDRH_1 ADCSR_1 ADCR_1 TCSR TCNT RSTCSR TCR_0 TCR_1
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep Initialized Initialized Initialized Initialized Initialized Initialized
AllSoftware ModuleClock-Stop Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module SCI_1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A/D_1
1
1
1
1
1
1
1
1
1
1
WDT
1
1
1
TMR_0 TMR_1
1
Rev. 2.00 Sep. 25, 2008 Page 1246 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation TCSR_0 TCSR_1 TCORA_0 TCORA_1 TCORB_0 TCORB_1 TCNT_0 TCNT_1 TCCR_0 TCCR_1 TSTR TSYR TCR_0 TMDR_0 TIORH_0 TIORL_0 TIER_0 TSR_0 TCNT_0 TGRA_0 TGRB_0 TGRC_0 TGRD_0 TCR_1 TMDR_1 TIOR_1 TIER_1 TSR_1 TCNT_1
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TMR_0 TMR_1 TPU
1
1
1
1
1
1
1
1
1
1
1
1
TPU_0
1
1
1
1
1
1
1
1
1
1
1
TPU_1
1
1
1
1
1
Rev. 2.00 Sep. 25, 2008 Page 1247 of 1340 REJ09B0413-0200
Section 28 List of Registers
Register Abbreviation TGRA_1 TGRB_1 TCR_2 TMDR_2 TIOR_2 TIER_2 TSR_2 TCNT_2 TGRA_2 TGRB_2 TCR_3 TMDR_3 TIORH_3 TIORL_3 TIER_3 TSR_3 TCNT_3 TGRA_3 TGRB_3 TGRC_3 TGRD_3
Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module Stop State Sleep
AllSoftware ModuleClock-Stop Standby
Deep Software Standby Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized* Initialized*
1
Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Module TPU_1
1
1
TPU_2
1
1
1
TPU_2
1
1
1
1
1
TPU_3
1
1
1
1
1
1
1
1
1
1
TPU_3
Notes: 1. Not initialized in deep software standby mode but initialized when deep software standby mode is released by the internal reset. 2. These registers are initialized when all the RAMCUT2 to RAMCUT0 bits in DPSBYCR are set to 1, and not initialized when these bits are set to 0. 3. Supported only by the H8SX/1658M Group. 4. LVDCR is initialized by a pin reset or power-on reset not by a voltage-monitoring reset, deep software standby reset, or watchdog timer reset.
Rev. 2.00 Sep. 25, 2008 Page 1248 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Section 29 Electrical Characteristics
29.1 Absolute Maximum Ratings
Table 29.1 Absolute Maximum Ratings
Item Power supply voltage Symbol VCC PLLVCC DrVCC Input voltage (except for port 5) Input voltage (port 5) Reference power supply voltage Analog power supply voltage Analog input voltage Operating temperature Vin Vin Vref AVCC VAN Topr -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +4.6 -0.3 to AVCC +0.3 Regular specifications: -20 to +75* Wide-range specifications: -40 to +85* Storage temperature Tstg -55 to +125 C Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded. Note: * The operating temperature range during programming/erasing of the flash memory is 0C to +75C for regular specifications and 0C to +85C for wide-range specifications. V V V V V C Value -0.3 to +4.6 Unit V
Rev. 2.00 Sep. 25, 2008 Page 1249 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
29.2
DC Characteristics H8SX/1658R Group
Table 29.2 DC Characteristics (1) Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Schmitt IRQ input pin, trigger input TPU input pin, voltage TMR input pin, port 2 port J, port K IRQ0-B to Symbol VT VT
- +
Min. VCC x 0.2
-
Typ.
Max. VCC x 0.7 VCC + 0.3 VCC + 0.3 AVCC + 0.3 VCC x 0.1 VCC x 0.2 VCC x 0.2 0.4 10.0 1.0 1.0
Test Unit Conditions V V V V
VT - VT VT-
+ +
+
VCC x 0.06
AVCC x 0.2
-
IRQ7-B input pin VT MD, RES, STBY, VIH EMLE, NMI EXTAL Other input pins Port 5 MD, RES, STBY, VIL EMLE EXTAL, NMI Other input pins

AVCC x 0.7 V V V
VT - VT Input high voltage (except Schmitt trigger input pin) Input low voltage (except Schmitt trigger input pin)
AVCC x 0.06 VCC x 0.9 VCC x 0.7
AVCC x 0.7 -0.3 -0.3 -0.3 VOH VOL |Iin| VCC - 0.5 VCC - 1.0
V
Output high All output pins voltage Output low voltage Input leakage current All output pins RES MD, STBY, EMLE, NMI Port 5
V
IOH = -200 A IOH = -1 mA IOL = 1.6 mA Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V
V A
Rev. 2.00 Sep. 25, 2008 Page 1250 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Table 29.2 DC Characteristics (2) Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Three-state Ports 1, 2, 3, 6, leakage current A to F, H to K, M (off state) Input pull-up MOS current Input capacitance Ports D to F, H, I Symbol Min. | ITSI | Typ. Max. 1.0 Test Unit Conditions A Vin = 0.5 to VCC - 0.5 V VCC = 3.0 to 3.6 V Vin = 0 V All input pins Cin 15 pF Vin = 0 V f = 1 MHz Ta = 25C f = 50 MHz Ta 50C 50C < Ta A Ta 50C 50C < Ta Ta 50C 50C < Ta A Ta 50C 50C < Ta mA
-Ip
10
300
A
Supply current*2 Normal operation Sleep mode
Standby Software standby mode mode*3 Deep standby mode RAM, USB
ICC*4

50 48 0.15 20 3 2 23
85 60 1.1 3.5 60 200 8 26 7 25 30
mA
mA
software retained*3
RAM, USB power supply stopped

Hardware standby mode All-module-clock-stop mode*5
Rev. 2.00 Sep. 25, 2008 Page 1251 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Item Analog power During A/D and supply current D/A conversion Standby for A/D and D/A conversion Reference power supply current During A/D and D/A conversion Standby for A/D and D/A conversion
Symbol Min. AICC AICC VRAM VCCSTART
6
Typ. 1.0 0.5 0.5 0.5
Max. 2.5 1.0 1.0 1.0 0.8 20
Test Unit Conditions mA A mA A V V ms/V
RAM standby voltage Vcc start voltage*
6
2.5
Vcc rising gradient*
SVCC
Notes: 1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. Supply current values are for VIHmin = VCC - 0.5 V and VILmax = 0.5 V with all output pins unloaded and all built-in pull-up MOSs in the off state. 3. The values are for VRAM VCC < 3.0 V, VIHmin = VCC x 0.9, and VILmax = 0.3 V. 4. ICC depends on f as follows: ICCmax = 30 (mA) + 1.1 (mA/MHz) x f (normal operation) ICCmax = 35 (mA) + 0.5 (mA/MHz) x f (sleep mode) 5. The values are for reference. 6. This applies when the RES pin is held low at power-on.
Rev. 2.00 Sep. 25, 2008 Page 1252 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Table 29.3 Permissible Output Currents Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V*, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Caution: Note: * Output pins Symbol IOL Min. Typ. Max. 2.0 80 2.0 40 Unit mA mA mA mA
Total of output pins IOL All output pins Total of all output pins -IOH -IOH
To protect the LSI's reliability, do not exceed the output current values in table 29.3. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.
Rev. 2.00 Sep. 25, 2008 Page 1253 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
29.3
DC Characteristics H8SX/1658M Group
Table 29.4 DC Characteristics (1) Conditions: VCC = PLLVCC = 2.95 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Schmitt IRQ input pin, trigger input TPU input pin, TMR input pin, voltage port 2, port J, port K IRQ0-B to IRQ7B input pins Symbol VT- VT+
+ - VT - VT
Min. VCC x 0.2 VCC x 0.06
Typ.
Max. VCC x 0.7
Test Unit Conditions V V V V
VT-
AVCC x 0.2
VT+ + - VT - VT AVCC x 0.06 Input high MD, RES, STBY, VIH VCC x 0.9 voltage EMLE, NMI (except EXTAL VCC x 0.7 Schmitt Other input pins trigger input pin) Port 5 AVCC x 0.7 Input low voltage (except Schmitt trigger input pin) MD, RES, STBY, VIL EMLE EXTAL, NMI Other input pins VOH VOL |Iin| -0.3 -0.3 -0.3 VCC - 0.5 VCC - 1.0
AVCC x 0.7 V V VCC + 0.3 V VCC + 0.3 AVCC + 0.3 VCC x 0.1 VCC x 0.2 VCC x 0.2 0.4 10.0 1.0 1.0 V V A IOH = -200 A IOH = -1 mA IOL = 1.6 mA Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V V
Output high All output pins voltage Output low voltage Input leakage current All output pins RES MD, STBY, EMLE, NMI Port 5
Rev. 2.00 Sep. 25, 2008 Page 1254 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Table 29.4 DC Characteristics (2) Conditions: VCC = PLLVCC = 2.95 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC , VSS = PLLVSS = AVSS = 0 V*1, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item SymTest bol Min. Typ. Max. Unit Conditions 1.0 A Vin = 0.5 to VCC - 0.5 V VCC = 2.95 to 3.6 V Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C f = 50 MHz
Three-state Ports 1, 2, 6, A, B, C to F, H, I, J, | ITSI | leakage current K, M (off state) Input pull-up MOS current Input capacitance Current consumption*2 Ports D to F, H, I -Ip
10
300
A
All input pins
Cin
15
pF
Normal operation Sleep mode Standby Software standby mode*3 mode RAM, USB Deep 3 software retained* standby RAM, USB mode power supply halted Hardware standby mode All-module-clock-stop mode*5
ICC*4

50 48 24 23 2 23 1.0 0.5 0.5 0.5
85 60
mA
0.15 1.1 3.5 67 200 35 60 7 25 30 3.0 1.0 1.0 1.0 20
mA A A
Ta 50C 50C < Ta Ta 50C 50C < Ta Ta 50C 50C < Ta
ICC*4

A
Ta 50C 50C < Ta
mA mA A mA A V ms/V
Analog power supply current
During A/D and D/A conversion Standby for A/D and D/A conversion During A/D and D/A conversion Standby for A/D and D/A conversion
AICC
Reference power supply current
AICC

RAM standby voltage Vcc rising gradient*
6
VRAM SVCC
2.5
Rev. 2.00 Sep. 25, 2008 Page 1255 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Notes: 1. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS. 2. Current consumption values are for VIHmin = VCC - 0.5 V and VILmax = 0.5 V with all output pins unloaded and all input pull-up MOSs in the off state. 3. The values are for VRAM VCC < 3.0 V, VIHmin = VCC x 0.9, and VILmax = 0.3 V. 4. ICC depends on f as follows: ICCmax = 30 (mA) + 1.1 (mA/MHz) x f (normal operation) ICCmax = 35 (mA) + 0.5 (mA/MHz) x f (sleep mode) 5. The values are for reference. 6. This can be applied at power-on.
Table 29.5 Permissible Output Currents Conditions: VCC = PLLVCC = 2.95 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = AVSS = 0 V*, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications) Applicable products: H8SX/1658M Group
Item Permissible output low current (per pin) Permissible output low current (total) Permissible output high current (per pin) Permissible output high current (total) Caution: Note: * Output pins Total of all output pins All output pins Total of all output pins Symbol IOL IOL -IOH -IOH Min. Typ. Max. 2.0 80 2.0 40 Unit mA mA mA mA
To protect the LSI's reliability, do not exceed the output current values in table 29.5. When the A/D and D/A converters are not used, the AVCC, Vref, and AVSS pins should not be open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.
Rev. 2.00 Sep. 25, 2008 Page 1256 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
29.4
AC Characteristics
3V
RL
LSI output pin C = 30 pF RL = 2.4 k RH = 12 k Input/output timing measurement level: 1.5 V (Vcc = 3.0 V to 3.6 V*)
C
RH
Note: *
Vcc=2.95 to 3.60V in the H8SX/1658M Group.
Figure 29.1 Output Load Circuit
Rev. 2.00 Sep. 25, 2008 Page 1257 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
29.4.1
Clock Timing
Table 29.6 Clock Timing Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V*, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, I = 8 MHz to 50 MHz, B = 8 MHz to 50 MHz, P = 8 MHz to 35 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Clock cycle time Clock high pulse width Clock low pulse width Clock rising time Clock falling time Oscillation settling time after reset (crystal) Oscillation settling time after leaving software standby mode (crystal) External clock output delay settling time External clock input low pulse width Symbol tcyc tCH tCL tCr tCf tOSC1 tOSC2 tDEXT TEXL TEXr TEXf Min. 20 5 5 10 10 1 27.7 27.7 Max. 125 5 5 5 5 Unit. ns ns ns ns ns ms ms ms ns ns ns ns Figure 29.4 Figure 29.3 Figure 29.4 Figure 29.5 Test Conditions Figure 29.2
External clock input high pulse width TEXH External clock rising time External clock falling time Note: *
Vcc= PLLVcc= DrVcc = 2.95V to 3.60V in the H8SX/1658M Group
tcyc tCH B tCf
tCL
tCr
Figure 29.2 External Bus Clock Timing
Rev. 2.00 Sep. 25, 2008 Page 1258 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Oscillator
I
NMI
NMIEG
SSBY
NMI exception handling NMI exception handling NMIEG = 1 SSBY = 1 Software standby mode (power-down mode) Oscillation settling time tOSC2
SLEEP instruction
Figure 29.3 Oscillation Settling Timing after Software Standby Mode
EXTAL tDEXT VCC tDEXT
STBY tOSC1 RES tOSC1
I
Figure 29.4 Oscillation Settling Timing
Rev. 2.00 Sep. 25, 2008 Page 1259 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
tEXH
tEXL
EXTAL
Vcc x 0.5
tEXr
tEXf
Figure 29.5 External Input Clock Timing
Rev. 2.00 Sep. 25, 2008 Page 1260 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
29.4.2
Control Signal Timing
Table 29.7 Control Signal Timing Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V*, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, I = 8 MHz to 50 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item RES setup time RES pulse width NMI setup time NMI hold time NMI pulse width (after leaving software standby mode) IRQ setup time IRQ hold time IRQ pulse width (after leaving software standby mode) Note: * Symbol tRESS tRESW tNMIS tNMIH tNMIW tIRQS tIRQH tIRQW Min. 200 20 150 10 200 150 10 200 Max. Unit ns tcyc ns ns ns ns ns ns Figure 29.7 Test Conditions Figure 29.6
Vcc= PLLVcc= DrVcc = 2.95V to 3.60V in the H8SX/1658M Group
I
tRESS RES tRESW tRESS
Figure 29.6 Reset Input Timing
Rev. 2.00 Sep. 25, 2008 Page 1261 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
I
tNMIS tNMIH
NMI
tNMIW
IRQi* (i = 0 to 11)
tIRQW
tIRQS
tIRQH
IRQ (edge input)
tIRQS
IRQ (level input)
Note: * SSIER must be set to cancel software standby mode.
Figure 29.7 Interrupt Input Timing 29.4.3 Bus Timing
Table 29.8 Bus Timing (1) Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V*, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC , VSS = PLLVSS = DrVSS = AVSS = 0 V, B = 8 MHz to 50 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Address delay time Address setup time 1 Address setup time 2 Address setup time 3 Address setup time 4 Address hold time 1 Address hold time 2 Address hold time 3 Symb ol Min. tAD tAS1 tAS2 tAS3 tAS4 tAH1 tAH2 tAH3 0.5 x tCYC - 8 1.0 x tCYC - 8 1.5 x tCYC - 8 2.0 x tCYC - 8 0.5 x tCYC - 8 1.0 x tCYC - 8 1.5 x tCYC - 8 Max. 15 Unit ns ns ns ns ns ns ns ns Test Conditions Figures 29.8 to 29.20
Rev. 2.00 Sep. 25, 2008 Page 1262 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Item CS delay time 1 AS delay time RD delay time 1 RD delay time 2 Read data setup time 1 Read data setup time 2 Read data hold time 1 Read data hold time 2 Read data access time 2 Read data access time 4 Read data access time 5 Read data access time 6 Read data access time (from address) 1 Read data access time (from address) 2 Read data access time (from address) 3 Read data access time (from address) 4 Read data access time (from address) 5 Note: *
Symbol tCSD1 tASD tRSD1 tRSD2 tRDS1 tRDS2 tRDH1 tRDH2 tAC2 tAC4 tAC5 tAC6 tAA1 tAA2 tAA3 tAA4 tAA5
Min. 15 15 0 0
Max. 15 15 15 15
Unit ns ns ns ns ns ns ns ns
Test Conditions Figures 29.8 to 29.20
1.5 x tCYC - 20 ns 2.5 x tCYC - 20 ns 1.0 x tCYC - 20 ns 2.0 x tCYC - 20 ns 1.0 x tCYC - 20 ns 1.5 x tCYC - 20 ns 2.0 x tCYC - 20 ns 2.5 x tCYC - 20 ns
3.0 x tCYC - 20 ns
Vcc= PLLVcc= DrVcc = 2.95V to 3.60V in the H8SX/1658M Group
Rev. 2.00 Sep. 25, 2008 Page 1263 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Table 29.8 Bus Timing (2) Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V*, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, B = 8 MHz to 50 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time 1 Write data setup time 2 Write data setup time 3 Write data hold time 1 Write data hold time 3 Byte control delay time Byte control pulse width 1 Byte control pulse width 2 Multiplexed address delay time 1 Multiplexed address hold time Multiplexed address setup time 1 Multiplexed address setup time 2 Address hold delay time Address hold pulse width 1 Address hold pulse width 2 WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus floating time BREQO delay time BS delay time RD/WR delay time Note: * Symbol Min. tWRD1 tWRD2 tWSW1 tWSW2 tWDD tWDS1 tWDS2 tWDS3 tWDH1 tWDH3 tUBD tUBW1 tUBW2 tMAD1 tMAH tMAS1 tMAS2 tAHD tAHW1 tAHW2 tWTS tWTH tBREQS tBACD tBZD tBRQOD TBSD TRWD Max. 15 15 Unit Test Conditions ns ns ns ns ns ns ns ns ns ns ns Figures 29.13, 29.14 Figure 29.13 Figure 29.14 Figures 29.17, 29.18 Figures 29.8 to 29.20
1.0 x tCYC - 13 1.5 x tCYC - 13 20 0.5 x tCYC - 13 1.0 x tCYC - 13 1.5 x tCYC - 13 0.5 x tCYC - 8 1.5 x tCYC - 8 15
1.0 x tCYC - 15 ns 2.0 x tCYC - 15 ns 15 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
1.0 x tCYC - 15 0.5 x tCYC - 15 1.5 x tCYC - 15 15 1.0 x tCYC - 15 2.0 x tCYC - 15 15 5.0 20 1.0 15 30 15 15 15
Figures 29.10, 29.18 Figure 29.19
Figure 29.20 Figures 29.8, 29.9, 29.11 to 29.14
Vcc= PLLVcc= DrVcc = 2.95V to 3.60V in the H8SX/1658M Group.
Rev. 2.00 Sep. 25, 2008 Page 1264 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
T1
B
T2
tAD
A20 to A0
tCSD1
CS7 to CS0
tAS1
tASD
tASD
tAH1
AS tBSD BS
tBSD
tRWD
tRWD
RD/WR
tAS1
tRSD1
tRSD1
Read (RDNn = 1)
RD
tAC5 tAA2
tRDS1 tRDH1
D15 to D0
tRWD
tRWD
RD/WR RD
tAS1
tRSD1
tRSD2
Read (RDNn = 0)
D15 to D0
tAC2 tAA3 tRWD
tRDS2 tRDH2
tRWD
RD/WR tAS1
LHWR, LLWR
tWRD2 tWRD2
tAH1
Write
tWDD
D15 to D0 (write)
tWSW1
tWDH1
tDACD1
tDACD2
(DKC = 0) DACK0 to DACK3 (DKC = 1) DACK0 to DACK3
tDACD2
tDACD2
Figure 29.8 Basic Bus Timing: Two-State Access
Rev. 2.00 Sep. 25, 2008 Page 1265 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
T1
T2
T3
B
tAD
A20 to A0
tCSD1
CS7 to CS0
tAS1
tASD
tASD
tAH1
AS
tBSD
tBSD
BS
tRWD tRWD
RD/WR
tAS1 tRSD1 tRSD1
Read (RDNn = 1)
RD
tAC6 tAA4
tRWD
tRDS1 tRDH1
D15 to D0
tRWD
RD/WR
tAS1 tRSD1 tRSD2
Read (RDNn = 0)
RD
tAC4 tRDS2 tRDH2
D15 to D0
tRWD
tAA5
tRWD
RD/WR
tAS2 tWRD1 tWRD2 tAH1
Write
LHWR, LLWR
tWDD
tWDS1 tWSW2 tWDH1
D15 to D0 (write)
tDACD1
tDACD2
(DKC = 0) DACK0 to DACK3 (DKC = 1) DACK0 to DACK3
tDACD2
tDACD2
Figure 29.9 Basic Bus Timing: Three-State Access
Rev. 2.00 Sep. 25, 2008 Page 1266 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
T1 B
T2
Tw
T3
A20 to A0
CS7 to CS0
AS
BS
RD/WR
Read (RDNn = 1)
RD
D15 to D0
RD/WR
Read (RDNn = 0)
RD
D15 to D0
RD/WR
Write
LHWR, LLWR
D15 to D0 tWTS tWTH WAIT tWTS tWTH
Figure 29.10 Basic Bus Timing: Three-State Access, One Wait
Rev. 2.00 Sep. 25, 2008 Page 1267 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Th
B
T1
T2
Tt
tAD
A20 to A0
tCSD1
CS7 to CS0
tAS1 tASD
AS
tASD
tAH1
tBSD
BS
tBSD
tRWD
RD/WR
tRWD
tAS3
Read (RDNn = 1)
tRSD1 tRSD1
tAH3
RD
tAC5
D15 to D0
tRDS1 tRDH1
tRWD
RD/WR
tRWD
tAS3
Read (RDNn = 0)
tRSD1
tRSD2
tAH2
RD
tAC2
D15 to D0
tRDS2 tRDH2
tRWD
tRWD
RD/WR
tAS3
Write LHWR, LLWR
tWRD2 tWRD2
tAH3
tWDD
D15 to D0 (write)
tWDS2
tWSW1
tWDH3
tDACD1
(DKC = 0) DACK0 to DACK3
tDACD2
tDACD2
(DKC = 1) DACK0 to DACK3
tDACD2
Figure 29.11 Basic Bus Timing: Two-State Access (CS Assertion Period Extended)
Rev. 2.00 Sep. 25, 2008 Page 1268 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Th
B
T1
T2
T3
Tt
tAD
A20 to A0
tCSD1
CS7 to CS0
tAS1 tASD
AS
tASD
tAH1
tBSD
BS
tBSD
tRWD
RD/WR
tRWD
tAS3
Read (RDNn = 1)
tRSD1
tRSD1
tAH3
RD
tAC6
D15 to D0
tRDS1 tRDH1
tRWD
RD/WR
tRWD
tAS3
Read (RDNn = 0)
tRSD1
tRSD2
tAH2
RD
tAC4
D15 to D0
tRDS2 tRDH2
tRWD
tRWD
RD/WR
tAS4
Write LHWR, LLWR
tWRD2 tWRD1 tWDS3
tAH3
tWDD
D15 to D0 (write)
tWSW2
tWDH3
tDACD1
(DKC = 0) DACK0 to DACK3
tDACD2
tDACD2
(DKC = 1) DACK0 to DACK3
tDACD2
Figure 29.12 Basic Bus Timing: Three-State Access (CS Assertion Period Extended)
Rev. 2.00 Sep. 25, 2008 Page 1269 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
T1 B tAD A20 to A0 tCSD1 CS7 to CS0 tAS1 AS tBSD BS tRWD RD/WR tAS1 tRSD1 tASD tASD
T2
tAH1
tBSD
tRWD
tRSD1
Read
RD tAC5 tRDS1 tRDH1 D15 to D0 tAA2 tAC5 tUBD LUB, LLB tAS1 tRWD RD/WR tUBW1 tAH1 tRWD tUBD
Write
RD
High tWDD tWDH1
D15 to D0 (write)
Figure 29.13 Byte Control SRAM: Two-State Read/Write Access
Rev. 2.00 Sep. 25, 2008 Page 1270 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
T1 B tAD A20 to A0 tCSD1 CS7 to CS0 tAS1 tASD
T2
T3
tASD
tAH1
AS tBSD BS tRWD RD/WR tAS1 tRSD1 Read RD tAC6 tAA4 D15 to D0 tAC6 tUBD LUB, LLB tAS1 tRWD RD/WR tUBW2 tUBD tAH1 tRWD tRDS1 tRDH1 tRSD1 tRWD tBSD
Write
RD D15 to D0 (write)
High
tWDD
tWDH1
Figure 29.14 Byte Control SRAM: Three-State Read/Write Access
Rev. 2.00 Sep. 25, 2008 Page 1271 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
T1 B
T2
T1
T1
A20 to A6, A0 tAD A5 to A1
CS7 to CS0
AS
BS
RD/WR tRSD2 Read RD tAA1 tRDS2 tRDH2 D15 to D0
LHWR, LLWR
High
Figure 29.15 Burst ROM Access Timing: One-State Burst Access
Rev. 2.00 Sep. 25, 2008 Page 1272 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
T1 B
T2
T3
T1
T2
A20 to A6, A0 tAD A5 to A1
CS7 to CS0 tAS1 AS tASD tASD tAH1
BS
RD/WR tRSD2 Read RD tAA3 D15 to D0 tRDS2 tRDH2
LHWR, LLWR
High
Figure 29.16 Burst ROM Access Timing: Two-State Burst Access
Rev. 2.00 Sep. 25, 2008 Page 1273 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Tma1
B
Tma2
T1
T2
tAD
A20 to A0
CS7 to CS0
tAHD
AH (AS)
tAHD
tAHW1
RD/WR
Read
RD
tMAD1
AD15 to AD0
tMAS1
tMAH
tRDS2
tRDH2
RD/WR
tWSW1
Write LHWR, LLWR
tMAS1 tMAD1
AD15 to AD0
tMAH tWDD tWDH1
BS DKC = 0 DACK3 to DACK0 DKC = 1
Figure 29.17 Address/Data Multiplexed Access Timing (No Wait) (Basic, Four-State Access)
Rev. 2.00 Sep. 25, 2008 Page 1274 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Tma1
B
Tmaw
Tma2
T1
T2
Tpw
Ttw
T3
tAD
A20 to A0
CS7 to CS0
tAHD
AH (AS)
tAHD tAHW2
RD/WR
Read
RD
tMAS2 tMAD1
AD15 to AD0
tMAH tRDS2 tRDH2
RD/WR
Write
LHWR, LLWR
tMAS2 tMAD1
tMAH tWDS1 tWDH1
AD15 to AD0
tWDD
WAIT
tWTS tWTH tWTS tWTH
Figure 29.18 Address/Data Multiplexed Access Timing (Wait Control) (Address Cycle Program Wait x 1 + Data Cycle Program Wait x 1 + Data Cycle Pin Wait x 1)
Rev. 2.00 Sep. 25, 2008 Page 1275 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
B tBREQS BREQ tBACD BACK tBZD A20 to A0 tBZD tBACD tBREQS
CS7 to CS0
D15 to D0
AS, RD, LHWR, LLWR
Figure 29.19 External Bus Release Timing
B
BACK tBRQOD BREQO tBRQOD
Figure 29.20 External Bus Request Output Timing
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Section 29 Electrical Characteristics
29.4.4
DMAC/EXDMAC Timing
Table 29.9 DMAC/EXDMAC Timing Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V*, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, B = 8 MHz to 50 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item DREQ setup time DREQ hold time TEND delay time DACK delay time 1 DACK delay time 2 EDREQ setup time EDREQ hold time ETEND delay time EDACK delay time 1 EDACK delay time 2 EDRAK delay time Note: * Symbol tDRQS tDRQH tTED tDACD1 tDACD2 tEDRQS tEDRQH tETED tEDACD1 tEDACD2 tEDRKD Min. 20 5 20 5 Max. 15 15 15 15 15 15 15 Unit ns ns ns ns ns ns ns ns ns ns ns Figure 29.22 Figure 29.23 Figure 29.24 Figure 29.25 Figure 29.22 Figure 29.23 Figure 29.24 Figure 29.21 Test Conditions Figure 29.21
Vcc= PLLVcc= DrVcc = 2.95V to 3.60V in the H8SX/1658M Group
B
tDRQS
tDRQH
DREQ0 to DREQ3 tEDRQS tEDRQH EDREQ0 to EDREQ1
Figure 29.21 DMAC/EXDMAC (DREQ and EDREQ) Input Timing
Rev. 2.00 Sep. 25, 2008 Page 1277 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
T1
T2 or T3
B
tTED
tTED
TEND0 to TEND3 tETED tETED
ETEND0 to ETEND1
Figure 29.22 DMAC/EXDMAC (TEND and ETEND) Output Timing
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Section 29 Electrical Characteristics
T1
T2
B
A20 to A0
CS7 to CS0
AS RD (Read)
D15 to D0 (Read)
LHWR, LLWR (Write) D15 to D0 (Write) tDACD1 (DKC = 0) DACK0 to DACK3 tDACD2 (DKC = 1) DACK0 to DACK3 tEDACD1 (EDKC = 0) EDACK0 to EDACK1 tEDACD2 (EDKC = 1) EDACK0 to EDACK1 tEDACD2 tEDACD2 tDACD2 tDACD2
BS
RD/WR
Figure 29.23 DMAC/EXDMAC Single-Address Transfer Timing: Two-State Access
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Section 29 Electrical Characteristics
T1 B
T2
T3
A20 to A0
CS7 to CS0
AS
RD (Read) D15 to D0 (Read) LHWR, LLWR (Write) D15 to D0 (Write) tDACD1 (DKC = 0) DACK0 to DACK3 tDACD2 tDACD2 tDACD2
(DKC = 1) DACK0 to DACK3 tEDACD1 (EDCK = 0) EDACK0 to EDACK1 tEDACD2 tEDACD2
tEDACD2
(EDCK = 1) EDACK0 to EDACK1
BS
RD/WR
Figure 29.24 DMAC/EXDMAC Single-Address Transfer Timing: Three-State Access
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Section 29 Electrical Characteristics
B
tEDRKD EDRAK0 to EDRAK1
tEDRKD
Figure 29.25 EXDMAC (EDRAK) Output Timing
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Section 29 Electrical Characteristics
29.4.5
Timing of On-Chip Peripheral Modules
Table 29.10 Timing of On-Chip Peripheral Modules Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V*2, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, P = 8 MHz to 35 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item I/O ports Output data delay time Input data setup time Input data hold time TPU Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single-edge setting Both-edge setting PPG 8-bit timer Pulse output delay time Timer output delay time Timer reset input setup time Timer clock input setup time Timer clock pulse width Single-edge setting Both-edge setting WDT SCI Overflow output delay time Input clock cycle Asynchronous Clocked synchronous tSCKW tSCKr tSCKf Symbol tPWD tPRS tPRH tTOCD tTICS tTCKS tTCKWH tTCKWL tPOD tTMOD tTMRS tTMCS tTMCWH tTMCWL tWOVD tScyc Min. 25 25 25 25 1.5 2.5 25 25 1.5 2.5 4 6 0.4 Max. 40 40 40 40 40 0.6 1.5 1.5 tScyc tcyc tcyc Unit ns ns ns ns ns ns tcyc tcyc ns ns ns ns tcyc tcyc ns tcyc Figure 29.33 Figure 29.34 Figure 29.29 Figure 29.30 Figure 29.31 Figure 29.32 Figure 29.28 Figure 29.27 Test Conditions Figure 29.26
Input clock pulse width Input clock rise time Input clock fall time
Rev. 2.00 Sep. 25, 2008 Page 1282 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Item SCI Transmit data delay time Receive data setup time (clocked synchronous) Receive data hold time (clocked synchronous) A/D Trigger input setup time converter IIC2 SCL input cycle time SCL input high pulse width SCL input low pulse width SCL, SDA input falling time SCL, SDA input spike pulse removal time SDA input bus free time
Symbol tTXD tRXS tRXH tTRGS tSCL tSCLH tSCLL tSf tSP tBUF
Min. 40 40 30
12 tCYC + 600 3 tCYC + 300 5 tCYC + 300
Max. 40 300 1 tCYC
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns pF ns
Test Conditions Figure 29.35
Figure 29.36 Figure 29.37
5 tCYC 3 tCYC 3 tCYC
Start condition input hold time tSTAH Repeated start condition input tSTAS setup time Stop condition input setup time Data input setup time Data input hold time SCL, SDA capacitive load SCL, SDA falling time tSTOS tSDAS tSDAH Cb tSf
1 tCYC + 20
0 0
400 300
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Section 29 Electrical Characteristics
Item Boundary TCK clock cycle time scan TCK clock high pulse width TCK clock low pulse width TCK clock rising time TCK clock falling time TRST pulse width TMS setup time TMS hold time TDI setup time TDI hold time TDO data delay time
Symbol tTCKcyc tTCKH tTCKL tTCKr tTCKf tTRSTW tTMSS tTMSH tTDIS tTDIH tTDOD
Min. 50* 20 20 20 20 20 20 20
1
Max. 5 5 23
Unit ns ns ns ns ns Tcyc ns ns ns ns ns
Test Conditions Figure 29.38
Figure 29.39 Figure 29.40
Notes: 1. tTCKcyc tTCKcyc must be satisfied. 2. Vcc= PLLVcc= DrVcc = 2.95V to 3.60V in the H8SX/1658M Group
Rev. 2.00 Sep. 25, 2008 Page 1284 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
T1 P tPRS tPRH Ports 1, 2, 5, 6, A, B, D to F, H, I, M (read)
T2
tPWD Ports 1, 2, 6, A, B, D to F, H, I, M (write)
Figure 29.26 I/O Port Input/Output Timing
P tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA3 to TIOCA5, TIOCB3 to TIOCB5, TIOCC3, TIOCD3
Figure 29.27 TPU Input/Output Timing
P tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS
Figure 29.28 TPU Clock Input Timing
P tPOD PO7 to PO0
Figure 29.29 PPG Output Timing
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Section 29 Electrical Characteristics
P tTMOD TMO0 to TMO3
Figure 29.30 8-Bit Timer Output Timing
P tTMRS TMRI0 to TMRI3
Figure 29.31 8-Bit Timer Reset Input Timing
P tTMCS TMCI0 to TMCI3 tTMCWL tTMCWH tTMCS
Figure 29.32 8-Bit Timer Clock Input Timing
P tWOVD WDTOVF tWOVD
Figure 29.33 WDT Output Timing
tSCKW SCK0 to SCK2, SCK4 tScyc tSCKr tSCKf
Figure 29.34 SCK Clock Input Timing
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Section 29 Electrical Characteristics
SCK0 to SCK2, SCK4 TxD0 to TxD2, TxD4 (transmit data) RxD0 to RxD2, RxD4 (receive data)
tTXD
tRXS tRXH
Figure 29.35 SCI Input/Output Timing: Clocked Synchronous Mode
P
tTRGS ADTRG0, ADTRG1
Figure 29.36 A/D Converter External Trigger Input Timing
SDA0 to SDA1 tBUF
VIH VIL
tSTAH SCL0 to SCL1 P* S* tSf tSCLL tSCL Note:
tSCLH
tSTAS
tSP
tSTOS
Sr* tSr tSDAH tSDAS
P*
S, P, and Sr represent the following conditions: S: Start condition P: Stop condition Sr: Repeated start condition
Figure 29.37 I2C Bus Interface2 Input/Output Timing (Option)
Rev. 2.00 Sep. 25, 2008 Page 1287 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
tTCKcyc tTCKH
TCK
tTCKf
tTCKL
tTCKr
Figure 29.38 Boundary Scan TCK Timing
TCK
RES
TRST tTRSTW
Figure 29.39 Boundary Scan TRST Timing
TCK
tTMSS tTMSH
TMS
tTDIS tTDIH
TDI
tTDOD
TDO
Figure 29.40 Boundary Scan Input/Output Timing
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Section 29 Electrical Characteristics
29.5
USB Characteristics
Table 29.11 USB Characteristics when On-Chip USB Transceiver is Used (USD+, USD- pin characteristics) Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V*, VSS = PLLVSS = DrVSS = AVSS = 0 V, CKU = 48 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Input Input high voltage Input low voltage Differential input sensitivity Differential common mode range Output Output high voltage Output low voltage Crossover voltage Rising time Falling time Ratio of rising time to falling time Output resistance Note: * Symbol VIH VIL VDI VCM VOH VOL VCRS tR tF tRFM ZDRV Min. 2.0 0.2 0.8 2.8 1.3 4 4 90 28 Max. 0.8 2.5 0.3 2.0 20 20 111.11 44 Unit Test Conditions V V V V V V V ns ns %
(TR/TF) Including RS = 22 IOH = -200 A IOL = 2 mA (D+) - (D-) Figures 29.41, 29.42
Vcc= PLLVcc= DrVcc = 2.95V to 3.60V in the H8SX/1658M Group
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Section 29 Electrical Characteristics
Rise time USD+, USDVCRS 10% Differential data lines tR 90%
Fall time 90% 10% tF
Figure 29.41 Data Signal Timing
USD+
RS = 22
Test point
CL = 50 pF
USD-
RS = 22
Test point
CL = 50 pF
Figure 29.42 Load Condition
Rev. 2.00 Sep. 25, 2008 Page 1290 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
29.6
A/D Conversion Characteristics
Table 29.12 A/D Conversion Characteristics Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V*, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, P = 8 MHz to 35 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Resolution Conversion time Analog input capacitance Permissible signal source impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Note: * Min. 10 2.7 Typ. 10 0.5 Max. 10 20 5 3.5 3.5 3.5 4.0 Unit Bit s pF k LSB LSB LSB LSB LSB
Vcc= PLLVcc= DrVcc = 2.95V to 3.60V in the H8SX/1658M Group
29.7
D/A Conversion Characteristics
Table 29.13 D/A Conversion Characteristics Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V*, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, P = 8 MHz to 35 MHz, Ta = -20C to +75C (regular specifications), Ta = -40C to +85C (wide-range specifications)
Item Resolution Conversion time Absolute accuracy Note: * Min. 8 Typ. 8 2.0 Max. 8 10 3.0 2.0 Unit Bit s LSB LSB 20-pF capacitive load 2-M resistive load 4-M resistive load Test Conditions
Vcc= PLLVcc= DrVcc = 2.95V to 3.60V in the H8SX/1658M Group
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Section 29 Electrical Characteristics
29.8
Flash Memory Characteristics
Table 29.14 Flash Memory Characteristics Conditions: VCC = PLLVCC = DrVCC = 3.0 V to 3.6 V*5, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVSS = AVSS = 0 V, Operating temperature range during programming/erasing: Operating temperature range : Ta = 0C to +75C (regular specifications), Operating temperature range : Ta = 0C to +85C (wide-range specifications) Operating voltage range: VCC = PLLVCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = PLLVSS = DrVss=AVSS = 0 V
Item Programming time *1, *2, *4 Erasure time*1, *2, *4 Symbol Min. tP tE Programming time (total)*1, *2, *4 tP Erasure time (total) *1, *2, *4 tE Programming and Erasure time (total) 1, 2, 4 *** tPE Reprogramming count Data retention time*
4
Typ. 1 40 300 600 3.4 4.5 9.0 3.4 4.5 9.0 6.8 9.0 18.0
Max. 10 130 800 1500 9 12 24 9 12 24 18 24 48
Unit ms/128 bytes ms/4-Kbyte block ms/32-Kbyte block ms/64-Kbyte block
Test Conditions
H8SX/1653R, H8SX/1653M Ta = 25C, s/384 Kbytes for all 0s H8SX/1654R, H8SX/1654M s/512 Kbytes H8SX/1658R, H8SX/1658M s/1 Mbytes H8SX/1653R, H8SX/1653M Ta = 25C s/384 Kbytes H8SX/1654R, H8SX/1654M s/512 Kbytes H8SX/1658R, H8SX/1658M s/1 Mbytes H8SX/1653R, H8SX/1653M Ta = 25C s/384 Kbytes H8SX/1654R, H8SX/1654M s/512 Kbytes H8SX/1658R, H8SX/1658M s/1 Mbytes times years
NWEC TDRP
100*3 10
Rev. 2.00 Sep. 25, 2008 Page 1292 of 1340 REJ09B0413-0200
Section 29 Electrical Characteristics
Notes: 1. Programming time and erasure time depend on data in the flash memory. 2. Programming time and erasure time do not include time for data transfer. 3. All the characteristics after programming are guaranteed within this value (guaranteed value is from 1 to Min. value). 4. Characteristics when programming is performed within the Min. value. 5. Vcc=PLLVcc=2.95V to 3.60V in the H8SX/1658M Group.
29.9
Power-On Reset Circuit and Voltage-Detection Circuit Characteristics (H8SX/1658M Group)
Table 29.15 Power-On Reset Circuit and Voltage-Detection Circuit Characteristics Conditions: VCC = PLLVCC , Avcc = 3.0V to AVcc, VSS = PLLVSS = AVSS = 0 V, Ta = - 20C to +75C (regular specifications), Ta = - 40C to +85C (wide-range specifications)
Item Symbol Min. 3.00 2.48 20 200 Typ. 3.10 2.58 35 Max. 3.20 2.68 50 ms us Unit V Test Conditions Figure 29.44 Figure 29.43 Figure 29.43 Figure 29.44
Voltage detection Voltage detection Vdet circuit (LVD) level Power-on reset (POR) Internal reset time Power-off time* Note: * VPOR tPOR tVOFF
Power-off time (tVOFF) is the time over which Vcc is lower than minimum value of the voltage-detection level of the POR and LVD.
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Section 29 Electrical Characteristics
tVOFF VPOR
VCC
Internal reset signal ("L" is enabled)
tPOR
tPOR
Figure 29.43 Power-On Reset Timing
tVOFF Vdet
VCC
Internal reset signal ("L" is enabled)
tPOR
Figure 29.44 Voltage Detection Circuit Timing
Rev. 2.00 Sep. 25, 2008 Page 1294 of 1340 REJ09B0413-0200
Appendix
Appendix
A. Port States in Each Pin State
Port States in Each Pin State
Deep Software Standby Mode Hardware IOKEEP = 1/0 Standby Mode OPE = 1 OPE = 0 Hi-Z Hi-Z Hi-Z Hi-Z Keep Keep Hi-Z Hi-Z Keep Keep Hi-Z Hi-Z Bus Released State Keep Keep Keep Keep
Table A.1
MCU Operating Port Name Mode Reset Port 1 Port 2 P55 to P50 P56/ AN6/ DA0/ IRQ6-B P57/ AN7/ DA1/ IRQ7-B P65 to P60 PA0/ BREQO/ BS-A All All All All Hi-Z Hi-Z Hi-Z Hi-Z
Software Standby Mode OPE = 1 Keep Keep Hi-Z [DAOE0 = 1] Keep [DAOE0 = 0] Hi-Z OPE = 0 Keep Keep Hi-Z [DAOE0 = 1] Keep [DAOE0 = 0] Hi-Z [DAOE1 = 1] Keep [DAOE1 = 0] Hi-Z Keep [BREQO output] Hi-Z [BS output] Hi-Z [Other than above] Keep [BACK output] Hi-Z [RD/WR-A output] Hi-Z [Other than above] Keep
All
Hi-Z
Hi-Z
Hi-Z
Hi-Z
[DAOE1 = 1] Keep [DAOE1 = 0] Hi-Z
Keep
All All
Hi-Z Hi-Z
Hi-Z Hi-Z
Keep [BREQO output] Hi-Z [BS output] Keep [Other than above] Keep
Keep [BREQO output] Hi-Z [BS output] Hi-Z [Other than above] Keep [BACK output] Hi-Z [RD/WR-A output] Hi-Z [Other than above] Keep
Keep [BREQO output] Hi-Z [BS output] Keep [Other than above] Keep [BACK output] Hi-Z [RD/WR-A output] Keep [Other than above] Keep
Keep [BREQO output] BREQO [BS output] Hi-Z [Other than above] Keep [BACK output] BACK [RD/WR-A output] Hi-Z [Other than above] Keep
PA1/ All BACK/ (RD/WR-A)
Hi-Z
Hi-Z
[BACK output] Hi-Z [RD/WR-A output] Keep [Other than above] Keep
Rev. 2.00 Sep. 25, 2008 Page 1295 of 1340 REJ09B0413-0200
Appendix
Deep Software Standby Mode IOKEEP = 1/0 OPE = 0
Port Name PA2/ BREQ/ WAIT
MCU Operating Mode All
Reset Hi-Z
Hardware Standby Mode OPE = 1 Hi-Z
Software Standby Mode OPE = 1 OPE = 0
Bus Released State
[BREQ input] [BREQ input] [BREQ input] [BREQ input] [BREQ input] Hi-Z Hi-Z Hi-Z Hi-Z [WAIT -A input] Hi-Z [Other than above] Keep [WAIT -A input] Hi-Z [Other than above] Keep Keep [WAIT -A input] Hi-Z [Other than above] Keep Keep [WAIT -A input] Hi-Z [Other than above] Keep Keep Keep Hi-Z (BREQ) [WAIT -A input] Hi-Z (WAIT A)
PA3/ LLWR/ LLB
Single-chip mode (EXPE = 0) External extended mode (EXPE = 1)
Hi-Z
Hi-Z
Keep
H
Hi-Z
H
Hi-Z
H
Hi-Z
Hi-Z
PA4/ LHWR/ LUB
Single-chip mode (EXPE = 0) External extended mode (EXPE = 1)
Hi-Z
Hi-Z
Keep
Keep
Keep
Keep
Keep
H
Hi-Z
[LHWR, LUB [LHWR, LUB [LHWR, LUB [LHWR, LUB [LHWR, LUB output] output] output] output] output] H [Other than above] Keep Hi-Z [Other than above] Keep Keep H [Other than above] Keep Keep Hi-Z [Other than above] Keep Keep Hi-Z [Other than above] Keep Keep
PA5/RD
Single-chip mode (EXPE = 0) External extended mode (EXPE = 1)
Hi-Z
Hi-Z
Keep
H
Hi-Z
H
Hi-Z
H
Hi-Z
Hi-Z
PA6/ AS/ AH/ BS-B
Single-chip mode (EXPE = 0) External extended mode (EXPE = 1)
Hi-Z
Hi-Z
[AS, BS output] H [AH output] L [Other than above] Keep
[AS, AH, BS [AS, BS output] output] Hi-Z [Other than above] Keep H [AH output] L [Other than above] Keep
[AS, AH, BS output] Hi-Z [Other than above] Keep
[AS, AH, BS output] Hi-Z [Other than above] Keep
H
Hi-Z
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Appendix
Deep Software Standby Mode IOKEEP = 1/0 OPE = 0 [Clock output] H [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [CS output] Hi-Z [Other than above] Keep
Port Name PA7/B
MCU Operating Mode Single-chip mode (EXPE = 0) External extended mode (EXPE = 1)
Hardware Standby Reset Mode OPE = 1 Hi-Z Hi-Z [Clock output] H Clock Hi-Z output
Software Standby Mode OPE = 1 [Clock output] H [Other than above] Keep [CS output] H [Other than above] Keep [CS output] H [Other than above] Keep [CS output] H [Other than above] Keep [CS output] H [Other than above] Keep OPE = 0 [Clock output] H [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [CS output] Hi-Z [Other than above] Keep
Bus Released State [Clock output] Clock output [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [CS output] Hi-Z [Other than above] Keep [CS output] Hi-Z [Other than above] Keep
[Other than above] Keep
PB0/ CS0/ CS4/ CS5-B
Single-chip mode (EXPE = 0) External extended mode (EXPE = 1) All
Hi-Z
Hi-Z
[CS output] H [Other than above] Keep
H
Hi-Z
PB1/ CS1/ CS2-B/ CS5-A/ CS6-B/ CS7-B PB2/ CS2-A/ CS6-A
Hi-Z
Hi-Z
[CS output] H [Other than above] Keep
All
Hi-Z
Hi-Z
[CS output] H [Other than above] Keep
PB3/ CS3/ CS7-A
All
Hi-Z
Hi-Z
[CS output] H [Other than above] Keep
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Appendix
Port Name Port D
MCU Operating Mode External extended mode (EXPE = 1) ROM enabled extended mode
Reset L
Hardware Standby Mode OPE = 1 OPE = 0 Hi-Z Keep Hi-Z
Deep Software Standby Mode IOKEEP = 1/0
Software Standby Mode OPE = 1 OPE = 0 Keep Hi-Z
Bus Released State Hi-Z
Hi-Z
Hi-Z
Keep
[Address output] Hi-Z [Other than above] Keep
Keep
[Address output] Hi-Z
[Address output] Hi-Z
[Other than [Other than above] above] Keep Keep Keep Hi-Z Keep Keep Keep Hi-Z
Single-chip mode (EXPE = 0) Port E External extended mode (EXPE = 1) ROM enabled extended mode
Hi-Z L
Hi-Z Hi-Z
Keep Keep
Keep Hi-Z
Hi-Z
Hi-Z
Keep
[Address output] Hi-Z [Other than above] Keep
Keep
[Address output] Hi-Z
[Address output] Hi-Z
[Other than [Other than above] above] Keep Keep Keep Hi-Z Keep Keep Keep Hi-Z
Single-chip mode (EXPE = 0) PF3 to PF0 External extended mode (EXPE = 1) ROM enabled extended mode
Hi-Z L
Hi-Z Hi-Z
Keep Keep
Keep Hi-Z
Hi-Z
Hi-Z
Keep
[Address output] Hi-Z [Other than above] Keep
Keep
[Address output] Hi-Z
[Address output] Hi-Z
[Other than [Other than above] above] Keep Keep Keep [Address output] Hi-Z Keep Keep Keep [Address output] Hi-Z
Single-chip mode (EXPE = 0) PF4 External extended mode (EXPE = 1)
Hi-Z Hi-Z
Hi-Z Hi-Z
Keep Keep
Keep [Address output] Hi-Z [Other than above] Keep
[Other than [Other than above] above] Keep Keep Keep Keep Keep
Single-chip mode (EXPE = 0)
Hi-Z
Hi-Z
Keep
Keep
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Appendix
Port Name Port H
MCU Operating Mode Single-chip mode (EXPE = 0) External extended mode (EXPE = 1)
Reset Hi-Z Hi-Z
Deep Software Standby Mode Hardware IOKEEP = 1/0 Standby Mode OPE = 1 OPE = 0 Hi-Z Hi-Z Keep Hi-Z Keep Hi-Z
Bus Released Software Standby Mode State OPE = 1 Keep Hi-Z OPE = 0 Keep Hi-Z Keep Hi-Z
Port I
Single-chip mode (EXPE = 0) External extended mode (EXPE = 1)
Hi-Z
Hi-Z Hi-Z
Keep Keep
Keep Keep
Keep Keep
Keep Keep
Keep Keep
8-bit Hi-Z bus mode 16-bit Hi-Z bus mode Hi-Z Hi-Z Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Port J Port K Port M
Hi-Z Hi-Z Hi-Z
Hi-Z Hi-Z Hi-Z
Keep Keep Keep
Keep Keep Keep
Keep Keep Keep
Keep Keep Keep
Keep Keep Keep
[Legend] H: High-level output L: Low-level output Keep: Input pins become high-impedance, output pins retain their state. Hi-Z: High impedance
Rev. 2.00 Sep. 25, 2008 Page 1299 of 1340 REJ09B0413-0200
Appendix
B.
Product Lineup
Part No. R5F61653R R5F61654R R5F61658R R5F61653M R5F61654M R5F61658M Marking R5F61653RFPV R5F61654RFPV R5F61658RFPV R5F61653MFPV R5F61654MFPV R5F61658MFPV Package (Package Code) PLQP0120LA-A (FP-120BV)* PLQP0120LA-A (FP-120BV)* PLQP0120LA-A (FP-120BV)* PLQP0120LA-A (FP-120BV)* PLQP0120LA-A (FP-120BV)* PLQP0120LA-A (FP-120BV)*
Product Classification H8SX/1653R H8SX/1654R H8SX/1658R H8SX/1653M H8SX/1654M H8SX/1658M Note: * Pb-free version
Rev. 2.00 Sep. 25, 2008 Page 1300 of 1340 REJ09B0413-0200
C.
JEITA Package Code PLQP0120LA-A 120P6R-A / FP-120B / FP-120BV 0.7g
RENESAS Code
Previous Code
MASS[Typ.]
P-LQFP120-14x14-0.40
HD
*1 D 61
90
Package Dimensions
91
60
bp b1
E HE
*2
c1 c
NOTE) 1. DIMENSIONS "*1" AND "*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION "*3" DOES NOT INCLUDE TRIM OFFSET.
Terminal cross section
120
ZE
31
Reference Symbol
Dimension in Millimeters Min D E 13.9 13.9 A2 Nom 14.0 14.0 1.4 Max 14.1 14.1
1 30
ZD F
A A2
Index mark
c
HD HE A
A1
15.8 15.8 L L1
16.0 16.0
16.2 16.2 1.7 A1 bp b1 Detail F c c1 0 e x y ZD ZE L L1 0.35 1.2 1.2 0.5 1.0 0.65 0.4 0.07 0.08 0.09 0.05 0.13 0.1 0.18 0.16 0.145 0.125 8 0.20 0.15 0.23
For the package dimensions, data in the Renesas IC Package General Catalog has priority.
Figure C.1 Package Dimensions (FP-120BV)
*3 bp x
y
e
Appendix
Rev. 2.00 Sep. 25, 2008 Page 1301 of 1340
REJ09B0413-0200
Appendix
D.
Treatment of Unused Pins
The treatments of unused pins are listed in table D.1 Table D.1
Pin Name RES STBY EMLE MD_CLK MD2 to MD0 NMI EXTAL XTAL WDTOVF USD+ USD- VBUS Port 1 Port 2 Port 6 PA2 to PA0 PB3 to PB1 Port J Port K Port M Port 5 * Connect these pins to AVcc via a pull-up resistor or to AVss via a pull-down resistor, respectively
Treatment of Unused Pins
Mode 4 * * * Mode 5 Mode 6 Modes 3, 7
Connect this pin to VCC via a pull-up resistor* Connect this pin to VCC via a pull-up resistor Connect this pin to VSS via a pull-down resistor
(Always used as mode pins) (Always used as mode pins) * * * * * * * Connect this pin to VCC via a pull-up resistor
(Always used as a clock pin) Leave this pin open Leave this pin open Leave this pin open Leave this pin open Leave this pin open Connect these pins to VCC via a pull-up resistor or to VSS via a pull-down resistor, respectively
Rev. 2.00 Sep. 25, 2008 Page 1302 of 1340 REJ09B0413-0200
Appendix
Pin Name PA7 PA6 PA5 PA4 PA3 PB0 Port D Port E PF4 to PF0 Port H Port I
Mode 4 * * * * * * *
Mode 5
Mode 6
Modes 3,7 Connect these pins to VCC via a pull-up resistor or to VSS via a pulldown resistor, respectively
This pin is left open in the initial state for the B output. * This pin is left open in the initial state for the AS output. This pin is left open in the initial state for the RD output. This pin is left open in the initial state for the LHWR output. This pin is left open in the initial state for the LLWR output. This pin is left open in the initial state for the CS0 output. These pins are left open in the initial state for the address output.
(Used as a data bus) (Used as a data bus) * Connect these pins to VCC via a pull-up resistor or to VSS via a pulldown resistor, respectively, in the initial state for the general input.
Vref
*
Connect this pin to AVcc
Notes: 1. Do not change the initial value (input-buffer disabled) of PnICR, where n corresponds to an unused pin. 2. When the pin function is changed from its initial state, use a pull-up or pull-down resistor as needed. * Always used as a reset signal input pin in case of the H8SX/1658R Group.
Rev. 2.00 Sep. 25, 2008 Page 1303 of 1340 REJ09B0413-0200
Appendix
Rev. 2.00 Sep. 25, 2008 Page 1304 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Main Revisions and Additions in this Edition
Common revised items due to the version upgrade from Rev.1.00 to Rev.2.00.
Item All Page Revision (See Manual for Details) Group Name Added: H8SX/1656M Group
Rev. 2.00 Sep. 25, 2008 Page 1305 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item All
Page
Revision (See Manual for Details) Amended: Section and Figure numbers are amended due to the addition of the sections 5. Structure of the Rev. 2.00 1. Overview 2. CPU 3. MCU Operating Modes 4. Resets 5. Voltage Detection Circuit (LVD) 6. Exception Handling 7. Interrupt Controller 8. User Break Controller (UBC) 9. Bus Controller (BSC) 10. DMA Controller (DMAC) 11. EXDMA Controller (EXDMAC) 12. Data Transfer Controller (DTC) 13. I/O Ports 14. 16-Bit Timer Pulse Unit (TPU) 15. Programmable Pulse Generator (PPG) 16. 8-bit Timer 17. Watch Dog Timer (WDT) 18. Serial Communication Interface (SCI, IrDA, CRC) 19. USB Function Module (USB) 20. I2C Bus Interface 2 (IIC2) 21. A/D Converter 22. D/A Converter 23. RAM 24. Flash Memory 25. Boundary Scan 26. Clock Pulse Generator 27. Power-Down Modes 28. List of Registers 29. Electrical Characteristics Appendix
Rev. 2.00 Sep. 25, 2008 Page 1306 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item Section 1 Overview 1.1.2 Overview of Functions Table 1.1 Overview of Functions
Page 3
Revision (See Manual for Details) Amended Interrupt controller (INTC) * Number of internal interrupt sources H8SX/1658R Group: 120 pins H8SX/1658M Group 121 pins
1.4.2 Pin Assignments Table 1.3 Pin Configuration in Each Operating Mode (H8SX/1658R Group and H8SX/1658M Group) 1.4.3 Pin Functions Table 1.4 Pin Functions
18
Added Note below is added 2. Pins TDO, TRST, TMS, TDI, and TCK are enabled in mode 3.
19
Amended Pin name of address bus A20 to A0
21
Added EDRAK0 and EDRAK1 are added to EXDMA controller (EXDMAC)
24
Pin name and details of I/O ports PF4 to PF0 5 bit input/output pins Amended H'FEC000 to H'FEE000 of each mode [Before amendment] Access prohibited area [After amendment] Reserved area*3
Section 3 MCU Operating Modes 3.4.1 Address Map Figure 3.1 Address Map in Each Operating Mode of H8SX/1658R and H8SX/1658M (1) Figure 3.1 Address Map in Each Operating Mode of H8SX/1658R and H8SX1658M (2)
80
81
Amended and added H'FEC000 to H'FF2000 of each mode [Before amendment] Access prohibited area [After amendment] Reserved area*1 Note 1 is added.
Figure 3.2 Address Map in Each Operating Mode of H8SX/1654R and H8SX/1654M (1)
82
Amended H'FEC000 to H'FE2000 of each mode [Before amendment] Access prohibited area [After amendment] Reserved area*3
Rev. 2.00 Sep. 25, 2008 Page 1307 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item Figure 3.2 Address Map in Each Operating Mode of H8SX/1654R and H8SX/1654M (2)
Page 83
Revision (See Manual for Details) Added and amended H'FEC000 to H'FE2000 of each mode [Before amendment] Access prohibited area [After amendment] Reserved area*1 Note 1 is added
Figure 3.3 Address Map in Each Operating Mode of H8SX/1653R and H8sX/1653M (1) Figure 3.3 Address Map in Each Operating Mode of H8SX/1653R and H8SX/1653M (2)
84
Amended H'FEC000 to H'FF2000 of each mode [Before amendment] Access prohibited area [After amendment] Reserved area*3
85
Amended H'FEC000 to H'FF2000 of each mode [Before amendment] Access prohibited area [After amendment] Reserved area*1 Note 1 is added
Section 4 Reset 4.3.1 Reset Status Register (RSTSR)
90
Amended Description of Bit 7 [Before amendment] External interrupt source [After amendment] Interrupt source Amended Each description [Before amendment] DMAC [After amendment] DMAC, and EXDMAC.
Section 7 Interrupt Controller 127, 128 7.3.2 CPU priority control register (CPUPCR) 7.3.4 IRQ Enable Register (IER) 7.3.6 IRQ Status Register 131 138
Amended IER enables interrupt requests IRQ14, and IRQ11 to IRQ0 Amended Bit 14 [Before amendment] IRQn [After amendment] IRQ14
7.4.1 External Interrupts (1) NMI interrupt
141
Added * * Sets the ERRF bit of EDMDR_0 in the EXDMAC to 1 Clears the DTE bits of EDMDRs for all channels in the EXDMAC to 0 to forcibly terminate transfer
Rev. 2.00 Sep. 25, 2008 Page 1308 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 7.7 CPU Priority Control Function Over DTC, DMAC, and EXDMAC Table 7.8 Example of Priority Control Function Setting and Control State Section 10 DMA Controller (DMAC) 10.1 Features 10.3.5 DMA Block Size Register (DBSR)
Page 160
Revision (See Manual for Details) Replaced Replaced due to the addition of the description for the EXDMAC.
284
Added * Module stop state can be set.
292
Amended Bit table Initial Value of the Bit 31-16 and 15-0 [Before amendment] Undefined [After amendment] All 0
10.5.8 Priority of Channels Figure 10.22 Example of Timing for Channel Priority
336
Amended Positions of dotted lines have been corrected. Added Module stop state can be set. Amended
Interrupt controller
DTCERA to DTCERF
Section11 EXDMA Controller 362 (EXDMAC) 11.1 Features Section 12. Data Transfer Controller (DTC) Figure 12.1 Block Diagram of DTC 468
DTCCR
12.9.3 DMAC Transfer End Interrupt
500
Added When the DTC is activated by a DMAC transfer end interrupt, even if DISEL=0, an automatic clearing of the relevant activation source flag is not automatically cleared by the DTC. Therefore, write 1 to the DTE bit by the DTC transfer and clear the activation source flag to 0.
12.9.9 Points for Caution when Overwriting DTCER.
502
Added
Rev. 2.00 Sep. 25, 2008 Page 1309 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item Section 13 I/O Ports Table 13.1 Port Functions 13.1.1 Data Direction Register (PnDDR) (n = 1, 2, 6, A, B, D to F, H to K, and M)
Page 507 511
Revision (See Manual for Details) Amended CAS and RAS are deleted from the port B function. Added Notes on port B and port F are added.
13.1.2 Data Register (PnDR) 512 (n = 1, 2, 6, A, B, D to F, H to K, and M) 13.1.3 Port Register (PORTn) (n = 1, 2, 5, 6, A, B, D to F, H to K, and M) 13.1.4 Input Buffer Control 513 Register (PnICR) (n = 1, 2, 5, 6, A, B, D to F, H to K, and M) 13.1.5 Pull-up MOS Control Register (PnPCR) (n = D to F, and H to K) 13.2 Output Buffer Control 13.2.5 Port A 514
Added Notes on port B and port F are added. Added Notes on port B and port F are added. Added Notes on port B and port F are added.
Added Note on port F is added.
528
Amended (2) PA6/AS/AH/BS-B Setting of I/O Port [Before amendment] BSB_OE [After amendment] BS-B_OE
531
(8) PA0/BREQO/BS-A Setting of I/O Port [Before amendment] BSA)_OE [After amendment] BS-A_OE.
13.2.6 Port B
532
Deleted (1) PB3/CS3/CS7-A CAS is deleted (2) PB2/CS2-A/CS6-A RAS is deleted
Table 13.5 Available Output 550 Signals and Settings in Each Port
Replaced Replaced due to the correction of an error
Rev. 2.00 Sep. 25, 2008 Page 1310 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 13.3.2 Port Function Control Register 1 (PFCR1)
Page 559
Revision (See Manual for Details) Amended Descriptions for bits 7,6,5, and 4 [Before amendment] Specifies pin PB6 as CS6-D output [After amendment] Setting prohibited [Before amendment] Specifies pin PB5 as CS5-D output [After amendment] Setting prohibited
13.3.3 Port Function Control Register 2 (PFCR2) 13.3.4 Port Function Control Register B (PFCR4) 13.3.6 Port Function Control Register (PFCR7)
561 562 564
Amended Bit 3 has been amended to the reserved bit Amended Bits 7 to 5 have been amended to the reserved bits Amended Descriptions for bits 5,4,3, and 2 [Before amendment] Setting prohibited [After amendment] Setting invalid
13.3.7 Port Function Control Register 8 (PFCR8)
565
Amended [Before amendment] EDMAC [After amendment] EXDMAC Amended
Item Channel 0 Input capture function O Channel 1 O Channel 2 Channel 3 O Channel 4 O Channel 5 O
Section 14 16-Bit Timer Pulse 576 Unit (TPU) 14.1 Features Table 14.1 TPU (Unit 0) Functions
14.1 Features Figure 14.1 Block Diagram of TPU (Unit 0)
580
Deleted Channels 0 to 2 are deleted from the [Input/output pins]
Rev. 2.00 Sep. 25, 2008 Page 1311 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item
Page
Revision (See Manual for Details) Amended
TIORH TIORL TMDR
Figure 14.2 Block Diagram of 581 TPU (Unit 1)
Channel 9
TSR
TMDR
Control logic for channels 9 to 11
Channel 10
TSR
TIER
TCR
TIOR
TMDR
Channel 11
TSR
TIER
TCR
TGRA
TIOR
14.3.3 Timer I/O Control Register (TIOR)
597
Amended Bit tables of registers are amended as shown below. TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5 (Unit 0) TIORH_6, TIOR_7, TIOR_8, TIORH_9, TIOR_10, TIOR_11 (Unit 1) * * TIORL_0, TIORL_3 (Unit 0) TIORL_6, TIORL_9 (Unit 1)
598 to Added and amended 629 Tables 14.14 to 14.45 Section17. Watchdog Timer (WDT) 17.3.2 Reset Control/Status Register (RSTCSR) Section 20 I2C Bus Interface 2 (IIC2) 20.1 Features
Rev. 2.00 Sep. 25, 2008 Page 1312 of 1340 REJ09B0413-0200
756
Deleted Description below for bit 7 is deleted (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
931
Added Module stop state can be set.
TIER
TCR
TGRA
TGRB
TCNT
TGRB
TCNT
TGRC
TGRD
TGRA
TGRB
TCNT
Main Revisions and Additions in this Edition
Item 20.3.5 I C Bus Status Register (ICSR)
2
Page 945
Revision (See Manual for Details) Deleted The description below for the bit 1 is deleted: [Clearing condition] When 0 is written to this bit after reading AAS = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
946
Deleted The description below for the bit 0 is deleted: [Clearing condition] When 0 is written to this bit after reading ADZ = 1 (When the CPU is used to clear this flag by writing 0 while the corresponding interrupt is enabled, be sure to read the flag after writing 0 to it.)
20.7 Usage Notes Section 21 A/D Converter 21.3.2 A/D Control/Status Register for Unit 0 (ADCSR_0)
964 971
Added 6. Setting of the module stop function Added Descriptions for bit 5 in the register table: Note: Do not write to ADST when activation is by an external trigger. For details, see section 21.7.3, Notes on A/D activation by an External Trigger.
21.3.3 A/D Control/Status Register for Unit 1 (ADCSR_1)
973
Added Descriptions for bit 5 in the register table: Note: Do not write to ADST when activation is by an external trigger. For details, see section 21.7.3, Notes on A/D activation by an External Trigger. Amended and added The description for bit 7,6, and 0 in the register table: 001: External trigger disabled Note: Do not write to ADST when activation is by an external trigger. For details, see section 21.7.3, Notes on A/D activation by an External Trigger.
21.3.4 A/D Control/Status 975 Register for Unit 2 (ADCR_0) Unit 0
Rev. 2.00 Sep. 25, 2008 Page 1313 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 21.3.5 A/D Control Register (ADCR_1) Unit 1
Page 977
Revision (See Manual for Details) Amended and added Descriptions for bits 7,6, and 0 in the register table: 001: External trigger disabled Note: Do not write to ADST when activation is by an external trigger. For details, see section 21.7.3, Notes on A/D activation by an External Trigger.
21.4.3 Input Sampling and A/D Conversion Time
984
Replaced Table 21.3 A/D Conversion Characteristics (EXCKS = 0) Table 21.4 A/D Conversion Characteristics (EXCKS = 1: Unit 1)
21.7 Usage Notes Section 22 D/A Converter 22.5.2 D/A Output Hold Function in Software Standby Mode 22.5.3 Notes on Deep Software Standby Mode Section 24 Flash Memory 24.7.1 Programming/Erasing Interface Registers
990 1000
Added 21.7.3 Notes on A/D Activation by an External Trigger Amended When this LSI makes a transition to software standby mode with D/A conversion enabled, the D/A outputs are retained, Added
1018
Added Bit 0 R/W* Note: This is a write-only bit. This bit is always read as 0. Amended FPEFEQ sets the operating frequency of the CPU. The operating frequency available in this LSI ranges from 8 MHz to 50 MHz.
24.7.2 Programming/Erasing 1030 Interface Parameters (3) Flash Program/Erase Frequency Parameter (FPEFEQ: General Register ER0 of CPU)
Rev. 2.00 Sep. 25, 2008 Page 1314 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 24.14 Usage Notes
Page 1100
Revision (See Manual for Details) Amended 5. Do not turn off the Vcc power supply nor remove the chip from the PROM programmer during programming/erasure in which a high voltage is applied to the flash memory. Doing so may damage the flash memory permanently. If a reset is input, the reset must be released after the reset input period of at least 100s. Amended 7. At powering on the Vcc power supply, fix the RES pin to low and set the flash memory to hardware protection state. This power on timing must also be satisfied at a power-off and power-on caused by a power failure and other factors.
Section 27 Power-Down Modes
1131
Deleted Table 27.1, Notes:4 However, outputs from pins are disabled even if the operation is selected.
27.2.4 Deep Standby Control 1140 Register (DPSBYCR)
Deleted DPSBYCR controls deep software standby mode. DPSBYCR is initialized by input of the reset signal on the RES pin, but is not initialized by the internal reset signal upon exit from deep software standby mode.
1142
Amended Descriptions for bit 5 in the register table: RAMCUT 2, 1, and 0 control the internal power supply to the on-chip RAM and USB in deep software standby mode. For details, see descriptions of the RAMCUT0 bit Amended Descriptions for bit 4 in the register table: RAMCUT 2, 1, and 0 control the internal power supply to the on-chip RAM in deep software standby mode.
Rev. 2.00 Sep. 25, 2008 Page 1315 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item
Page
Revision (See Manual for Details) Amended Descriptions for bit 0 in the register table: RAMCUT 2, 1, and 0 control the internal power supply to the on-chip RAM in deep software standby mode.
27.2.4 Deep Standby Control 1142 Register (DPSBYCR)
27.2.5 Deep Standby Wait Control Register (DPSWCR)
1143
Deleted DPSWCR is initialized by input of the reset signal on the RES pin, but is not initialized by the internal reset signal upon exit from deep software standby mode.
27.2.6 Deep Standby Interrupt Enable Register (DPSIER)
1145
Deleted DPSIER enables or disables interrupts to clear deep software standby mode. DPSIER is initialized by input of the reset signal on the RES pin, but is not initialized by the internal reset signal upon exit from deep software standby mode.
1146
Amended Descriptions for bit 3 in the register table: Enables or disables exit from deep software standby mode by IRQ3-A. 0: Disables exit from deep software standby mode by IRQ3-A. 1: Enables exit from deep software standby mode by IRQ3-A.
Rev. 2.00 Sep. 25, 2008 Page 1316 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 27.2.6 Deep Standby Interrupt Enable Register (DPSIER)
Page 1146
Revision (See Manual for Details) Amended Descriptions for bit 2 in the register table: Enables or disables exit from deep software standby mode by IRQ2-A. 0: Disables exit from deep software standby mode by IRQ2-A. 1: Enables exit from deep software standby mode by IRQ2-A. Amended Descriptions for bit 1 in the register table: Enables or disables exit from deep software standby mode by IRQ1-A. 0: Disables exit from deep software standby mode by IRQ1-A. 1: Enables exit from deep software standby mode by IRQ1-A. Amended Descriptions for bit 0 in the register table: Enables or disables exit from deep software standby mode by IRQ0-A. 0: Disables exit from deep software standby mode by IRQ0-A. 1: Enables exit from deep software standby mode by IRQ0-A.
27.2.7 Deep Standby Interrupt Flag Register (DPSIFR)
1147
Amended DPSIFR is not initialized by the internal reset signal upon exit from deep software standby mode.
1148
Descriptions for bit 3 R/W in the register table R/(W)*1 IRQ3-A input specified in DPSIEGR is generated. Descriptions for bit 2 R/W in the register table R/(W)*1 IRQ2-A input specified in DPSIEGR is generated. Descriptions for bit 1 R/W in the register table R/(W)*1 IRQ1-A input specified in DPSIEGR is generated.
Rev. 2.00 Sep. 25, 2008 Page 1317 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 27.2.7 Deep Standby Interrupt Flag Register (DPSIFR 27.2.8 Deep Standby Interrupt Edge Register (DPSIEGR)
Page 1148
Revision (See Manual for Details) Descriptions for bit 0 R/W in the register table R/(W)*1 IRQ0-A input specified in DPSIEGR is generated.
1149
Amended DPSIEGR is not initialized by the internal reset signal upon exit from deep software standby mode. Descriptions for bit 3 in the register table Selects the active edge for IRQ3-A pin input. Descriptions for bit 2 in the register table Selects the active edge for IRQ2 pin input. Descriptions for bit 1 in the register table Selects the active edge for IRQ1 pin input.
1150 27.2.9 Reset Status Register 1150 (RSTSR) 27.2.10 Deep Standby 1151 Backup Register (DPSBKRn) 27.9.4 Timing Sequence at Power-On 1172
Descriptions for bit 0 in the register table Selects the active edge for IRQ0-A pin input. RSTSR is not initialized by the internal reset signal upon exit from deep software standby mode. Amended DPSBKRn (n=15 to 0) is not initialized by the internal reset signal upon exit from deep software standby mode. Amended Figure 27.9 shows the timing sequence at power-on. At power-on, the RES pin must be driven low with the STBY pin driven high for a given time in order to clear the reset state.
Rev. 2.00 Sep. 25, 2008 Page 1318 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item Section 28. List of Registers 28.1 Register Addresses (Address Order)
Page 1183
Revision (See Manual for Details) Added
Access Cycles Number Register Name Abbreviation of Bits Address Module Data Width (Read/ Write)
Break address register AH Break address register AL Break address mask register AH Break address mask register AL Break address register BH Break address register BL Break address mask register BH Break address mask register BL Break address register CH Break address register CL Break address mask register CH Break address mask register CL Break address register DH Break address register DL Break address mask register DH Break address mask register DL Break control register A Break control register B
BARAH BARAL BAMRAH BAMRAL BARBH BARBL BAMRBH BAMRBL BARCH BARCL BAMRCH BAMRCL BARDH BARDL BAMRDH BAMRDL BRCRA BRCRB
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
H'FFA00 H'FFA02 H'FFA04 H'FFA06 H'FFA08
UBC UBC UBC UBC UBC
16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16
2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I 2I/2I
H'FFA0A UBC H'FFA0C UBC H'FFA0E UBC H'FFA10 H'FFA12 H'FFA14 H'FFA16 H'FFA18 UBC UBC UBC UBC UBC
H'FFA1A UBC H'FFA1C UBC H'FFA1E UBC H'FFA28 UBC
H'FFA2C UBC H'FFA30 H'FFA34 UBC UBC
Break control register C BRCRC Break control register D BRCRD
Rev. 2.00 Sep. 25, 2008 Page 1319 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 28.2 Register Bits
Page 1203
Revision (See Manual for Details) Amended List of register bits
Register Abbreviation BARAH Bit 31/23/1 5/7 BARA3 1 BARA2 3 BARAL BARA1 5 BARA7 BAMRAH Bit 30/22/1 4/6 BARA3 0 BARA2 2 BARA1 4 BARA6 Bit 29/21/1 3/5 BARA2 9 BARA2 1 BARA1 3 BARA5 Bit 28/20/1 2/4 BARA2 8 BARA2 0 BARA1 2 BARA4 Bit 27/19/1 1/3 BARA2 7 BARA1 9 BARA1 1 BARA3 Bit 26/18/1 0/2 BARA2 6 BARA1 8 BARA1 0 BARA2 BARA1 BARA0 Bit Bit 25/17/9/ 24/16/8/ 1 BARA2 5 BARA1 7 BARA9 0 BARA2 4 BARA1 6 BARA8
Module
UBC
BAMRA BAMRA BAMRA BAMRA BAMRA BAMRA BAMRA BAMRA 31 30 29 28 27 26 25 24
BAMRA BAMRA BAMRA BAMRA BAMRA BAMRA BAMRA BAMRA 23 BAMRAL 22 21 20 19 18 17 16
BAMRA BAMRA BAMRA BAMRA BAMRA BAMRA BAMRA BAMRA 15 14 13 12 11 10 9 8
BAMRA BAMRA BAMRA BAMRA BAMRA BAMRA BAMRA BAMRA 7 BARBH BARB3 1 BARB2 3 BARBL BARB1 5 BARB7 BAMRBH 6 BARB3 0 BARB2 2 BARB1 4 BARB6 5 BARB2 9 BARB2 1 BARB1 3 BARB5 4 BARB2 8 BARB2 0 BARB1 2 BARB4 3 BARB2 7 BARB1 9 BARB1 1 BARB3 2 BARB2 6 BARB1 8 BARB1 0 BARB2 BARB1 BARB0 1 BARB2 5 BARB1 7 BARB9 0 BARB2 4 BARB1 6 BARB8
BAMRB BAMRB BAMRB BAMRB BAMRB BAMRB BAMRB BAMRB 31 30 29 28 27 26 25 24
BAMRB BAMRB BAMRB BAMRB BAMRB BAMRB BAMRB BAMRB 23 BAMRBL 22 21 20 19 18 17 16
BAMRB BAMRB BAMRB BAMRB BAMRB BAMRB BAMRB BAMRB 15 14 13 12 11 10 9 8
BAMRB BAMRB BAMRB BAMRB BAMRB BAMRB BAMRB BAMRB 7 BARCH BARC3 1 BARC2 3 6 BARC3 0 BARC2 2 5 BARC2 9 BARC2 1 4 BARC2 8 BARC2 0 3 BARC2 7 BARC1 9 2 BARC2 6 BARC1 8 1 BARC2 5 BARC1 7 0 BARC2 4 BARC1 6
Rev. 2.00 Sep. 25, 2008 Page 1320 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 28.2 Register Bits
Page 1203, 1204
Revision (See Manual for Details) Added (Continued from the previous page.)
Register Abbreviati on BARCL Bit 31/23/1 5/7 BARC1 5 BARC7 BAMRCH Bit 30/22/1 4/6 BARC1 4 BARC6 Bit 29/21/1 3/5 BARC1 3 BARC5 Bit 28/20/1 2/4 BARC1 2 BARC4 Bit 27/19/1 1/3 BARC1 1 BARC3 Bit 26/18/1 0/2 BARC1 0 BARC2 BARC1 BARC0 Bit 1 BARC9 Bit 0 BARC8 Module UBC 25/17/9/ 24/16/8/
BAMRC BAMRC BAMRC BAMRC BAMRC BAMRC BAMRC BAMRC 31 30 29 28 27 26 25 24
BAMRC BAMRC BAMRC BAMRC BAMRC BAMRC BAMRC BAMRC 23 BAMRCL 22 21 20 19 18 17 16
BAMRC BAMRC BAMRC BAMRC BAMRC BAMRC BAMRC BAMRC 15 14 13 12 11 10 9 8
BAMRC BAMRC BAMRC BAMRC BAMRC BAMRC BAMRC BAMRC 7 BARDH BARD3 1 BARD2 3 BARDL BARD1 5 BARD7 BRCRA 6 BARD3 0 BARD2 2 BARD1 4 BARD6 5 BARD2 9 BARD2 1 BARD1 3 BARD5 CMFCP A BRCRB IDA1 CMFCP B BRCRC IDB1 CMFCP C BRCRD IDC1 DMFCP D IDD1 IDD0 RWD1 RWD0 IDC0 * RWC1 CPD2 RWC0 CPD1 CPD0 IDB0 RWB1 CPC2 RWB0 CPC1 CPC0 IDA0 RWA1 CPB2 RWA0 CPB1 CPB0 4 BARD2 8 BARD2 0 BARD1 2 BARD4 3 BARD2 7 BARD1 9 BARD1 1 BARD3 CPA2 2 BARD2 6 BARD1 8 BARD1 0 BARD2 CPA1 BARD1 CPA0 BARD0 1 BARD2 5 BARD1 7 BARD9 0 BARD2 4 BARD1 6 BARD8
Rev. 2.00 Sep. 25, 2008 Page 1321 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 28.2 Register Bits
Page 1208
Revision (See Manual for Details) Added
Register Abbrevi ation Bit 31/23/1 5/7 Bit 30/22/1 4/6 BKUP0 6 BKUP1 6 BKUP2 6 BKUP3 6 BKUP4 6 BKUP5 6 BKUP6 6 BKUP7 6 BKUP8 6 BKUP9 6 BKUP1 06 BKUP1 16 BKUP1 26 BKUP1 36 BKUP1 46 BKUP1 56 Bit 29/21/1 3/5 BKUP0 5 BKUP1 5 BKUP2 5 BKUP3 5 BKUP4 5 BKUP5 5 BKUP6 5 BKUP7 5 BKUP8 5 BKUP9 5 BKUP1 05 BKUP1 15 BKUP1 25 BKUP1 35 BKUP1 45 BKUP1 55 Bit 28/20/1 2/4 BKUP0 4 BKUP1 4 BKUP2 4 BKUP3 4 BKUP4 4 BKUP5 4 BKUP6 4 BKUP7 4 BKUP8 4 BKUP9 4 BKUP1 04 BKUP1 14 BKUP1 24 BKUP1 34 BKUP1 44 BKUP1 54 Bit 27/19/1 1/3 BKUP0 3 BKUP1 3 BKUP2 3 BKUP3 3 BKUP4 3 BKUP5 3 BKUP6 3 BKUP7 3 BKUP8 3 BKUP9 3 BKUP1 03 BKUP1 13 BKUP1 23 BKUP1 33 BKUP1 43 BKUP1 53 Bit 26/18/1 0/2 BKUP0 2 BKUP1 2 BKUP2 2 BKUP3 2 BKUP4 2 BKUP5 2 BKUP6 2 BKUP7 2 BKUP8 2 BKUP9 2 BKUP1 02 BKUP1 12 BKUP1 22 BKUP1 32 BKUP1 42 BKUP1 52 Bit Bit 25/17/9/ 24/16/8/ 1 BKUP0 1 BKUP1 1 BKUP2 1 BKUP3 1 BKUP4 1 BKUP5 1 BKUP6 1 BKUP7 1 BKUP8 1 BKUP9 1 BKUP1 01 BKUP1 11 BKUP1 21 BKUP1 31 BKUP1 41 BKUP1 51 0 BKUP0 0 BKUP1 0 BKUP2 0 BKUP3 0 BKUP4 0 BKUP5 0 BKUP6 0 BKUP7 0 BKUP8 0 BKUP9 0 BKUP1 00 BKUP1 10 BKUP1 20 BKUP1 30 BKUP1 40 BKUP1 50 Module SYSTEM
DPSBKR BKUP0 0 7
DPSBKR BKUP1 1 7
DPSBKR BKUP2 2 7
DPSBKR BKUP3 3 7
DPSBKR BKUP4 4 7
DPSBKR BKUP5 5 7
DPSBKR BKUP6 6 7
DPSBKR BKUP7 7 7
DPSBKR BKUP8 8 7
DPSBKR BKUP9 9 7
DPSBKR BKUP1 10 07
DPSBKR BKUP1 11 17
DPSBKR BKUP1 12 27
DPSBKR BKUP1 13 37
DPSBKR BKUP1 14 47
DPSBKR BKUP1 15 57
1220
Amended
Register Abbreviatio n Bit Bit Bit Bit Bit Bit Bit Bit 31/23/15/ 30/22/14/ 29/21/13/ 28/20/12/ 27/19/11/ 26/18/10/ 25/17/9/1 24/16/8/0 7 6 5 4 3 2
SCKCR
PSTOP PSTOP -- 1 -- 0*3 PCK2 PCK1
--
--
ICK2
ICK1
ICK0
PCK0
--
BCK2
BCK1
BCK0
Rev. 2.00 Sep. 25, 2008 Page 1322 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 28.3 Register States in Each Operating Mode
Page 1201
Revision (See Manual for Details) Added
Bit Register Abbreviation 31/23/15/ 7 Bit 30/22/14/ 6 Bit 29/21/13/ 5 Bit 28/20/12/ 4 Bit 27/19/11/ 3 Bit 26/18/10/ 2 Bit 25/17/9/ 1
PORTM*
2

28.3 Register States in Each Operating Mode
1233
Added
AllModul Modul Register Abbreviation BARAH BARAL BAMRAH BAMRAL BARBH BARBL BAMRBH BAMRBL BARCH BARCL BAMRCH BAMRCL BARDH BARDL BAMRDH BAMRDL BRCRA BRCRB BRCRC BRCRD Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized e Stop State Sleep eClockStop Softwar e Deep Software Hardware Standby Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Module UBC
Standby Standby Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1 Initialized*1
Rev. 2.00 Sep. 25, 2008 Page 1323 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 28.3 Register States in Each Operating Mode
Page 1237, 1238
Revision (See Manual for Details) Added
AllModul Module Register Abbreviation Reset DPSBKR0 DPSBKR1 DPSBKR2 DPSBKR3 DPSBKR4 DPSBKR5 DPSBKR6 DPSBKR7 DPSBKR8 DPSBKR9 DPSBKR10 DPSBKR11 DPSBKR12 DPSBKR13 DPSBKR14 DPSBKR15 Stop State Sleep eClockStop Softwa re Standb y Deep Software Standby Hardware Standby Module SYSTEM
Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized -- Initialized --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized
28.3 Register States in Each Operating Mode
1242
Amended
AllModule Register Abbreviation Reset DPSBYCR DPSWCR Stop State Sleep Module -ClockStop Deep Software Software Standby Standby Hardware Standby Module SYSTEM
Initialized -- Initialized -- Initialized -- Initialized -- Initialized --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
-- -- -- -- --
Initialized Initialized Initialized Initialized Initialized
DPSIER DPSIFR
DPSIEGR
Rev. 2.00 Sep. 25, 2008 Page 1324 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item Section 29 Electrical Characteristics Table 29.2 DC Characteristics (2)
Page 1251
Revision (See Manual for Details) Amended
Test Item Supply current*
2
Symbol Normal operation Sleep mode Hardware Standby standby mode mode ICC*
4
Min.
Typ. 50 48 2
Max. 85 60 7
Unit mA
Conditions f = 50 MHz
A
Ta 50C
25
50C < Ta
Rev. 2.00 Sep. 25, 2008 Page 1325 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Items revised or amended due to the addition of the H8SX/1658M Group
Item All Page Revision (See Manual for Details) Added The functions for H8SX/1658M Group Details are noted as below: Note * : Supported only by the H8SX/1658M Group. All Added Below is the section added and those functions are added to the corresponding sections due to the addition of modules. (1) Section 5 Voltage Detection Circuit (LVD) Cover i Replaced Product names due to the addition of theH8SX1658M Group How to Use This Manual Section 1 Overview 1.1 Features 1.1.2 Overview of Functions 2 8 Replaced Table 1.1 Overview of Functions Added Table 1.2 Comparison of Support Functions in the H8SX/1658R Group and 1658M Group 1.2 List of Products 9 Replaced Table 1.3 List of Products Figure 1.1 How to Read the Product Name Code v 1 Replaced Name of groups: H8SX1658M Group Replaced
Rev. 2.00 Sep. 25, 2008 Page 1326 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 1.3 Block Diagram 1.4.2 Correspondence between Pin Configuration and Operating Modes Section 3 MCU Operating Modes 3.4.1 Address Map
Page 11 13
Revision (See Manual for Details) Replaced Figure 1.2 Block Diagram Replaced Table 1.3 Pin Configuration in Each Operating Mode (H8SX/1658R Group and H8SX/1658M Group)
79 80
Replaced Replaced Figure 3.1 Address Map in Each Operating Mode of H8SX/1658R and 1658M (1)
81 82 83 84 85 Section 4 Reset 4.1 Types of Reset
Figure 3.1 Address Map in Each Operating Mode of H8SX/1658R and H8SX/1658M (2) Figure 3.2 Address Map in Each Operating Mode of H8SX/1654R and H8SX/1654M (1) Figure 3.2 Address Map in Each Operating Mode of H8SX/1654R and H8SX/1654M (2) Figure 3.3 Address Map in Each Operating Mode of H8SX/1653R and 1653M (1) Figure 3.3 Address Map in Each Operating Mode of H8SX/1653R and 1653M (2) Table 4.1 Reset Names And Sources Figure 4.1 Block Diagram of Reset Circuit Replaced due to the addition of the power-on reset and voltage-monitoring reset.
87, 88 Replaced
4.3.1 Reset Status Register (RSTSR) 4.5 Power-on Reset (POR) (H8SX/1658M Group)
90, 91 Replaced Replaced due to the addition of the power-on reset and voltage-monitoring reset. 93 Added Added due to the addition of the power-on reset. Added Added due to the addition of the power supply monitoring reset. Replaced Replaced due to the addition of the power supply monitoring reset.
4.6 Power Supply Monitoring 94 Reset (H8SX/1658M Group) 4.9 Determination of Reset Generation Source 95
Rev. 2.00 Sep. 25, 2008 Page 1327 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item
Page
Revision (See Manual for Details) Replaced Table 6.7 Interrupt Sources Replaced due to the addition of the LVD Replaced Figure 7.1 Block Diagram of Interrupt Controller Replaced due to the addition of the LVD.
Section 6 Exception Handling 116 6.6.1 Interrupt Sources Section 7 Interrupt Controller 124 7.1 Features 7.3 Register Descriptions 7.3.4 IRQ Enable Register (IER) 7.3.5 IRQ Sense Control Registers H and L (ISCRH, ISCRL) 7.3.6 IRQ Status Register (ISR) 7.5 Interrupt Exception Handling Vector Table 131, 132
Replaced Replaced due to the addition of the LVD.
133 to Replaced 137 Replaced due to the addition of the LVD. 138, 139 Replaced Replaced due to the addition of the LVD.
143 to Replaced 148 Table 7.2 Interrupt Sources, Vector Address Offsets, and Interrupt Priority Replaced due to the addition of the LVD.
Section 13. I/O Ports
569, 13.3.10 Port Function Control 570 Register B (PFCRB) 23. RAM 24. Flash Memory 24.1 Features Section 27. Power-Down Modes 27.1 Features 1130 to 1132 1001, 1002 1003
Replaced Replaced due to the addition of the LVD. Replaced Replaced due to the addition of the H8SX/1658M Group Replaced * ROM size Replaced due to the addition of the H8SX/1658M Group Replaced Table 27.1 States of Operation Figure 27.1 (1) Mode Transitions Replaced due to the addition of the LVD. Added Bit 5 and Bit 4 Added due to the addition of the LVD.
27.2.6 Deep Standby Interrupt Enable Register (DPSIER)
1145
Rev. 2.00 Sep. 25, 2008 Page 1328 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 27.2.7 Deep Standby Interrupt Flag Register (DPSIFR)
Page 1147, 1148
Revision (See Manual for Details) Replaced Replaced due to the addition of the LVD. Added * * H8SX1658R Group H8SX1658M Group
27.2.9 Reset Status Register 1151 (RSTSR)
Added due to the addition of the LVD. 27.5.2 Exit from Sleep Mode 1153 Replaced Replaced due to the addition of the LVD and power-on reset. 27.6 All-Module-Clock-Stop Mode 27.7.2 Exit from Software Standby Mode 1154 1155 Replaced Replaced due to the addition of the LVD. Replaced 1. Exit from software standby mode by interrupt Replaced due to the addition of the 32K timer, voltagemonitoring reset, and power-on reset. Added 2. Exit from voltage monitoring reset*2 3. Exit from power-on reset*2 Replaced due to the addition of the voltage monitoring reset and power on reset. 27.8.1 Entry to Deep Software Standby Mode 27.8.2 Exit from Deep Software Standby Mode 1159 1160 Replaced Replaced due to the addition of the LVD. Replaced 1. Exit from software standby mode by interrupt Replaced due to the addition of the LVD. Added 2. Exit from voltage monitoring reset* 3. Exit from power-on reset*2 Added due to the addition of the voltage monitoring reset and power-on reset. 27.9.4 Timing Sequence at Power-On 1172 Replaced Replaced due to the addition of the power-on reset.
2
Rev. 2.00 Sep. 25, 2008 Page 1329 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 27.12.7 Conflict between a transition to deep software standby mode and interrupts Section 28 List of Registers 28.1 Register Addresses (Address Order)
Page 1178
Revision (See Manual for Details) Replaced Replaced due to the addition of the voltage monitoring interrupt.
1192
Added
Data Number of Register Name Low voltage detection control register*
2
Widt Address H'FFE78 Module h SYSTE M 8
Access Cycles (Read/Write) 2I/3I
Abbreviation LVDCR
Bits 8
Added due to the addition of the LVD. 28.2 Register Bits 1221 Added
Register Abbreviati on LVDCR*
3
Bit 31/23/1 5/7 LVDE
Bit 30/22/1 4/6 LVDRI
Bit 29/21/1 3/5
Bit 28/20/1 2/4 LVDMO N
Bit 27/19/1 1/3
Bit 26/18/1 0/2
Bit 25/17/9/ 1
Bit 24/16/8/ 0 Module SYSTE M
Added due to the addition of the LVD. 28.3 Register States in Each Operating Mode 1242 Added
AllModule Register Abbreviation Reset LVDCR*
3
Softwar e Standb y Deep Software Standby Hardwar e Standby Module
ModuleSlee p ClockStop
Stop State
Initialize d*
4
Initialized SYSTEM
Added due to the addition of the LVD. Section 29 Electrical Characteristics 29.2 DC Characteristics, H8SX/1658R Group 29.3 DC Characteristics H8SX/1658M Group 1250 to 1253 1254 to 1256 Replaced Replaced due to the addition of the H8SX/1658M Group.
Added Added due to the addition of the H8SX/1658M Group
Rev. 2.00 Sep. 25, 2008 Page 1330 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item 29.4.AC Characteristics 29.4.1 Clock Timing
Page 1257 1258
Revision (See Manual for Details) Replaced Replaced due to the addition of the H8SX/1658M Group. Replaced Table 29.6 Conditions of Clock Timing Replaced due to the addition of the H8SX/1658M Group.
29.4.2 Control Signal Timing
1261
Replaced Table 29.7 Conditions of Control Signal Timing Replaced due to the addition of the H8SX/1658M Group.
29.4.3 Bus Timing
1262 to 1264
Replaced Table 29.8 Conditions of Bus Timing (1) Table 29.8 Conditions of Bus Timing (2) Replaced due to the addition of the H8SX/1658M Group. Replaced Table 29.9 DMAC/EXDMAC Timing Added due to the addition of the H8SX/1658M Group.
29.4.4 Timing
DMAC/EXDMAC
1277
29.4.5 Timing of On-Chip Peripheral Modules
1292 to 1284 1289
Replaced Table 29.10 Timing of On-Chip Peripheral Modules Added due to the addition of the H8SX/1658M Group. Replaced Table 29.11 USB Characteristics when On-Chip USB Transceiver is Used (USD+, USD- pin characteristics) Added due to the addition of the H8SX/1658M Group.
29.5 USB Characteristics
29.6 A/D Conversion Characteristics
1291
Replaced Table 29.12 A/D Conversion Characteristics Added due to the addition of the H8SX/1658M Group.
29.7 D/A Conversion Characteristics
1291
Replaced Table 29.13 D/A Conversion Characteristics Added due to the addition of the H8SX/1658M Group.
29.8 Flash Memory Characteristics
1292 to 1293
Replaced Added due to the addition of the H8SX/1658M Group.
Rev. 2.00 Sep. 25, 2008 Page 1331 of 1340 REJ09B0413-0200
Main Revisions and Additions in this Edition
Item
Page
Revision (See Manual for Details) Added Added due to the addition of the H8SX/1658M Group.
29.9 Power-On Reset Circuit 1293 and Voltage-Detection Circuit Characteristics (H8SX/1658M Group) Appendix B. Product Lineup D. Treatment of Unused Pins 1302, 1303 1300
Replaced Replaced due to the addition of the H8SX/1658M Group Replaced Replaced due to the addition of the H8SX/1658M Group
Rev. 2.00 Sep. 25, 2008 Page 1332 of 1340 REJ09B0413-0200
Index
Numerics
0 output/1 output..................................... 641 0-output/1-output .................................... 641 16-bit access space.................................. 222 16-bit counter mode................................ 744 16-bit timer pulse unit (TPU) ................. 575 8-bit access space.................................... 221 8-bit timers (TMR) ................................. 719
B
B clock output control......................... 1176 Basic bus interface .......................... 214, 224 Big endian ............................................... 213 Bit rate..................................................... 793 Bit synchronous circuit ........................... 962 Block structure ...................................... 1009 Block transfer mode ................ 316, 396, 490 Boot mode................................... 1006, 1036 Boundary scan commands .................... 1107 Buffer operation ...................................... 646 Bulk-in transfer ....................................... 917 Bulk-out transfer ..................................... 916 Burst access mode................................... 322 Burst mode.............................................. 401 Burst ROM interface....................... 214, 245 Bus access modes.................................... 321 Bus arbitration......................................... 276 Bus configuration.................................... 202 Bus controller (BSC)............................... 177 Bus cycle division ................................... 484 Bus mode ................................................ 400 Bus width ................................................ 213 Bus-released state...................................... 69 Byte control SRAM interface ......... 214, 237
A
A/D conversion accuracy........................ 988 Absolute accuracy................................... 988 Acknowledge .......................................... 948 Address error .......................................... 112 Address map ............................................. 79 Address mode ......................................... 440 Address modes................................ 310, 390 Address/data multiplexed I/O interface .......................................... 215, 250 All-module-clock-stop mode ...... 1130, 1154 Area 0 ..................................................... 216 Area 1 ..................................................... 217 Area 2 ..................................................... 217 Area 3 ..................................................... 218 Area 4 ..................................................... 218 Area 5 ..................................................... 219 Area 6 ..................................................... 220 Area 7 ..................................................... 220 Area division........................................... 210 Asynchronous mode ............................... 810 AT-cut parallel-resonance type............. 1122 Available output signal and settings in each port ................................................. 550 Average transfer rate generator............... 766
C
Cascaded connection............................... 744 Cascaded operation ................................. 650 Chain transfer.......................................... 491 Chip select signals................................... 211 Clock pulse generator ........................... 1117 Clock synchronization cycle (Tsy).......... 204 Clocked synchronous mode .................... 827 Cluster transfer dual address mode ......... 440 Cluster transfer modes ............................ 389
Rev. 2.00 Sep. 25, 2008 Page 1333 of 1340 REJ09B0413-0200
Cluster transfer read address mode......... 442 Cluster transfer write address mode ....... 444 Communications protocol..................... 1073 Compare match A................................... 742 Compare match B ................................... 743 Compare match count mode ................... 745 Compare match signal ............................ 742 Control transfer....................................... 910 Counter operation ................................... 638 CPU priority control function over DTC and DMAC .................................... 158 CRC Operation Circuit ........................... 856 Crystal resonator................................... 1122 Cycle steal mode..................................... 400 Cycle stealing mode................................ 321
Extended repeat area ............................... 307 Extended repeat area function......... 323, 401 Extension of chip select (CS) assertion period ...................................................... 234 External access bus ................................. 202 External bus ............................................ 207 External bus clock (B) ................ 203, 1117 External bus interface ............................. 212 External clock ....................................... 1123 External interrupts................................... 141
F
Flash erase block select parameter........ 1034 Flash memory ....................................... 1003 Flash multipurpose address area parameter .............................................. 1032 Flash multipurpose data destination parameter .............................................. 1033 Flash pass and fail parameter ................ 1026 Flash program/erase frequency parameter .................................... 1030, 1048 Free-running count operation.................. 639 Frequency divider ....................... 1117, 1124 Full address mode ................................... 477 Full-scale error........................................ 988
D
D/A converter ......................................... 995 Data direction register ............................ 511 Data register............................................ 512 Data stage ............................................... 912 Data transfer controller (DTC) ............... 467 Direct convention ................................... 835 DMA controller (DMAC)....................... 283 Double-buffered structure....................... 810 Download pass/fail result parameter..... 1025 DTC vector address ................................ 479 DTC vector address offset ...... 479, 480, 481 Dual address mode.......................... 310, 390
G
General illegal instructions ..................... 119
E
Endian and data alignment ..................... 221 Endian format ......................................... 213 Error protection .................................... 1065 Error signal ............................................. 835 Exception handling ................................. 105 Exception-handling state .......................... 69 EXDMA controller (EXDMAC) ............ 361
Rev. 2.00 Sep. 25, 2008 Page 1334 of 1340 REJ09B0413-0200
H
Hardware protection ............................. 1064 Hardware standby mode ............. 1130, 1171
I
I/O ports .................................................. 503
I2C bus format......................................... 948 I2C bus interface2 (IIC2) ........................ 931 ID code ................................................... 821 Idle cycle ................................................ 260 Illegal instruction.................................... 119 Input buffer control register.................... 513 Input capture function............................. 642 Internal interrupts ................................... 142 Internal peripheral bus ............................ 202 Internal system bus ................................. 202 Interrupt .................................................. 116 Interrupt control mode 0 ......................... 149 Interrupt control mode 2 ......................... 151 Interrupt controller.................................. 123 Interrupt exception handling sequence ... 153 Interrupt exception handling vector table ........................................................ 143 Interrupt response times.......................... 154 Interrupt sources ..................................... 141 Interrupt sources and vector address offsets ..................................................... 143 Interrupt-in transfer................................. 919 Interval timer .......................................... 760 Interval timer mode................................. 760 Inverse convention.................................. 836 IRQn interrupts ....................................... 141
MCU operating modes .............................. 71 Memory MAT configuration ................ 1008 Mode 2 ...................................................... 77 Mode 4 ...................................................... 77 Mode 5 ...................................................... 78 Mode 6 ...................................................... 78 Mode 7 ...................................................... 78 Mode pin ................................................... 71 Multi-clock mode.................................. 1152 Multiprocessor bit ................................... 821 Multiprocessor communication function ................................................... 821
N
NMI interrupt.......................................... 141 Noise canceler......................................... 957 Nonlinearity error.................................... 988 Non-overlapping pulse output................. 709 Normal transfer mode ............................. 487 Normal transfer mode ..................... 314, 394 Number of Access Cycles ....................... 214
O
Offset addition ........................................ 326 Offset addition method ........................... 404 Offset error.............................................. 988 On-board programming ........................ 1036 On-board programming mode..... 1003, 1036 On-chip baud rate generator.................... 813 On-chip ROM disabled extended mode .... 71 On-chip ROM enabled extended mode..... 71 Open-drain control register ..................... 515 Oscillator............................................... 1122 Output buffer control .............................. 516 Output trigger.......................................... 708 Overflow ......................................... 744, 758
J
JTAG interface ....................................... 965
L
Little endian............................................ 213
M
Mark state ....................................... 810, 851 Master receive mode............................... 951 Master transmit mode ............................. 949
Rev. 2.00 Sep. 25, 2008 Page 1335 of 1340 REJ09B0413-0200
P
Package dimensions.................... 1301, 1302 Parity bit ................................................. 810 Periodic count operation......................... 639 Peripheral module clock (P) ....... 203, 1117 Phase counting mode .............................. 658 Pin assignments ........................................ 12 Pin functions............................................. 19 PLL circuit.................................. 1117, 1124 Port function controller........................... 557 Port register ............................................ 512 Power-down modes .............................. 1129 Procedure program ............................... 1058 Processing states ....................................... 69 Product lineup....................................... 1300 Program execution state............................ 69 Program stop state .................................... 69 Programmable pulse generator (PPG) .... 685 Programmer mode ...................... 1006, 1071 Programming/erasing interface............. 1012 Programming/erasing interface parameters............................................. 1023 Programming/erasing interface register .................................................. 1016 Protection.............................................. 1064 Pull-up MOS control register.................. 514 PWM modes ........................................... 652
Q
Quantization error................................... 988
R
RAM..................................................... 1001 Read strobe (RD) timing......................... 233 Register addresses ................................... 1180 Register Bits ........................................... 1199 Register configuration in each port......... 510
Registers ABWCR.............................................. 181 ADCSR ............................................... 971 ASTCR ............................................... 182 BAMRAH......................................... 1183 BAMRAL ......................................... 1183 BAMRBH ......................................... 1183 BAMRBL ......................................... 1183 BAMRCH ......................................... 1183 BARAH ............................................ 1183 BARAL............................................. 1183 BARBH............................................. 1183 BARBL ............................................. 1183 BARCH............................................. 1183 BARCL ............................................. 1183 BCR1 .................................................. 194 BCR2 .................................................. 196 BROMCR ........................................... 199 BRR .................................................... 793 CCR ...................................................... 37 CLSBR................................................ 387 CPUPCR ............................................. 127 CRA .................................................... 473 CRB .................................................... 474 CRCCR ............................................... 857 CRCDIR ............................................. 858 CRCDOR............................................ 858 CSACR ............................................... 189 CTLR .................................................. 888 CVR .................................................... 888 DACR ................................................. 302 DACR01 ............................................. 997 DADR0 ............................................... 996 DADR1 ............................................... 996 DAR.................................................... 473 DASTS................................................ 882 DBSR.................................................. 292 DDAR ................................................. 289 DDR.................................................... 511 DMA ................................................... 884
Rev. 2.00 Sep. 25, 2008 Page 1336 of 1340 REJ09B0413-0200
DMDR ................................................ 293 DMRSR .............................................. 308 DOFR ................................................. 290 DPFR ................................................ 1025 DR....................................................... 512 DSAR ................................................. 288 DTCCR............................................... 475 DTCER ............................................... 474 DTCR ................................................. 291 DTCVBR............................................ 477 EDACR............................................... 381 EDBSR ............................................... 371 EDDAR .............................................. 368 EDMDR.............................................. 372 EDOFR ............................................... 369 EDSAR ............................................... 367 EDTCR ............................................... 370 ENDIANCR........................................ 197 EPDR.................................................. 878 EPDR0i............................................... 876 EPDR0o.............................................. 877 EPDR0s .............................................. 877 EPIR ................................................... 890 EPSTL ................................................ 887 EPSZ0o............................................... 879 EPSZ1................................................. 880 EXR ...................................................... 38 FCCS ................................................ 1016 FCLR .................................................. 883 FEBS................................................. 1034 FECS................................................. 1019 FKEY................................................ 1020 FMATS............................................. 1021 FMPAR............................................. 1032 FMPDR............................................. 1033 FPCS................................................. 1019 FPEFEQ.................................. 1030, 1048 FPFR................................................. 1026 FTDAR ............................................. 1022 General registers ................................... 35
ICCRA ................................................ 935 ICCRB ................................................ 937 ICDRR ................................................ 947 ICDRS................................................. 947 ICDRT ................................................ 947 ICIER .................................................. 940 ICMR .................................................. 939 ICR...................................................... 513 ICSR.................................................... 943 IDLCR ................................................ 192 IER...................................................... 131 IER (USB)........................................... 874 IFR (USB)........................................... 866 INTCR ................................................ 126 IPR ...................................................... 129 IrCR .................................................... 809 ISCRH................................................. 133 ISCRL ................................................. 133 ISR ...................................................... 138 ISR (USB)........................................... 871 LVDCR................................................. 98 MAC ..................................................... 39 MDCR................................................... 73 MPXCR .............................................. 201 MRA ................................................... 470 MRB.................................................... 471 MSTPCRA........................................ 1136 MSTPCRB ........................................ 1136 MSTPCRC ........................................ 1139 NDERH............................................... 690 NDERL ............................................... 690 NDRH ................................................. 695 NDRL.................................................. 695 ODR.................................................... 515 PC ......................................................... 36 PCR..................................................... 699 PCR (I/O port)..................................... 514 PFCR0................................................. 558 PFCR1................................................. 559 PFCR2................................................. 560
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PFCR4 ................................................ 562 PFCR6 ................................................ 563 PFCR7 ................................................ 564 PFCR9 ................................................ 566 PFCRB................................................ 569 PFCRC................................................ 571 PMR.................................................... 701 PODRH .............................................. 692 PODRL ............................................... 692 PORT.................................................. 512 RAMER............................................ 1035 RDNCR .............................................. 188 RDR.................................................... 773 RSR .................................................... 773 RSTCSR ............................................. 757 RSTSR.................................................. 99 SAR ............................................ 472, 946 SBR ...................................................... 39 SBYCR............................................. 1133 SCKCR............................................. 1119 SCMR................................................. 792 SCR .................................................... 778 SDBPR ............................................. 1107 SDBSR ............................................. 1107 SDID................................................. 1112 SEMR ................................................. 800 SMR.................................................... 774 SRAMCR ........................................... 198 SSIER ................................................. 140 SSR..................................................... 783 SYSCR ................................................. 75 TCCR.................................................. 730 TCNT.................................................. 635 TCNT (TMR) ..................................... 727 TCNT (WDT)..................................... 755 TCORA .............................................. 727 TCORB............................................... 728 TCR .................................................... 589 TCR (TMR) ........................................ 728 TCSR (TMR)...................................... 735
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TCSR (WDT)...................................... 755 TDR .................................................... 774 TGR .................................................... 635 TIER ................................................... 630 TIOR ................................................... 596 TMDR................................................. 594 TRG .................................................... 880 TRNTREG .......................................... 894 TSR ............................................. 631, 774 TSTR................................................... 636 TSYR .................................................. 637 VBR ...................................................... 39 WTCRA.............................................. 183 WTCRB .............................................. 183 Repeat transfer mode .............. 315, 395, 488 Reset ....................................................... 108 Reset state ................................................. 69 Resolution ............................................... 988
S
Sample-and-hold circuit.......................... 983 Scan mode............................................... 980 Serial communication interface (SCI)..... 765 Setup stage .............................................. 911 Short address mode ................................. 477 Single address mode ....................... 311, 391 Single mode ............................................ 979 Slave receive mode ................................. 956 Slave transmit mode................................ 953 Sleep mode.................................. 1130, 1153 Slot illegal instructions ........................... 119 Smart card interface ................................ 834 Software protection............................... 1065 Software standby mode............... 1130, 1155 Space state .............................................. 810 Stack status after exception handling...... 120 Stall operations ....................................... 921 Standard serial communication interface specifications for boot mode................. 1071
Start bit ................................................... 810 State transition of TAP controller......... 1113 State transitions......................................... 70 Status stage ............................................. 914 Stop bit.................................................... 810 Strobe assert/negate timing..................... 216 Synchronous clearing.............................. 644 Synchronous operation ........................... 644 Synchronous presetting........................... 644 System clock (I).......................... 203, 1117
U
USB function module ............................. 863 USB standard commands ........................ 920 User boot MAT ..................................... 1008 User boot mode ........................... 1006, 1054 User break controller (UBC)................... 165 User MAT ............................................. 1008 User program mode..................... 1006, 1044
V T
TAP controller ...................................... 1113 Toggle output.......................................... 641 Trace exception handling........................ 111 Transfer information............................... 477 Transfer information read skip function................................................... 486 Transfer information writeback skip function................................................... 487 Transfer modes ............................... 314, 394 Transmit/receive data.............................. 810 Trap instruction exception handling ....... 117 Vector table address................................ 106 Vector table address offset...................... 106 Voltage Detection Circuit (LVD).............. 97
W
Wait control ............................................ 231 Watchdog timer (WDT) .......................... 753 Watchdog timer mode............................. 758 Waveform output by compare match...... 640 Write data buffer function....................... 274 Write data buffer function for external data bus ................................................... 274 Write data buffer function for peripheral modules.................................. 275
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Rev. 2.00 Sep. 25, 2008 Page 1340 of 1340 REJ09B0413-0200
Renesas 32-Bit CISC Microcomputer Hardware Manual H8SX/1658R Group, H8SX/1658M Group
Publication Date: Rev.1.00, Feb. 22, 2008 Rev.2.00, Sep 25, 2008 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp.
2008. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
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Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7858/7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2377-3473 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 3518-3399 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
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Colophon 6.2
H8SX/1658R Group, H8SX/1658M Group Hardware Manual

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